1 // SPDX-License-Identifier: GPL-2.0+
3 * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
5 * Watchdog driver for AT91SAM9x processors.
7 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
12 * The Watchdog Timer Mode Register can be only written to once. If the
13 * timeout need to be set from U-Boot, be sure that the bootstrap doesn't
14 * write to this register. Inform Linux to it too
18 #include <asm/arch/at91_wdt.h>
25 DECLARE_GLOBAL_DATA_PTR;
28 * AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
29 * use this to convert a watchdog
32 #define WDT_SEC2TICKS(s) (((s) << 8) - 1)
34 /* Hardware timeout in seconds */
35 #define WDT_MAX_TIMEOUT 16
36 #define WDT_DEFAULT_TIMEOUT 2
38 struct at91_wdt_priv {
45 * Set the watchdog time interval in 1/256Hz (write-once)
48 static int at91_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
50 struct at91_wdt_priv *priv = dev_get_priv(dev);
54 /* Calculate timeout in seconds and the resulting ticks */
56 do_div(timeout, 1000);
57 timeout = min_t(u64, timeout, WDT_MAX_TIMEOUT);
58 ticks = WDT_SEC2TICKS(timeout);
60 /* Check if disabled */
61 if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) {
62 printf("sorry, watchdog is disabled\n");
67 * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
69 * Since WDV is a 12-bit counter, the maximum period is
70 * 4096 / 256 = 16 seconds.
72 priv->regval = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
73 | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
74 | AT91_WDT_MR_WDD(0xfff) /* restart at any time */
75 | AT91_WDT_MR_WDV(ticks); /* timer value */
76 writel(priv->regval, priv->regs + AT91_WDT_MR);
81 static int at91_wdt_stop(struct udevice *dev)
83 struct at91_wdt_priv *priv = dev_get_priv(dev);
85 /* Disable Watchdog Timer */
86 priv->regval |= AT91_WDT_MR_WDDIS;
87 writel(priv->regval, priv->regs + AT91_WDT_MR);
92 static int at91_wdt_reset(struct udevice *dev)
94 struct at91_wdt_priv *priv = dev_get_priv(dev);
96 writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, priv->regs + AT91_WDT_CR);
101 static const struct wdt_ops at91_wdt_ops = {
102 .start = at91_wdt_start,
103 .stop = at91_wdt_stop,
104 .reset = at91_wdt_reset,
107 static const struct udevice_id at91_wdt_ids[] = {
108 { .compatible = "atmel,at91sam9260-wdt" },
112 static int at91_wdt_probe(struct udevice *dev)
114 struct at91_wdt_priv *priv = dev_get_priv(dev);
116 priv->regs = dev_remap_addr(dev);
120 #if CONFIG_IS_ENABLED(OF_CONTROL)
121 priv->timeout = dev_read_u32_default(dev, "timeout-sec",
122 WDT_DEFAULT_TIMEOUT);
123 debug("%s: timeout %d", __func__, priv->timeout);
125 priv->timeout = WDT_DEFAULT_TIMEOUT;
128 debug("%s: Probing wdt%u\n", __func__, dev->seq);
133 U_BOOT_DRIVER(at91_wdt) = {
136 .of_match = at91_wdt_ids,
137 .priv_auto_alloc_size = sizeof(struct at91_wdt_priv),
138 .ops = &at91_wdt_ops,
139 .probe = at91_wdt_probe,