drivers/video/tegra124/sor.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2011-2013, NVIDIA Corporation.
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <errno.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <panel.h>
  12 #include <syscon.h>
  13 #include <video_bridge.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch-tegra/dc.h>
  17 #include "displayport.h"
  18 #include "sor.h"
  19 #include <linux/err.h>
  20
  21 #define DEBUG_SOR 0
  22
  23 #define APBDEV_PMC_DPD_SAMPLE                           0x20
  24 #define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE                0
  25 #define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE                 1
  26 #define APBDEV_PMC_SEL_DPD_TIM                          0x1c8
  27 #define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT      0x7f
  28 #define APBDEV_PMC_IO_DPD2_REQ                          0x1c0
  29 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT               25
  30 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF                 (0 << 25)
  31 #define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON                  (1 << 25)
  32 #define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT               30
  33 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK        (0x3 << 30)
  34 #define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE                (0 << 30)
  35 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF             (1 << 30)
  36 #define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON              (2 << 30)
  37 #define APBDEV_PMC_IO_DPD2_STATUS                       0x1c4
  38 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT            25
  39 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF              (0 << 25)
  40 #define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON               (1 << 25)
  41
  42 struct tegra_dc_sor_data {
  43         void *base;
  44         void *pmc_base;
  45         u8 portnum;     /* 0 or 1 */
  46         int power_is_up;
  47         struct udevice *panel;
  48 };
  49
  50 static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
  51 {
  52         return readl((u32 *)sor->base + reg);
  53 }
  54
  55 static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg,
  56                                     u32 val)
  57 {
  58         writel(val, (u32 *)sor->base + reg);
  59 }
  60
  61 static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
  62         u32 reg, u32 mask, u32 val)
  63 {
  64         u32 reg_val = tegra_sor_readl(sor, reg);
  65         reg_val &= ~mask;
  66         reg_val |= val;
  67         tegra_sor_writel(sor, reg, reg_val);
  68 }
  69
  70 void tegra_dp_disable_tx_pu(struct udevice *dev)
  71 {
  72         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  73
  74         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
  75                               DP_PADCTL_TX_PU_MASK, DP_PADCTL_TX_PU_DISABLE);
  76 }
  77
  78 void tegra_dp_set_pe_vs_pc(struct udevice *dev, u32 mask, u32 pe_reg,
  79                            u32 vs_reg, u32 pc_reg, u8 pc_supported)
  80 {
  81         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
  82
  83         tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg);
  84         tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg);
  85         if (pc_supported) {
  86                 tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask,
  87                                       pc_reg);
  88         }
  89 }
  90
  91 static int tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg,
  92                                       u32 mask, u32 exp_val,
  93                                       int poll_interval_us, int timeout_ms)
  94 {
  95         u32 reg_val = 0;
  96         ulong start;
  97
  98         start = get_timer(0);
  99         do {
 100                 reg_val = tegra_sor_readl(sor, reg);
 101                 if (((reg_val & mask) == exp_val))
 102                         return 0;
 103                 udelay(poll_interval_us);
 104         } while (get_timer(start) < timeout_ms);
 105
 106         debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n",
 107               reg, reg_val, mask, exp_val);
 108
 109         return -ETIMEDOUT;
 110 }
 111
 112 int tegra_dc_sor_set_power_state(struct udevice *dev, int pu_pd)
 113 {
 114         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 115         u32 reg_val;
 116         u32 orig_val;
 117
 118         orig_val = tegra_sor_readl(sor, PWR);
 119
 120         reg_val = pu_pd ? PWR_NORMAL_STATE_PU :
 121                 PWR_NORMAL_STATE_PD; /* normal state only */
 122
 123         if (reg_val == orig_val)
 124                 return 0;       /* No update needed */
 125
 126         reg_val |= PWR_SETTING_NEW_TRIGGER;
 127         tegra_sor_writel(sor, PWR, reg_val);
 128
 129         /* Poll to confirm it is done */
 130         if (tegra_dc_sor_poll_register(sor, PWR,
 131                                        PWR_SETTING_NEW_DEFAULT_MASK,
 132                                        PWR_SETTING_NEW_DONE,
 133                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 134                 debug("dc timeout waiting for SOR_PWR = NEW_DONE\n");
 135                 return -EFAULT;
 136         }
 137
 138         return 0;
 139 }
 140
 141 void tegra_dc_sor_set_dp_linkctl(struct udevice *dev, int ena,
 142                                  u8 training_pattern,
 143                                  const struct tegra_dp_link_config *link_cfg)
 144 {
 145         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 146         u32 reg_val;
 147
 148         reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
 149
 150         if (ena)
 151                 reg_val |= DP_LINKCTL_ENABLE_YES;
 152         else
 153                 reg_val &= DP_LINKCTL_ENABLE_NO;
 154
 155         reg_val &= ~DP_LINKCTL_TUSIZE_MASK;
 156         reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT);
 157
 158         if (link_cfg->enhanced_framing)
 159                 reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE;
 160
 161         tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
 162
 163         switch (training_pattern) {
 164         case training_pattern_1:
 165                 tegra_sor_writel(sor, DP_TPG, 0x41414141);
 166                 break;
 167         case training_pattern_2:
 168         case training_pattern_3:
 169                 reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?
 170                         0x43434343 : 0x42424242;
 171                 tegra_sor_writel(sor, DP_TPG, reg_val);
 172                 break;
 173         default:
 174                 tegra_sor_writel(sor, DP_TPG, 0x50505050);
 175                 break;
 176         }
 177 }
 178
 179 static int tegra_dc_sor_enable_lane_sequencer(struct tegra_dc_sor_data *sor,
 180                                               int pu, int is_lvds)
 181 {
 182         u32 reg_val;
 183
 184         /* SOR lane sequencer */
 185         if (pu) {
 186                 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 187                         LANE_SEQ_CTL_SEQUENCE_DOWN |
 188                         LANE_SEQ_CTL_NEW_POWER_STATE_PU;
 189         } else {
 190                 reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |
 191                         LANE_SEQ_CTL_SEQUENCE_UP |
 192                         LANE_SEQ_CTL_NEW_POWER_STATE_PD;
 193         }
 194
 195         if (is_lvds)
 196                 reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT;
 197         else
 198                 reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT;
 199
 200         tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val);
 201
 202         if (tegra_dc_sor_poll_register(sor, LANE_SEQ_CTL,
 203                                        LANE_SEQ_CTL_SETTING_MASK,
 204                                        LANE_SEQ_CTL_SETTING_NEW_DONE,
 205                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 206                 debug("dp: timeout while waiting for SOR lane sequencer to power down lanes\n");
 207                 return -1;
 208         }
 209
 210         return 0;
 211 }
 212
 213 static int tegra_dc_sor_power_dplanes(struct udevice *dev,
 214                                       u32 lane_count, int pu)
 215 {
 216         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 217         u32 reg_val;
 218
 219         reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
 220
 221         if (pu) {
 222                 switch (lane_count) {
 223                 case 4:
 224                         reg_val |= (DP_PADCTL_PD_TXD_3_NO |
 225                                 DP_PADCTL_PD_TXD_2_NO);
 226                         /* fall through */
 227                 case 2:
 228                         reg_val |= DP_PADCTL_PD_TXD_1_NO;
 229                 case 1:
 230                         reg_val |= DP_PADCTL_PD_TXD_0_NO;
 231                         break;
 232                 default:
 233                         debug("dp: invalid lane number %d\n", lane_count);
 234                         return -1;
 235                 }
 236
 237                 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
 238                 tegra_dc_sor_set_lane_count(dev, lane_count);
 239         }
 240
 241         return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
 242 }
 243
 244 void tegra_dc_sor_set_panel_power(struct udevice *dev, int power_up)
 245 {
 246         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 247         u32 reg_val;
 248
 249         reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
 250
 251         if (power_up)
 252                 reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP;
 253         else
 254                 reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP;
 255
 256         tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
 257 }
 258
 259 static void tegra_dc_sor_config_pwm(struct tegra_dc_sor_data *sor, u32 pwm_div,
 260                                     u32 pwm_dutycycle)
 261 {
 262         tegra_sor_writel(sor, PWM_DIV, pwm_div);
 263         tegra_sor_writel(sor, PWM_CTL,
 264                          (pwm_dutycycle & PWM_CTL_DUTY_CYCLE_MASK) |
 265                          PWM_CTL_SETTING_NEW_TRIGGER);
 266
 267         if (tegra_dc_sor_poll_register(sor, PWM_CTL,
 268                                        PWM_CTL_SETTING_NEW_SHIFT,
 269                                        PWM_CTL_SETTING_NEW_DONE,
 270                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 271                 debug("dp: timeout while waiting for SOR PWM setting\n");
 272         }
 273 }
 274
 275 static void tegra_dc_sor_set_dp_mode(struct udevice *dev,
 276                                 const struct tegra_dp_link_config *link_cfg)
 277 {
 278         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 279         u32 reg_val;
 280
 281         tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);
 282
 283         tegra_dc_sor_set_dp_linkctl(dev, 1, training_pattern_none, link_cfg);
 284         reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));
 285         reg_val &= ~DP_CONFIG_WATERMARK_MASK;
 286         reg_val |= link_cfg->watermark;
 287         reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK;
 288         reg_val |= (link_cfg->active_count <<
 289                 DP_CONFIG_ACTIVESYM_COUNT_SHIFT);
 290         reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK;
 291         reg_val |= (link_cfg->active_frac <<
 292                 DP_CONFIG_ACTIVESYM_FRAC_SHIFT);
 293         if (link_cfg->activepolarity)
 294                 reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 295         else
 296                 reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;
 297         reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE |
 298                 DP_CONFIG_RD_RESET_VAL_NEGATIVE);
 299
 300         tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);
 301
 302         /* program h/vblank sym */
 303         tegra_sor_write_field(sor, DP_AUDIO_HBLANK_SYMBOLS,
 304                               DP_AUDIO_HBLANK_SYMBOLS_MASK,
 305                               link_cfg->hblank_sym);
 306
 307         tegra_sor_write_field(sor, DP_AUDIO_VBLANK_SYMBOLS,
 308                               DP_AUDIO_VBLANK_SYMBOLS_MASK,
 309                               link_cfg->vblank_sym);
 310 }
 311
 312 static inline void tegra_dc_sor_super_update(struct tegra_dc_sor_data *sor)
 313 {
 314         tegra_sor_writel(sor, SUPER_STATE0, 0);
 315         tegra_sor_writel(sor, SUPER_STATE0, 1);
 316         tegra_sor_writel(sor, SUPER_STATE0, 0);
 317 }
 318
 319 static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
 320 {
 321         tegra_sor_writel(sor, STATE0, 0);
 322         tegra_sor_writel(sor, STATE0, 1);
 323         tegra_sor_writel(sor, STATE0, 0);
 324 }
 325
 326 static int tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
 327 {
 328         u32 reg_val;
 329         void *pmc_base = sor->pmc_base;
 330
 331         if (up) {
 332                 writel(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
 333                        pmc_base + APBDEV_PMC_DPD_SAMPLE);
 334                 writel(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
 335         }
 336
 337         reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 338         reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
 339                         APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
 340
 341         reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
 342                         APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
 343                         APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
 344                         APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
 345
 346         writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
 347
 348         /* Polling */
 349         u32 temp = 10 * 1000;
 350         do {
 351                 udelay(20);
 352                 reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
 353                 if (temp > 20)
 354                         temp -= 20;
 355                 else
 356                         break;
 357         } while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
 358
 359         if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) {
 360                 debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
 361                 return -EIO;
 362         }
 363
 364         if (up) {
 365                 writel(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
 366                        pmc_base + APBDEV_PMC_DPD_SAMPLE);
 367         }
 368
 369         return 0;
 370 }
 371
 372 void tegra_dc_sor_set_internal_panel(struct udevice *dev, int is_int)
 373 {
 374         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 375         u32 reg_val;
 376
 377         reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));
 378         if (is_int)
 379                 reg_val |= DP_SPARE_PANEL_INTERNAL;
 380         else
 381                 reg_val &= ~DP_SPARE_PANEL_INTERNAL;
 382
 383         reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |
 384                 DP_SPARE_SEQ_ENABLE_YES;
 385         tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);
 386 }
 387
 388 void tegra_dc_sor_read_link_config(struct udevice *dev, u8 *link_bw,
 389                                    u8 *lane_count)
 390 {
 391         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 392         u32 reg_val;
 393
 394         reg_val = tegra_sor_readl(sor, CLK_CNTRL);
 395         *link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK)
 396                 >> CLK_CNTRL_DP_LINK_SPEED_SHIFT;
 397         reg_val = tegra_sor_readl(sor,
 398                 DP_LINKCTL(sor->portnum));
 399
 400         switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) {
 401         case DP_LINKCTL_LANECOUNT_ZERO:
 402                 *lane_count = 0;
 403                 break;
 404         case DP_LINKCTL_LANECOUNT_ONE:
 405                 *lane_count = 1;
 406                 break;
 407         case DP_LINKCTL_LANECOUNT_TWO:
 408                 *lane_count = 2;
 409                 break;
 410         case DP_LINKCTL_LANECOUNT_FOUR:
 411                 *lane_count = 4;
 412                 break;
 413         default:
 414                 printf("Unknown lane count\n");
 415         }
 416 }
 417
 418 void tegra_dc_sor_set_link_bandwidth(struct udevice *dev, u8 link_bw)
 419 {
 420         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 421
 422         tegra_sor_write_field(sor, CLK_CNTRL,
 423                               CLK_CNTRL_DP_LINK_SPEED_MASK,
 424                               link_bw << CLK_CNTRL_DP_LINK_SPEED_SHIFT);
 425 }
 426
 427 void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count)
 428 {
 429         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 430         u32 reg_val;
 431
 432         reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));
 433         reg_val &= ~DP_LINKCTL_LANECOUNT_MASK;
 434         switch (lane_count) {
 435         case 0:
 436                 break;
 437         case 1:
 438                 reg_val |= DP_LINKCTL_LANECOUNT_ONE;
 439                 break;
 440         case 2:
 441                 reg_val |= DP_LINKCTL_LANECOUNT_TWO;
 442                 break;
 443         case 4:
 444                 reg_val |= DP_LINKCTL_LANECOUNT_FOUR;
 445                 break;
 446         default:
 447                 /* 0 should be handled earlier. */
 448                 printf("dp: Invalid lane count %d\n", lane_count);
 449                 return;
 450         }
 451         tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);
 452 }
 453
 454 /*
 455  * The SOR power sequencer does not work for t124 so SW has to
 456  *  go through the power sequence manually
 457  * Power up steps from spec:
 458  * STEP PDPORT  PDPLL   PDBG    PLLVCOD PLLCAPD E_DPD   PDCAL
 459  * 1    1       1       1       1       1       1       1
 460  * 2    1       1       1       1       1       0       1
 461  * 3    1       1       0       1       1       0       1
 462  * 4    1       0       0       0       0       0       1
 463  * 5    0       0       0       0       0       0       1
 464  */
 465 static int tegra_dc_sor_power_up(struct udevice *dev, int is_lvds)
 466 {
 467         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 468         u32 reg;
 469         int ret;
 470
 471         if (sor->power_is_up)
 472                 return 0;
 473
 474         /*
 475          * If for some reason it is already powered up, don't do it again.
 476          * This can happen if U-Boot is the secondary boot loader.
 477          */
 478         reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
 479         if (reg & DP_PADCTL_PD_TXD_0_NO)
 480                 return 0;
 481
 482         /* Set link bw */
 483         tegra_dc_sor_set_link_bandwidth(dev, is_lvds ?
 484                                         CLK_CNTRL_DP_LINK_SPEED_LVDS :
 485                                         CLK_CNTRL_DP_LINK_SPEED_G1_62);
 486
 487         /* step 1 */
 488         tegra_sor_write_field(sor, PLL2,
 489                               PLL2_AUX7_PORT_POWERDOWN_MASK | /* PDPORT */
 490                               PLL2_AUX6_BANDGAP_POWERDOWN_MASK | /* PDBG */
 491                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK, /* PLLCAPD */
 492                               PLL2_AUX7_PORT_POWERDOWN_ENABLE |
 493                               PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE |
 494                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE);
 495         tegra_sor_write_field(sor, PLL0, PLL0_PWR_MASK | /* PDPLL */
 496                               PLL0_VCOPD_MASK, /* PLLVCOPD */
 497                               PLL0_PWR_OFF | PLL0_VCOPD_ASSERT);
 498         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 499                               DP_PADCTL_PAD_CAL_PD_POWERDOWN, /* PDCAL */
 500                               DP_PADCTL_PAD_CAL_PD_POWERDOWN);
 501
 502         /* step 2 */
 503         ret = tegra_dc_sor_io_set_dpd(sor, 1);
 504         if (ret)
 505                 return ret;
 506         udelay(15);
 507
 508         /* step 3 */
 509         tegra_sor_write_field(sor, PLL2,
 510                               PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
 511                               PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
 512         udelay(25);
 513
 514         /* step 4 */
 515         tegra_sor_write_field(sor, PLL0,
 516                               PLL0_PWR_MASK | /* PDPLL */
 517                               PLL0_VCOPD_MASK, /* PLLVCOPD */
 518                               PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
 519         /* PLLCAPD */
 520         tegra_sor_write_field(sor, PLL2,
 521                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 522                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
 523         udelay(225);
 524
 525         /* step 5 PDPORT */
 526         tegra_sor_write_field(sor, PLL2,
 527                               PLL2_AUX7_PORT_POWERDOWN_MASK,
 528                               PLL2_AUX7_PORT_POWERDOWN_DISABLE);
 529
 530         sor->power_is_up = 1;
 531
 532         return 0;
 533 }
 534
 535 #if DEBUG_SOR
 536 static void dump_sor_reg(struct tegra_dc_sor_data *sor)
 537 {
 538 #define DUMP_REG(a) printk(BIOS_INFO, \
 539                 "%-32s  %03x  %08x\n",          \
 540                 #a, a, tegra_sor_readl(sor, a));
 541
 542         DUMP_REG(SUPER_STATE0);
 543         DUMP_REG(SUPER_STATE1);
 544         DUMP_REG(STATE0);
 545         DUMP_REG(STATE1);
 546         DUMP_REG(NV_HEAD_STATE0(0));
 547         DUMP_REG(NV_HEAD_STATE0(1));
 548         DUMP_REG(NV_HEAD_STATE1(0));
 549         DUMP_REG(NV_HEAD_STATE1(1));
 550         DUMP_REG(NV_HEAD_STATE2(0));
 551         DUMP_REG(NV_HEAD_STATE2(1));
 552         DUMP_REG(NV_HEAD_STATE3(0));
 553         DUMP_REG(NV_HEAD_STATE3(1));
 554         DUMP_REG(NV_HEAD_STATE4(0));
 555         DUMP_REG(NV_HEAD_STATE4(1));
 556         DUMP_REG(NV_HEAD_STATE5(0));
 557         DUMP_REG(NV_HEAD_STATE5(1));
 558         DUMP_REG(CRC_CNTRL);
 559         DUMP_REG(CLK_CNTRL);
 560         DUMP_REG(CAP);
 561         DUMP_REG(PWR);
 562         DUMP_REG(TEST);
 563         DUMP_REG(PLL0);
 564         DUMP_REG(PLL1);
 565         DUMP_REG(PLL2);
 566         DUMP_REG(PLL3);
 567         DUMP_REG(CSTM);
 568         DUMP_REG(LVDS);
 569         DUMP_REG(CRCA);
 570         DUMP_REG(CRCB);
 571         DUMP_REG(SEQ_CTL);
 572         DUMP_REG(LANE_SEQ_CTL);
 573         DUMP_REG(SEQ_INST(0));
 574         DUMP_REG(SEQ_INST(1));
 575         DUMP_REG(SEQ_INST(2));
 576         DUMP_REG(SEQ_INST(3));
 577         DUMP_REG(SEQ_INST(4));
 578         DUMP_REG(SEQ_INST(5));
 579         DUMP_REG(SEQ_INST(6));
 580         DUMP_REG(SEQ_INST(7));
 581         DUMP_REG(SEQ_INST(8));
 582         DUMP_REG(PWM_DIV);
 583         DUMP_REG(PWM_CTL);
 584         DUMP_REG(MSCHECK);
 585         DUMP_REG(XBAR_CTRL);
 586         DUMP_REG(DP_LINKCTL(0));
 587         DUMP_REG(DP_LINKCTL(1));
 588         DUMP_REG(DC(0));
 589         DUMP_REG(DC(1));
 590         DUMP_REG(LANE_DRIVE_CURRENT(0));
 591         DUMP_REG(PR(0));
 592         DUMP_REG(LANE4_PREEMPHASIS(0));
 593         DUMP_REG(POSTCURSOR(0));
 594         DUMP_REG(DP_CONFIG(0));
 595         DUMP_REG(DP_CONFIG(1));
 596         DUMP_REG(DP_MN(0));
 597         DUMP_REG(DP_MN(1));
 598         DUMP_REG(DP_PADCTL(0));
 599         DUMP_REG(DP_PADCTL(1));
 600         DUMP_REG(DP_DEBUG(0));
 601         DUMP_REG(DP_DEBUG(1));
 602         DUMP_REG(DP_SPARE(0));
 603         DUMP_REG(DP_SPARE(1));
 604         DUMP_REG(DP_TPG);
 605
 606         return;
 607 }
 608 #endif
 609
 610 static void tegra_dc_sor_config_panel(struct tegra_dc_sor_data *sor,
 611                         int is_lvds,
 612                         const struct tegra_dp_link_config *link_cfg,
 613                         const struct display_timing *timing)
 614 {
 615         const int       head_num = 0;
 616         u32             reg_val  = STATE1_ASY_OWNER_HEAD0 << head_num;
 617         u32             vtotal, htotal;
 618         u32             vsync_end, hsync_end;
 619         u32             vblank_end, hblank_end;
 620         u32             vblank_start, hblank_start;
 621
 622         reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM :
 623                 STATE1_ASY_PROTOCOL_DP_A;
 624         reg_val |= STATE1_ASY_SUBOWNER_NONE |
 625                 STATE1_ASY_CRCMODE_COMPLETE_RASTER;
 626
 627         reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;
 628         reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;
 629         reg_val |= (link_cfg->bits_per_pixel > 18) ?
 630                 STATE1_ASY_PIXELDEPTH_BPP_24_444 :
 631                 STATE1_ASY_PIXELDEPTH_BPP_18_444;
 632
 633         tegra_sor_writel(sor, STATE1, reg_val);
 634
 635         /*
 636          * Skipping programming NV_HEAD_STATE0, assuming:
 637          * interlacing: PROGRESSIVE, dynamic range: VESA, colorspace: RGB
 638          */
 639         vtotal = timing->vsync_len.typ + timing->vback_porch.typ +
 640                 timing->vactive.typ + timing->vfront_porch.typ;
 641         htotal = timing->hsync_len.typ + timing->hback_porch.typ +
 642                 timing->hactive.typ + timing->hfront_porch.typ;
 643
 644         tegra_sor_writel(sor, NV_HEAD_STATE1(head_num),
 645                          vtotal << NV_HEAD_STATE1_VTOTAL_SHIFT |
 646                          htotal << NV_HEAD_STATE1_HTOTAL_SHIFT);
 647
 648         vsync_end = timing->vsync_len.typ - 1;
 649         hsync_end = timing->hsync_len.typ - 1;
 650         tegra_sor_writel(sor, NV_HEAD_STATE2(head_num),
 651                          vsync_end << NV_HEAD_STATE2_VSYNC_END_SHIFT |
 652                          hsync_end << NV_HEAD_STATE2_HSYNC_END_SHIFT);
 653
 654         vblank_end = vsync_end + timing->vback_porch.typ;
 655         hblank_end = hsync_end + timing->hback_porch.typ;
 656         tegra_sor_writel(sor, NV_HEAD_STATE3(head_num),
 657                          vblank_end << NV_HEAD_STATE3_VBLANK_END_SHIFT |
 658                          hblank_end << NV_HEAD_STATE3_HBLANK_END_SHIFT);
 659
 660         vblank_start = vblank_end + timing->vactive.typ;
 661         hblank_start = hblank_end + timing->hactive.typ;
 662         tegra_sor_writel(sor, NV_HEAD_STATE4(head_num),
 663                          vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
 664                          hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
 665
 666         /* TODO: adding interlace mode support */
 667         tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
 668
 669         tegra_sor_write_field(sor, CSTM,
 670                               CSTM_ROTCLK_DEFAULT_MASK |
 671                               CSTM_LVDS_EN_ENABLE,
 672                               2 << CSTM_ROTCLK_SHIFT |
 673                               is_lvds ? CSTM_LVDS_EN_ENABLE :
 674                               CSTM_LVDS_EN_DISABLE);
 675
 676          tegra_dc_sor_config_pwm(sor, 1024, 1024);
 677 }
 678
 679 static void tegra_dc_sor_enable_dc(struct dc_ctlr *disp_ctrl)
 680 {
 681         u32 reg_val = readl(&disp_ctrl->cmd.state_access);
 682
 683         writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
 684         writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
 685
 686         /* Enable DC now - otherwise pure text console may not show. */
 687         writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
 688                &disp_ctrl->cmd.disp_cmd);
 689         writel(reg_val, &disp_ctrl->cmd.state_access);
 690 }
 691
 692 int tegra_dc_sor_enable_dp(struct udevice *dev,
 693                            const struct tegra_dp_link_config *link_cfg)
 694 {
 695         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 696         int ret;
 697
 698         tegra_sor_write_field(sor, CLK_CNTRL,
 699                               CLK_CNTRL_DP_CLK_SEL_MASK,
 700                               CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK);
 701
 702         tegra_sor_write_field(sor, PLL2,
 703                               PLL2_AUX6_BANDGAP_POWERDOWN_MASK,
 704                               PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE);
 705         udelay(25);
 706
 707         tegra_sor_write_field(sor, PLL3,
 708                               PLL3_PLLVDD_MODE_MASK,
 709                               PLL3_PLLVDD_MODE_V3_3);
 710         tegra_sor_writel(sor, PLL0,
 711                          0xf << PLL0_ICHPMP_SHFIT |
 712                          0x3 << PLL0_VCOCAP_SHIFT |
 713                          PLL0_PLLREG_LEVEL_V45 |
 714                          PLL0_RESISTORSEL_EXT |
 715                          PLL0_PWR_ON | PLL0_VCOPD_RESCIND);
 716         tegra_sor_write_field(sor, PLL2,
 717                               PLL2_AUX1_SEQ_MASK |
 718                               PLL2_AUX9_LVDSEN_OVERRIDE |
 719                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 720                               PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE |
 721                               PLL2_AUX9_LVDSEN_OVERRIDE |
 722                               PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE);
 723         tegra_sor_writel(sor, PLL1, PLL1_TERM_COMPOUT_HIGH |
 724                          PLL1_TMDS_TERM_ENABLE);
 725
 726         if (tegra_dc_sor_poll_register(sor, PLL2,
 727                                        PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
 728                                        PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE,
 729                                        100, TEGRA_SOR_TIMEOUT_MS)) {
 730                 printf("DP failed to lock PLL\n");
 731                 return -EIO;
 732         }
 733
 734         tegra_sor_write_field(sor, PLL2, PLL2_AUX2_MASK |
 735                               PLL2_AUX7_PORT_POWERDOWN_MASK,
 736                               PLL2_AUX2_OVERRIDE_POWERDOWN |
 737                               PLL2_AUX7_PORT_POWERDOWN_DISABLE);
 738
 739         ret = tegra_dc_sor_power_up(dev, 0);
 740         if (ret) {
 741                 debug("DP failed to power up\n");
 742                 return ret;
 743         }
 744
 745         /* re-enable SOR clock */
 746         clock_sor_enable_edp_clock();
 747
 748         /* Power up lanes */
 749         tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1);
 750
 751         tegra_dc_sor_set_dp_mode(dev, link_cfg);
 752         debug("%s ret\n", __func__);
 753
 754         return 0;
 755 }
 756
 757 int tegra_dc_sor_attach(struct udevice *dc_dev, struct udevice *dev,
 758                         const struct tegra_dp_link_config *link_cfg,
 759                         const struct display_timing *timing)
 760 {
 761         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 762         struct dc_ctlr *disp_ctrl;
 763         u32 reg_val;
 764
 765         /* Use the first display controller */
 766         debug("%s\n", __func__);
 767         disp_ctrl = (struct dc_ctlr *)dev_read_addr(dc_dev);
 768
 769         tegra_dc_sor_enable_dc(disp_ctrl);
 770         tegra_dc_sor_config_panel(sor, 0, link_cfg, timing);
 771
 772         writel(0x9f00, &disp_ctrl->cmd.state_ctrl);
 773         writel(0x9f, &disp_ctrl->cmd.state_ctrl);
 774
 775         writel(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 776                PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
 777                &disp_ctrl->cmd.disp_pow_ctrl);
 778
 779         reg_val = tegra_sor_readl(sor, TEST);
 780         if (reg_val & TEST_ATTACHED_TRUE)
 781                 return -EEXIST;
 782
 783         tegra_sor_writel(sor, SUPER_STATE1,
 784                          SUPER_STATE1_ATTACHED_NO);
 785
 786         /*
 787          * Enable display2sor clock at least 2 cycles before DC start,
 788          * to clear sor internal valid signal.
 789          */
 790         writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
 791         writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
 792         writel(0, &disp_ctrl->disp.disp_win_opt);
 793         writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
 794
 795         /* Attach head */
 796         tegra_dc_sor_update(sor);
 797         tegra_sor_writel(sor, SUPER_STATE1,
 798                          SUPER_STATE1_ATTACHED_YES);
 799         tegra_sor_writel(sor, SUPER_STATE1,
 800                          SUPER_STATE1_ATTACHED_YES |
 801                          SUPER_STATE1_ASY_HEAD_OP_AWAKE |
 802                          SUPER_STATE1_ASY_ORMODE_NORMAL);
 803         tegra_dc_sor_super_update(sor);
 804
 805         /* Enable dc */
 806         reg_val = readl(&disp_ctrl->cmd.state_access);
 807         writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
 808         writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT,
 809                &disp_ctrl->cmd.disp_cmd);
 810         writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
 811         writel(reg_val, &disp_ctrl->cmd.state_access);
 812
 813         if (tegra_dc_sor_poll_register(sor, TEST,
 814                                        TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
 815                                        TEST_ACT_HEAD_OPMODE_AWAKE,
 816                                        100,
 817                                        TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
 818                 printf("dc timeout waiting for OPMOD = AWAKE\n");
 819                 return -ETIMEDOUT;
 820         } else {
 821                 debug("%s: sor is attached\n", __func__);
 822         }
 823
 824 #if DEBUG_SOR
 825         dump_sor_reg(sor);
 826 #endif
 827         debug("%s: ret=%d\n", __func__, 0);
 828
 829         return 0;
 830 }
 831
 832 void tegra_dc_sor_set_lane_parm(struct udevice *dev,
 833                 const struct tegra_dp_link_config *link_cfg)
 834 {
 835         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 836
 837         tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
 838                          link_cfg->drive_current);
 839         tegra_sor_writel(sor, PR(sor->portnum),
 840                          link_cfg->preemphasis);
 841         tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
 842                          link_cfg->postcursor);
 843         tegra_sor_writel(sor, LVDS, 0);
 844
 845         tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);
 846         tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count);
 847
 848         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 849                               DP_PADCTL_TX_PU_ENABLE |
 850                               DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
 851                               DP_PADCTL_TX_PU_ENABLE |
 852                               2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
 853
 854         /* Precharge */
 855         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
 856         udelay(20);
 857
 858         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
 859 }
 860
 861 int tegra_dc_sor_set_voltage_swing(struct udevice *dev,
 862                                     const struct tegra_dp_link_config *link_cfg)
 863 {
 864         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 865         u32 drive_current = 0;
 866         u32 pre_emphasis = 0;
 867
 868         /* Set to a known-good pre-calibrated setting */
 869         switch (link_cfg->link_bw) {
 870         case SOR_LINK_SPEED_G1_62:
 871         case SOR_LINK_SPEED_G2_7:
 872                 drive_current = 0x13131313;
 873                 pre_emphasis = 0;
 874                 break;
 875         case SOR_LINK_SPEED_G5_4:
 876                 debug("T124 does not support 5.4G link clock.\n");
 877         default:
 878                 debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw);
 879                 return -ENOLINK;
 880         }
 881
 882         tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current);
 883         tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis);
 884
 885         return 0;
 886 }
 887
 888 void tegra_dc_sor_power_down_unused_lanes(struct udevice *dev,
 889                         const struct tegra_dp_link_config *link_cfg)
 890 {
 891         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 892         u32 pad_ctrl = 0;
 893         int err = 0;
 894
 895         switch (link_cfg->lane_count) {
 896         case 4:
 897                 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
 898                         DP_PADCTL_PD_TXD_1_NO |
 899                         DP_PADCTL_PD_TXD_2_NO |
 900                         DP_PADCTL_PD_TXD_3_NO;
 901                 break;
 902         case 2:
 903                 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
 904                         DP_PADCTL_PD_TXD_1_NO |
 905                         DP_PADCTL_PD_TXD_2_YES |
 906                         DP_PADCTL_PD_TXD_3_YES;
 907                 break;
 908         case 1:
 909                 pad_ctrl = DP_PADCTL_PD_TXD_0_NO |
 910                         DP_PADCTL_PD_TXD_1_YES |
 911                         DP_PADCTL_PD_TXD_2_YES |
 912                         DP_PADCTL_PD_TXD_3_YES;
 913                 break;
 914         default:
 915                 printf("Invalid sor lane count: %u\n", link_cfg->lane_count);
 916                 return;
 917         }
 918
 919         pad_ctrl |= DP_PADCTL_PAD_CAL_PD_POWERDOWN;
 920         tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);
 921
 922         err = tegra_dc_sor_enable_lane_sequencer(sor, 0, 0);
 923         if (err) {
 924                 debug("Wait for lane power down failed: %d\n", err);
 925                 return;
 926         }
 927 }
 928
 929 int tegra_sor_precharge_lanes(struct udevice *dev,
 930                               const struct tegra_dp_link_config *cfg)
 931 {
 932         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 933         u32 val = 0;
 934
 935         switch (cfg->lane_count) {
 936         case 4:
 937                 val |= (DP_PADCTL_PD_TXD_3_NO |
 938                         DP_PADCTL_PD_TXD_2_NO);
 939                 /* fall through */
 940         case 2:
 941                 val |= DP_PADCTL_PD_TXD_1_NO;
 942                 /* fall through */
 943         case 1:
 944                 val |= DP_PADCTL_PD_TXD_0_NO;
 945                 break;
 946         default:
 947                 debug("dp: invalid lane number %d\n", cfg->lane_count);
 948                 return -EINVAL;
 949         }
 950
 951         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 952                               (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
 953                               (val << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT));
 954         udelay(100);
 955         tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
 956                               (0xf << DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT),
 957                               0);
 958
 959         return 0;
 960 }
 961
 962 static void tegra_dc_sor_enable_sor(struct dc_ctlr *disp_ctrl, bool enable)
 963 {
 964         u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt);
 965
 966         reg_val = enable ? reg_val | SOR_ENABLE : reg_val & ~SOR_ENABLE;
 967         writel(reg_val, &disp_ctrl->disp.disp_win_opt);
 968 }
 969
 970 int tegra_dc_sor_detach(struct udevice *dc_dev, struct udevice *dev)
 971 {
 972         struct tegra_dc_sor_data *sor = dev_get_priv(dev);
 973         int dc_reg_ctx[DC_REG_SAVE_SPACE];
 974         struct dc_ctlr *disp_ctrl;
 975         unsigned long dc_int_mask;
 976         int ret;
 977
 978         debug("%s\n", __func__);
 979         /* Use the first display controller */
 980         disp_ctrl = (struct dc_ctlr *)dev_read_addr(dev);
 981
 982         /* Sleep mode */
 983         tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
 984                          SUPER_STATE1_ASY_ORMODE_SAFE |
 985                          SUPER_STATE1_ATTACHED_YES);
 986         tegra_dc_sor_super_update(sor);
 987
 988         tegra_dc_sor_disable_win_short_raster(disp_ctrl, dc_reg_ctx);
 989
 990         if (tegra_dc_sor_poll_register(sor, TEST,
 991                                        TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
 992                                        TEST_ACT_HEAD_OPMODE_SLEEP, 100,
 993                                        TEGRA_SOR_ATTACH_TIMEOUT_MS)) {
 994                 debug("dc timeout waiting for OPMOD = SLEEP\n");
 995                 ret = -ETIMEDOUT;
 996                 goto err;
 997         }
 998
 999         tegra_sor_writel(sor, SUPER_STATE1, SUPER_STATE1_ASY_HEAD_OP_SLEEP |
1000                          SUPER_STATE1_ASY_ORMODE_SAFE |
1001                          SUPER_STATE1_ATTACHED_NO);
1002
1003         /* Mask DC interrupts during the 2 dummy frames required for detach */
1004         dc_int_mask = readl(&disp_ctrl->cmd.int_mask);
1005         writel(0, &disp_ctrl->cmd.int_mask);
1006
1007         /* Stop DC->SOR path */
1008         tegra_dc_sor_enable_sor(disp_ctrl, false);
1009         ret = tegra_dc_sor_general_act(disp_ctrl);
1010         if (ret)
1011                 goto err;
1012
1013         /* Stop DC */
1014         writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd);
1015         ret = tegra_dc_sor_general_act(disp_ctrl);
1016         if (ret)
1017                 goto err;
1018
1019         tegra_dc_sor_restore_win_and_raster(disp_ctrl, dc_reg_ctx);
1020
1021         writel(dc_int_mask, &disp_ctrl->cmd.int_mask);
1022
1023         return 0;
1024 err:
1025         debug("%s: ret=%d\n", __func__, ret);
1026
1027         return ret;
1028 }
1029
1030 static int tegra_sor_set_backlight(struct udevice *dev, int percent)
1031 {
1032         struct tegra_dc_sor_data *priv = dev_get_priv(dev);
1033         int ret;
1034
1035         ret = panel_enable_backlight(priv->panel);
1036         if (ret) {
1037                 debug("sor: Cannot enable panel backlight\n");
1038                 return ret;
1039         }
1040
1041         return 0;
1042 }
1043
1044 static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
1045 {
1046         struct tegra_dc_sor_data *priv = dev_get_priv(dev);
1047         int ret;
1048
1049         priv->base = (void *)dev_read_addr(dev);
1050
1051         priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
1052         if (IS_ERR(priv->pmc_base))
1053                 return PTR_ERR(priv->pmc_base);
1054
1055         ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
1056                                            &priv->panel);
1057         if (ret) {
1058                 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1059                       dev->name, ret);
1060                 return ret;
1061         }
1062
1063         return 0;
1064 }
1065
1066 static const struct video_bridge_ops tegra_sor_ops = {
1067         .set_backlight  = tegra_sor_set_backlight,
1068 };
1069
1070 static const struct udevice_id tegra_sor_ids[] = {
1071         { .compatible = "nvidia,tegra124-sor" },
1072         { }
1073 };
1074
1075 U_BOOT_DRIVER(sor_tegra) = {
1076         .name   = "sor_tegra",
1077         .id     = UCLASS_VIDEO_BRIDGE,
1078         .of_match = tegra_sor_ids,
1079         .ofdata_to_platdata = tegra_sor_ofdata_to_platdata,
1080         .ops    = &tegra_sor_ops,
1081         .priv_auto_alloc_size = sizeof(struct tegra_dc_sor_data),
1082 };