drivers/video/sunxi/sunxi_dw_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Allwinner DW HDMI bridge
   4  *
   5  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   6  */
   7
   8 #include <common.h>
   9 #include <display.h>
  10 #include <dm.h>
  11 #include <dw_hdmi.h>
  12 #include <edid.h>
  13 #include <log.h>
  14 #include <time.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/lcdc.h>
  18 #include <linux/delay.h>
  19
  20 struct sunxi_dw_hdmi_priv {
  21         struct dw_hdmi hdmi;
  22         int mux;
  23 };
  24
  25 struct sunxi_hdmi_phy {
  26         u32 pol;
  27         u32 res1[3];
  28         u32 read_en;
  29         u32 unscramble;
  30         u32 res2[2];
  31         u32 ctrl;
  32         u32 unk1;
  33         u32 unk2;
  34         u32 pll;
  35         u32 clk;
  36         u32 unk3;
  37         u32 status;
  38 };
  39
  40 #define HDMI_PHY_OFFS 0x10000
  41
  42 static int sunxi_dw_hdmi_get_divider(uint clock)
  43 {
  44         /*
  45          * Due to missing documentaion of HDMI PHY, we know correct
  46          * settings only for following four PHY dividers. Select one
  47          * based on clock speed.
  48          */
  49         if (clock <= 27000000)
  50                 return 11;
  51         else if (clock <= 74250000)
  52                 return 4;
  53         else if (clock <= 148500000)
  54                 return 2;
  55         else
  56                 return 1;
  57 }
  58
  59 static void sunxi_dw_hdmi_phy_init(void)
  60 {
  61         struct sunxi_hdmi_phy * const phy =
  62                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
  63         unsigned long tmo;
  64         u32 tmp;
  65
  66         /*
  67          * HDMI PHY settings are taken as-is from Allwinner BSP code.
  68          * There is no documentation.
  69          */
  70         writel(0, &phy->ctrl);
  71         setbits_le32(&phy->ctrl, BIT(0));
  72         udelay(5);
  73         setbits_le32(&phy->ctrl, BIT(16));
  74         setbits_le32(&phy->ctrl, BIT(1));
  75         udelay(10);
  76         setbits_le32(&phy->ctrl, BIT(2));
  77         udelay(5);
  78         setbits_le32(&phy->ctrl, BIT(3));
  79         udelay(40);
  80         setbits_le32(&phy->ctrl, BIT(19));
  81         udelay(100);
  82         setbits_le32(&phy->ctrl, BIT(18));
  83         setbits_le32(&phy->ctrl, 7 << 4);
  84
  85         /* Note that Allwinner code doesn't fail in case of timeout */
  86         tmo = timer_get_us() + 2000;
  87         while ((readl(&phy->status) & 0x80) == 0) {
  88                 if (timer_get_us() > tmo) {
  89                         printf("Warning: HDMI PHY init timeout!\n");
  90                         break;
  91                 }
  92         }
  93
  94         setbits_le32(&phy->ctrl, 0xf << 8);
  95         setbits_le32(&phy->ctrl, BIT(7));
  96
  97         writel(0x39dc5040, &phy->pll);
  98         writel(0x80084343, &phy->clk);
  99         udelay(10000);
 100         writel(1, &phy->unk3);
 101         setbits_le32(&phy->pll, BIT(25));
 102         udelay(100000);
 103         tmp = (readl(&phy->status) & 0x1f800) >> 11;
 104         setbits_le32(&phy->pll, BIT(31) | BIT(30));
 105         setbits_le32(&phy->pll, tmp);
 106         writel(0x01FF0F7F, &phy->ctrl);
 107         writel(0x80639000, &phy->unk1);
 108         writel(0x0F81C405, &phy->unk2);
 109
 110         /* enable read access to HDMI controller */
 111         writel(0x54524545, &phy->read_en);
 112         /* descramble register offsets */
 113         writel(0x42494E47, &phy->unscramble);
 114 }
 115
 116 static int sunxi_dw_hdmi_get_plug_in_status(void)
 117 {
 118         struct sunxi_hdmi_phy * const phy =
 119                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 120
 121         return !!(readl(&phy->status) & (1 << 19));
 122 }
 123
 124 static int sunxi_dw_hdmi_wait_for_hpd(void)
 125 {
 126         ulong start;
 127
 128         start = get_timer(0);
 129         do {
 130                 if (sunxi_dw_hdmi_get_plug_in_status())
 131                         return 0;
 132                 udelay(100);
 133         } while (get_timer(start) < 300);
 134
 135         return -1;
 136 }
 137
 138 static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
 139 {
 140         struct sunxi_hdmi_phy * const phy =
 141                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 142         int div = sunxi_dw_hdmi_get_divider(clock);
 143         u32 tmp;
 144
 145         /*
 146          * Unfortunately, we don't know much about those magic
 147          * numbers. They are taken from Allwinner BSP driver.
 148          */
 149         switch (div) {
 150         case 1:
 151                 writel(0x30dc5fc0, &phy->pll);
 152                 writel(0x800863C0 | (phy_div - 1), &phy->clk);
 153                 mdelay(10);
 154                 writel(0x00000001, &phy->unk3);
 155                 setbits_le32(&phy->pll, BIT(25));
 156                 mdelay(200);
 157                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 158                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 159                 if (tmp < 0x3d)
 160                         setbits_le32(&phy->pll, tmp + 2);
 161                 else
 162                         setbits_le32(&phy->pll, 0x3f);
 163                 mdelay(100);
 164                 writel(0x01FFFF7F, &phy->ctrl);
 165                 writel(0x8063b000, &phy->unk1);
 166                 writel(0x0F8246B5, &phy->unk2);
 167                 break;
 168         case 2:
 169                 writel(0x39dc5040, &phy->pll);
 170                 writel(0x80084380 | (phy_div - 1), &phy->clk);
 171                 mdelay(10);
 172                 writel(0x00000001, &phy->unk3);
 173                 setbits_le32(&phy->pll, BIT(25));
 174                 mdelay(100);
 175                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 176                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 177                 setbits_le32(&phy->pll, tmp);
 178                 writel(0x01FFFF7F, &phy->ctrl);
 179                 writel(0x8063a800, &phy->unk1);
 180                 writel(0x0F81C485, &phy->unk2);
 181                 break;
 182         case 4:
 183                 writel(0x39dc5040, &phy->pll);
 184                 writel(0x80084340 | (phy_div - 1), &phy->clk);
 185                 mdelay(10);
 186                 writel(0x00000001, &phy->unk3);
 187                 setbits_le32(&phy->pll, BIT(25));
 188                 mdelay(100);
 189                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 190                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 191                 setbits_le32(&phy->pll, tmp);
 192                 writel(0x01FFFF7F, &phy->ctrl);
 193                 writel(0x8063b000, &phy->unk1);
 194                 writel(0x0F81C405, &phy->unk2);
 195                 break;
 196         case 11:
 197                 writel(0x39dc5040, &phy->pll);
 198                 writel(0x80084300 | (phy_div - 1), &phy->clk);
 199                 mdelay(10);
 200                 writel(0x00000001, &phy->unk3);
 201                 setbits_le32(&phy->pll, BIT(25));
 202                 mdelay(100);
 203                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 204                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 205                 setbits_le32(&phy->pll, tmp);
 206                 writel(0x01FFFF7F, &phy->ctrl);
 207                 writel(0x8063b000, &phy->unk1);
 208                 writel(0x0F81C405, &phy->unk2);
 209                 break;
 210         }
 211 }
 212
 213 static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
 214 {
 215         int value, n, m, div, diff;
 216         int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
 217
 218         /*
 219          * Find the lowest divider resulting in a matching clock. If there
 220          * is no match, pick the closest lower clock, as monitors tend to
 221          * not sync to higher frequencies.
 222          */
 223         for (div = 1; div <= 16; div++) {
 224                 int target = clk_khz * div;
 225
 226                 if (target < 192000)
 227                         continue;
 228                 if (target > 912000)
 229                         continue;
 230
 231                 for (m = 1; m <= 16; m++) {
 232                         n = (m * target) / 24000;
 233
 234                         if (n >= 1 && n <= 128) {
 235                                 value = (24000 * n) / m / div;
 236                                 diff = clk_khz - value;
 237                                 if (diff < best_diff) {
 238                                         best_diff = diff;
 239                                         best_m = m;
 240                                         best_n = n;
 241                                         best_div = div;
 242                                 }
 243                         }
 244                 }
 245         }
 246
 247         *phy_div = best_div;
 248
 249         clock_set_pll3_factors(best_m, best_n);
 250         debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
 251               clk_khz, (clock_get_pll3() / 1000) / best_div,
 252               best_n, best_m, best_div);
 253 }
 254
 255 static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
 256                                     int bpp)
 257 {
 258         struct sunxi_ccm_reg * const ccm =
 259                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 260         int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
 261         struct sunxi_lcdc_reg *lcdc;
 262
 263         if (mux == 0) {
 264                 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 265
 266                 /* Reset off */
 267                 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 268
 269                 /* Clock on */
 270                 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 271                 writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
 272                        &ccm->lcd0_clk_cfg);
 273         } else {
 274                 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
 275
 276                 /* Reset off */
 277                 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
 278
 279                 /* Clock on */
 280                 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
 281                 writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
 282                        &ccm->lcd1_clk_cfg);
 283         }
 284
 285         lcdc_init(lcdc);
 286         lcdc_tcon1_mode_set(lcdc, edid, false, false);
 287         lcdc_enable(lcdc, bpp);
 288 }
 289
 290 static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
 291 {
 292         int phy_div;
 293
 294         sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
 295         sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
 296
 297         return 0;
 298 }
 299
 300 static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
 301 {
 302         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 303
 304         return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
 305 }
 306
 307 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 308                                 const struct display_timing *edid)
 309 {
 310         struct sunxi_hdmi_phy * const phy =
 311                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 312         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 313         int ret;
 314
 315         ret = dw_hdmi_enable(&priv->hdmi, edid);
 316         if (ret)
 317                 return ret;
 318
 319         sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
 320
 321         if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
 322                 setbits_le32(&phy->pol, 0x200);
 323
 324         if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
 325                 setbits_le32(&phy->pol, 0x100);
 326
 327         setbits_le32(&phy->ctrl, 0xf << 12);
 328
 329         /*
 330          * This is last hdmi access before boot, so scramble addresses
 331          * again or othwerwise BSP driver won't work. Dummy read is
 332          * needed or otherwise last write doesn't get written correctly.
 333          */
 334         (void)readb(SUNXI_HDMI_BASE);
 335         writel(0, &phy->unscramble);
 336
 337         return 0;
 338 }
 339
 340 static int sunxi_dw_hdmi_probe(struct udevice *dev)
 341 {
 342         struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 343         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 344         struct sunxi_ccm_reg * const ccm =
 345                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 346         int ret;
 347
 348         /* Set pll3 to 297 MHz */
 349         clock_set_pll3(297000000);
 350
 351         /* Set hdmi parent to pll3 */
 352         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
 353                         CCM_HDMI_CTRL_PLL3);
 354
 355         /* Set ahb gating to pass */
 356         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 357         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
 358         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
 359         setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
 360
 361         /* Clock on */
 362         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 363
 364         sunxi_dw_hdmi_phy_init();
 365
 366         ret = sunxi_dw_hdmi_wait_for_hpd();
 367         if (ret < 0) {
 368                 debug("hdmi can not get hpd signal\n");
 369                 return -1;
 370         }
 371
 372         priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
 373         priv->hdmi.i2c_clk_high = 0xd8;
 374         priv->hdmi.i2c_clk_low = 0xfe;
 375         priv->hdmi.reg_io_width = 1;
 376         priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
 377         priv->mux = uc_plat->source_id;
 378
 379         uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
 380                                      &priv->hdmi.ddc_bus);
 381
 382         dw_hdmi_init(&priv->hdmi);
 383
 384         return 0;
 385 }
 386
 387 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
 388         .read_edid = sunxi_dw_hdmi_read_edid,
 389         .enable = sunxi_dw_hdmi_enable,
 390 };
 391
 392 U_BOOT_DRIVER(sunxi_dw_hdmi) = {
 393         .name   = "sunxi_dw_hdmi",
 394         .id     = UCLASS_DISPLAY,
 395         .ops    = &sunxi_dw_hdmi_ops,
 396         .probe  = sunxi_dw_hdmi_probe,
 397         .priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
 398 };
 399
 400 U_BOOT_DEVICE(sunxi_dw_hdmi) = {
 401         .name = "sunxi_dw_hdmi"
 402 };