drivers/video/sunxi/sunxi_dw_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Allwinner DW HDMI bridge
   4  *
   5  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   6  */
   7
   8 #include <common.h>
   9 #include <display.h>
  10 #include <dm.h>
  11 #include <dw_hdmi.h>
  12 #include <edid.h>
  13 #include <log.h>
  14 #include <time.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/lcdc.h>
  18
  19 struct sunxi_dw_hdmi_priv {
  20         struct dw_hdmi hdmi;
  21         int mux;
  22 };
  23
  24 struct sunxi_hdmi_phy {
  25         u32 pol;
  26         u32 res1[3];
  27         u32 read_en;
  28         u32 unscramble;
  29         u32 res2[2];
  30         u32 ctrl;
  31         u32 unk1;
  32         u32 unk2;
  33         u32 pll;
  34         u32 clk;
  35         u32 unk3;
  36         u32 status;
  37 };
  38
  39 #define HDMI_PHY_OFFS 0x10000
  40
  41 static int sunxi_dw_hdmi_get_divider(uint clock)
  42 {
  43         /*
  44          * Due to missing documentaion of HDMI PHY, we know correct
  45          * settings only for following four PHY dividers. Select one
  46          * based on clock speed.
  47          */
  48         if (clock <= 27000000)
  49                 return 11;
  50         else if (clock <= 74250000)
  51                 return 4;
  52         else if (clock <= 148500000)
  53                 return 2;
  54         else
  55                 return 1;
  56 }
  57
  58 static void sunxi_dw_hdmi_phy_init(void)
  59 {
  60         struct sunxi_hdmi_phy * const phy =
  61                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
  62         unsigned long tmo;
  63         u32 tmp;
  64
  65         /*
  66          * HDMI PHY settings are taken as-is from Allwinner BSP code.
  67          * There is no documentation.
  68          */
  69         writel(0, &phy->ctrl);
  70         setbits_le32(&phy->ctrl, BIT(0));
  71         udelay(5);
  72         setbits_le32(&phy->ctrl, BIT(16));
  73         setbits_le32(&phy->ctrl, BIT(1));
  74         udelay(10);
  75         setbits_le32(&phy->ctrl, BIT(2));
  76         udelay(5);
  77         setbits_le32(&phy->ctrl, BIT(3));
  78         udelay(40);
  79         setbits_le32(&phy->ctrl, BIT(19));
  80         udelay(100);
  81         setbits_le32(&phy->ctrl, BIT(18));
  82         setbits_le32(&phy->ctrl, 7 << 4);
  83
  84         /* Note that Allwinner code doesn't fail in case of timeout */
  85         tmo = timer_get_us() + 2000;
  86         while ((readl(&phy->status) & 0x80) == 0) {
  87                 if (timer_get_us() > tmo) {
  88                         printf("Warning: HDMI PHY init timeout!\n");
  89                         break;
  90                 }
  91         }
  92
  93         setbits_le32(&phy->ctrl, 0xf << 8);
  94         setbits_le32(&phy->ctrl, BIT(7));
  95
  96         writel(0x39dc5040, &phy->pll);
  97         writel(0x80084343, &phy->clk);
  98         udelay(10000);
  99         writel(1, &phy->unk3);
 100         setbits_le32(&phy->pll, BIT(25));
 101         udelay(100000);
 102         tmp = (readl(&phy->status) & 0x1f800) >> 11;
 103         setbits_le32(&phy->pll, BIT(31) | BIT(30));
 104         setbits_le32(&phy->pll, tmp);
 105         writel(0x01FF0F7F, &phy->ctrl);
 106         writel(0x80639000, &phy->unk1);
 107         writel(0x0F81C405, &phy->unk2);
 108
 109         /* enable read access to HDMI controller */
 110         writel(0x54524545, &phy->read_en);
 111         /* descramble register offsets */
 112         writel(0x42494E47, &phy->unscramble);
 113 }
 114
 115 static int sunxi_dw_hdmi_get_plug_in_status(void)
 116 {
 117         struct sunxi_hdmi_phy * const phy =
 118                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 119
 120         return !!(readl(&phy->status) & (1 << 19));
 121 }
 122
 123 static int sunxi_dw_hdmi_wait_for_hpd(void)
 124 {
 125         ulong start;
 126
 127         start = get_timer(0);
 128         do {
 129                 if (sunxi_dw_hdmi_get_plug_in_status())
 130                         return 0;
 131                 udelay(100);
 132         } while (get_timer(start) < 300);
 133
 134         return -1;
 135 }
 136
 137 static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
 138 {
 139         struct sunxi_hdmi_phy * const phy =
 140                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 141         int div = sunxi_dw_hdmi_get_divider(clock);
 142         u32 tmp;
 143
 144         /*
 145          * Unfortunately, we don't know much about those magic
 146          * numbers. They are taken from Allwinner BSP driver.
 147          */
 148         switch (div) {
 149         case 1:
 150                 writel(0x30dc5fc0, &phy->pll);
 151                 writel(0x800863C0 | (phy_div - 1), &phy->clk);
 152                 mdelay(10);
 153                 writel(0x00000001, &phy->unk3);
 154                 setbits_le32(&phy->pll, BIT(25));
 155                 mdelay(200);
 156                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 157                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 158                 if (tmp < 0x3d)
 159                         setbits_le32(&phy->pll, tmp + 2);
 160                 else
 161                         setbits_le32(&phy->pll, 0x3f);
 162                 mdelay(100);
 163                 writel(0x01FFFF7F, &phy->ctrl);
 164                 writel(0x8063b000, &phy->unk1);
 165                 writel(0x0F8246B5, &phy->unk2);
 166                 break;
 167         case 2:
 168                 writel(0x39dc5040, &phy->pll);
 169                 writel(0x80084380 | (phy_div - 1), &phy->clk);
 170                 mdelay(10);
 171                 writel(0x00000001, &phy->unk3);
 172                 setbits_le32(&phy->pll, BIT(25));
 173                 mdelay(100);
 174                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 175                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 176                 setbits_le32(&phy->pll, tmp);
 177                 writel(0x01FFFF7F, &phy->ctrl);
 178                 writel(0x8063a800, &phy->unk1);
 179                 writel(0x0F81C485, &phy->unk2);
 180                 break;
 181         case 4:
 182                 writel(0x39dc5040, &phy->pll);
 183                 writel(0x80084340 | (phy_div - 1), &phy->clk);
 184                 mdelay(10);
 185                 writel(0x00000001, &phy->unk3);
 186                 setbits_le32(&phy->pll, BIT(25));
 187                 mdelay(100);
 188                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 189                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 190                 setbits_le32(&phy->pll, tmp);
 191                 writel(0x01FFFF7F, &phy->ctrl);
 192                 writel(0x8063b000, &phy->unk1);
 193                 writel(0x0F81C405, &phy->unk2);
 194                 break;
 195         case 11:
 196                 writel(0x39dc5040, &phy->pll);
 197                 writel(0x80084300 | (phy_div - 1), &phy->clk);
 198                 mdelay(10);
 199                 writel(0x00000001, &phy->unk3);
 200                 setbits_le32(&phy->pll, BIT(25));
 201                 mdelay(100);
 202                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 203                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 204                 setbits_le32(&phy->pll, tmp);
 205                 writel(0x01FFFF7F, &phy->ctrl);
 206                 writel(0x8063b000, &phy->unk1);
 207                 writel(0x0F81C405, &phy->unk2);
 208                 break;
 209         }
 210 }
 211
 212 static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
 213 {
 214         int value, n, m, div, diff;
 215         int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
 216
 217         /*
 218          * Find the lowest divider resulting in a matching clock. If there
 219          * is no match, pick the closest lower clock, as monitors tend to
 220          * not sync to higher frequencies.
 221          */
 222         for (div = 1; div <= 16; div++) {
 223                 int target = clk_khz * div;
 224
 225                 if (target < 192000)
 226                         continue;
 227                 if (target > 912000)
 228                         continue;
 229
 230                 for (m = 1; m <= 16; m++) {
 231                         n = (m * target) / 24000;
 232
 233                         if (n >= 1 && n <= 128) {
 234                                 value = (24000 * n) / m / div;
 235                                 diff = clk_khz - value;
 236                                 if (diff < best_diff) {
 237                                         best_diff = diff;
 238                                         best_m = m;
 239                                         best_n = n;
 240                                         best_div = div;
 241                                 }
 242                         }
 243                 }
 244         }
 245
 246         *phy_div = best_div;
 247
 248         clock_set_pll3_factors(best_m, best_n);
 249         debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
 250               clk_khz, (clock_get_pll3() / 1000) / best_div,
 251               best_n, best_m, best_div);
 252 }
 253
 254 static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
 255                                     int bpp)
 256 {
 257         struct sunxi_ccm_reg * const ccm =
 258                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 259         int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
 260         struct sunxi_lcdc_reg *lcdc;
 261
 262         if (mux == 0) {
 263                 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 264
 265                 /* Reset off */
 266                 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 267
 268                 /* Clock on */
 269                 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 270                 writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
 271                        &ccm->lcd0_clk_cfg);
 272         } else {
 273                 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
 274
 275                 /* Reset off */
 276                 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
 277
 278                 /* Clock on */
 279                 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
 280                 writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
 281                        &ccm->lcd1_clk_cfg);
 282         }
 283
 284         lcdc_init(lcdc);
 285         lcdc_tcon1_mode_set(lcdc, edid, false, false);
 286         lcdc_enable(lcdc, bpp);
 287 }
 288
 289 static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
 290 {
 291         int phy_div;
 292
 293         sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
 294         sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
 295
 296         return 0;
 297 }
 298
 299 static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
 300 {
 301         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 302
 303         return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
 304 }
 305
 306 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 307                                 const struct display_timing *edid)
 308 {
 309         struct sunxi_hdmi_phy * const phy =
 310                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 311         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 312         int ret;
 313
 314         ret = dw_hdmi_enable(&priv->hdmi, edid);
 315         if (ret)
 316                 return ret;
 317
 318         sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
 319
 320         if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
 321                 setbits_le32(&phy->pol, 0x200);
 322
 323         if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
 324                 setbits_le32(&phy->pol, 0x100);
 325
 326         setbits_le32(&phy->ctrl, 0xf << 12);
 327
 328         /*
 329          * This is last hdmi access before boot, so scramble addresses
 330          * again or othwerwise BSP driver won't work. Dummy read is
 331          * needed or otherwise last write doesn't get written correctly.
 332          */
 333         (void)readb(SUNXI_HDMI_BASE);
 334         writel(0, &phy->unscramble);
 335
 336         return 0;
 337 }
 338
 339 static int sunxi_dw_hdmi_probe(struct udevice *dev)
 340 {
 341         struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 342         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 343         struct sunxi_ccm_reg * const ccm =
 344                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 345         int ret;
 346
 347         /* Set pll3 to 297 MHz */
 348         clock_set_pll3(297000000);
 349
 350         /* Set hdmi parent to pll3 */
 351         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
 352                         CCM_HDMI_CTRL_PLL3);
 353
 354         /* Set ahb gating to pass */
 355         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 356         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
 357         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
 358         setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
 359
 360         /* Clock on */
 361         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 362
 363         sunxi_dw_hdmi_phy_init();
 364
 365         ret = sunxi_dw_hdmi_wait_for_hpd();
 366         if (ret < 0) {
 367                 debug("hdmi can not get hpd signal\n");
 368                 return -1;
 369         }
 370
 371         priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
 372         priv->hdmi.i2c_clk_high = 0xd8;
 373         priv->hdmi.i2c_clk_low = 0xfe;
 374         priv->hdmi.reg_io_width = 1;
 375         priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
 376         priv->mux = uc_plat->source_id;
 377
 378         uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
 379                                      &priv->hdmi.ddc_bus);
 380
 381         dw_hdmi_init(&priv->hdmi);
 382
 383         return 0;
 384 }
 385
 386 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
 387         .read_edid = sunxi_dw_hdmi_read_edid,
 388         .enable = sunxi_dw_hdmi_enable,
 389 };
 390
 391 U_BOOT_DRIVER(sunxi_dw_hdmi) = {
 392         .name   = "sunxi_dw_hdmi",
 393         .id     = UCLASS_DISPLAY,
 394         .ops    = &sunxi_dw_hdmi_ops,
 395         .probe  = sunxi_dw_hdmi_probe,
 396         .priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
 397 };
 398
 399 U_BOOT_DEVICE(sunxi_dw_hdmi) = {
 400         .name = "sunxi_dw_hdmi"
 401 };