1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/edp_rk3288.h>
20 #include <asm/arch-rockchip/vop_rk3288.h>
21 #include <dm/device-internal.h>
22 #include <dm/uclass-internal.h>
23 #include <linux/bitops.h>
24 #include <linux/err.h>
25 #include <power/regulator.h>
28 DECLARE_GLOBAL_DATA_PTR;
37 static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
38 int fb_bits_per_pixel,
39 const struct display_timing *edid)
43 u32 hactive = edid->hactive.typ;
44 u32 vactive = edid->vactive.typ;
46 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
47 ®s->win0_act_info);
49 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
50 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
53 writel(V_DSP_WIDTH(hactive - 1) |
54 V_DSP_HEIGHT(vactive - 1),
55 ®s->win0_dsp_info);
57 clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
58 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
60 switch (fb_bits_per_pixel) {
63 writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir);
67 writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir);
72 writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir);
77 lb_mode = LB_RGB_3840X2;
78 else if (hactive > 1920)
79 lb_mode = LB_RGB_2560X4;
80 else if (hactive > 1280)
81 lb_mode = LB_RGB_1920X5;
83 lb_mode = LB_RGB_1280X8;
85 clrsetbits_le32(®s->win0_ctrl0,
86 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
87 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
90 writel(fbbase, ®s->win0_yrgb_mst);
91 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
94 static void rkvop_set_pin_polarity(struct udevice *dev,
95 enum vop_modes mode, u32 polarity)
97 struct rkvop_driverdata *ops =
98 (struct rkvop_driverdata *)dev_get_driver_data(dev);
100 if (ops->set_pin_polarity)
101 ops->set_pin_polarity(dev, mode, polarity);
104 static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
106 struct rk_vop_priv *priv = dev_get_priv(dev);
107 struct rk3288_vop *regs = priv->regs;
109 /* remove from standby */
110 clrbits_le32(®s->sys_ctrl, V_STANDBY_EN(1));
114 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
119 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
123 #if defined(CONFIG_ROCKCHIP_RK3288)
125 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
131 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
136 debug("%s: unsupported output mode %x\n", __func__, mode);
140 static void rkvop_mode_set(struct udevice *dev,
141 const struct display_timing *edid,
144 struct rk_vop_priv *priv = dev_get_priv(dev);
145 struct rk3288_vop *regs = priv->regs;
146 struct rkvop_driverdata *data =
147 (struct rkvop_driverdata *)dev_get_driver_data(dev);
149 u32 hactive = edid->hactive.typ;
150 u32 vactive = edid->vactive.typ;
151 u32 hsync_len = edid->hsync_len.typ;
152 u32 hback_porch = edid->hback_porch.typ;
153 u32 vsync_len = edid->vsync_len.typ;
154 u32 vback_porch = edid->vback_porch.typ;
155 u32 hfront_porch = edid->hfront_porch.typ;
156 u32 vfront_porch = edid->vfront_porch.typ;
160 pin_polarity = BIT(DCLK_INVERT);
161 if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
162 pin_polarity |= BIT(HSYNC_POSITIVE);
163 if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
164 pin_polarity |= BIT(VSYNC_POSITIVE);
166 rkvop_set_pin_polarity(dev, mode, pin_polarity);
167 rkvop_enable_output(dev, mode);
169 mode_flags = 0; /* RGB888 */
170 if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
171 (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
172 mode_flags = 15; /* RGBaaa */
174 clrsetbits_le32(®s->dsp_ctrl0, M_DSP_OUT_MODE,
175 V_DSP_OUT_MODE(mode_flags));
177 writel(V_HSYNC(hsync_len) |
178 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
179 ®s->dsp_htotal_hs_end);
181 writel(V_HEAP(hsync_len + hback_porch + hactive) |
182 V_HASP(hsync_len + hback_porch),
183 ®s->dsp_hact_st_end);
185 writel(V_VSYNC(vsync_len) |
186 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
187 ®s->dsp_vtotal_vs_end);
189 writel(V_VAEP(vsync_len + vback_porch + vactive)|
190 V_VASP(vsync_len + vback_porch),
191 ®s->dsp_vact_st_end);
193 writel(V_HEAP(hsync_len + hback_porch + hactive) |
194 V_HASP(hsync_len + hback_porch),
195 ®s->post_dsp_hact_info);
197 writel(V_VAEP(vsync_len + vback_porch + vactive)|
198 V_VASP(vsync_len + vback_porch),
199 ®s->post_dsp_vact_info);
201 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
205 * rk_display_init() - Try to enable the given display device
207 * This function performs many steps:
208 * - Finds the display device being referenced by @ep_node
209 * - Puts the VOP's ID into its uclass platform data
210 * - Probes the device to set it up
211 * - Reads the EDID timing information
212 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
213 * - Enables the display (the display device handles this and will do different
214 * things depending on the display type)
215 * - Tells the uclass about the display resolution so that the console will
218 * @dev: VOP device that we want to connect to the display
219 * @fbbase: Frame buffer address
220 * @ep_node: Device tree node to process - this is the offset of an endpoint
221 * node within the VOP's 'port' list.
222 * @return 0 if OK, -ve if something went wrong
224 static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
226 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
227 struct rk_vop_priv *priv = dev_get_priv(dev);
228 int vop_id, remote_vop_id;
229 struct rk3288_vop *regs = priv->regs;
230 struct display_timing timing;
231 struct udevice *disp;
234 struct display_plat *disp_uc_plat;
236 enum video_log2_bpp l2bpp;
239 debug("%s(%s, %lu, %s)\n", __func__,
240 dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
242 vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
243 debug("vop_id=%d\n", vop_id);
244 ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
248 remote = ofnode_get_by_phandle(remote_phandle);
249 if (!ofnode_valid(remote))
251 remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
252 debug("remote vop_id=%d\n", remote_vop_id);
255 * The remote-endpoint references into a subnode of the encoder
256 * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
257 * the following (assume 'hdmi_in_vopl' to be referenced):
259 * hdmi: hdmi@ff940000 {
262 * hdmi_in_vopb: endpoint@0 { ... };
263 * hdmi_in_vopl: endpoint@1 { ... };
268 * The original code had 3 steps of "walking the parent", but
269 * a much better (as in: less likely to break if the DTS
270 * changes) way of doing this is to "find the enclosing device
271 * of UCLASS_DISPLAY".
273 while (ofnode_valid(remote)) {
274 remote = ofnode_get_parent(remote);
275 if (!ofnode_valid(remote)) {
276 debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
277 __func__, dev_read_name(dev));
281 uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
286 disp_uc_plat = dev_get_uclass_platdata(disp);
287 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
288 if (display_in_use(disp)) {
289 debug(" - device in use\n");
293 disp_uc_plat->source_id = remote_vop_id;
294 disp_uc_plat->src_dev = dev;
296 ret = device_probe(disp);
298 debug("%s: device '%s' display won't probe (ret=%d)\n",
299 __func__, dev->name, ret);
303 ret = display_read_timing(disp, &timing);
305 debug("%s: Failed to read timings\n", __func__);
309 ret = clk_get_by_index(dev, 1, &clk);
311 ret = clk_set_rate(&clk, timing.pixelclock.typ);
312 if (IS_ERR_VALUE(ret)) {
313 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
317 /* Set bitwidth for vop display according to vop mode */
320 #if defined(CONFIG_ROCKCHIP_RK3288)
333 rkvop_mode_set(dev, &timing, vop_id);
334 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
336 ret = display_enable(disp, 1 << l2bpp, &timing);
340 uc_priv->xsize = timing.hactive.typ;
341 uc_priv->ysize = timing.vactive.typ;
342 uc_priv->bpix = l2bpp;
343 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
348 void rk_vop_probe_regulators(struct udevice *dev,
349 const char * const *names, int cnt)
355 for (i = 0; i < cnt; ++i) {
357 debug("%s: probing regulator '%s'\n", dev->name, name);
359 ret = regulator_autoset_by_name(name, ®);
361 ret = regulator_set_enable(reg, true);
365 int rk_vop_probe(struct udevice *dev)
367 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
368 struct rk_vop_priv *priv = dev_get_priv(dev);
372 /* Before relocation we don't need to do anything */
373 if (!(gd->flags & GD_FLG_RELOC))
376 priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
379 * Try all the ports until we find one that works. In practice this
380 * tries EDP first if available, then HDMI.
382 * Note that rockchip_vop_set_clk() always uses NPLL as the source
383 * clock so it is currently not possible to use more than one display
384 * device simultaneously.
386 port = dev_read_subnode(dev, "port");
387 if (!ofnode_valid(port)) {
388 debug("%s(%s): 'port' subnode not found\n",
389 __func__, dev_read_name(dev));
393 for (node = ofnode_first_subnode(port);
395 node = dev_read_next_subnode(node)) {
396 ret = rk_display_init(dev, plat->base, node);
398 debug("Device failed: ret=%d\n", ret);
402 video_set_flush_dcache(dev, 1);
407 int rk_vop_bind(struct udevice *dev)
409 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
411 plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
412 CONFIG_VIDEO_ROCKCHIP_MAX_YRES);