drivers/video/rockchip/rk_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
   4  * Copyright (c) 2015 Google, Inc
   5  * Copyright 2014 Rockchip Inc.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <display.h>
  11 #include <dm.h>
  12 #include <dw_hdmi.h>
  13 #include <edid.h>
  14 #include <regmap.h>
  15 #include <syscon.h>
  16 #include <asm/gpio.h>
  17 #include <asm/hardware.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/hardware.h>
  21 #include "rk_hdmi.h"
  22 #include "rk_vop.h" /* for rk_vop_probe_regulators */
  23
  24 static const struct hdmi_phy_config rockchip_phy_config[] = {
  25         {
  26                 .mpixelclock = 74250000,
  27                 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
  28         }, {
  29                 .mpixelclock = 148500000,
  30                 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
  31         }, {
  32                 .mpixelclock = 297000000,
  33                 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
  34         }, {
  35                 .mpixelclock = 584000000,
  36                 .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d,
  37         }, {
  38                 .mpixelclock = ~0ul,
  39                 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
  40         }
  41 };
  42
  43 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
  44         {
  45                 .mpixelclock = 40000000,
  46                 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
  47         }, {
  48                 .mpixelclock = 65000000,
  49                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
  50         }, {
  51                 .mpixelclock = 66000000,
  52                 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
  53         }, {
  54                 .mpixelclock = 83500000,
  55                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
  56         }, {
  57                 .mpixelclock = 146250000,
  58                 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
  59         }, {
  60                 .mpixelclock = 148500000,
  61                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
  62         }, {
  63                 .mpixelclock = 272000000,
  64                 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
  65         }, {
  66                 .mpixelclock = 340000000,
  67                 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
  68         }, {
  69                 .mpixelclock = ~0ul,
  70                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
  71         }
  72 };
  73
  74 int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  75 {
  76         struct rk_hdmi_priv *priv = dev_get_priv(dev);
  77
  78         return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
  79 }
  80
  81 int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
  82 {
  83         struct rk_hdmi_priv *priv = dev_get_priv(dev);
  84         struct dw_hdmi *hdmi = &priv->hdmi;
  85
  86         hdmi->ioaddr = (ulong)dev_read_addr(dev);
  87         hdmi->mpll_cfg = rockchip_mpll_cfg;
  88         hdmi->phy_cfg = rockchip_phy_config;
  89
  90         /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
  91
  92         hdmi->reg_io_width = 4;
  93         hdmi->phy_set = dw_hdmi_phy_cfg;
  94
  95         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  96
  97         return 0;
  98 }
  99
 100 void rk_hdmi_probe_regulators(struct udevice *dev,
 101                               const char * const *names, int cnt)
 102 {
 103         rk_vop_probe_regulators(dev, names, cnt);
 104 }
 105
 106 int rk_hdmi_probe(struct udevice *dev)
 107 {
 108         struct rk_hdmi_priv *priv = dev_get_priv(dev);
 109         struct dw_hdmi *hdmi = &priv->hdmi;
 110         int ret;
 111
 112         ret = dw_hdmi_phy_wait_for_hpd(hdmi);
 113         if (ret < 0) {
 114                 debug("hdmi can not get hpd signal\n");
 115                 return -1;
 116         }
 117
 118         dw_hdmi_init(hdmi);
 119         dw_hdmi_phy_init(hdmi);
 120
 121         return 0;
 122 }