drivers/video/raydium-rm68200.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
   4  * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
   5  *            Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
   6  *
   7  * This rm68200 panel driver is inspired from the Linux Kernel driver
   8  * drivers/gpu/drm/panel/panel-raydium-rm68200.c.
   9  */
  10 #include <common.h>
  11 #include <backlight.h>
  12 #include <dm.h>
  13 #include <mipi_dsi.h>
  14 #include <panel.h>
  15 #include <asm/gpio.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/delay.h>
  18 #include <power/regulator.h>
  19
  20 /*** Manufacturer Command Set ***/
  21 #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
  22 #define MCS_CMD1_UCS    0x00 /* User Command Set (UCS = CMD1) */
  23 #define MCS_CMD2_P0     0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
  24 #define MCS_CMD2_P1     0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
  25 #define MCS_CMD2_P2     0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
  26 #define MCS_CMD2_P3     0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
  27
  28 /* CMD2 P0 commands (Display Options and Power) */
  29 #define MCS_STBCTR      0x12 /* TE1 Output Setting Zig-Zag Connection */
  30 #define MCS_SGOPCTR     0x16 /* Source Bias Current */
  31 #define MCS_SDCTR       0x1A /* Source Output Delay Time */
  32 #define MCS_INVCTR      0x1B /* Inversion Type */
  33 #define MCS_EXT_PWR_IC  0x24 /* External PWR IC Control */
  34 #define MCS_SETAVDD     0x27 /* PFM Control for AVDD Output */
  35 #define MCS_SETAVEE     0x29 /* PFM Control for AVEE Output */
  36 #define MCS_BT2CTR      0x2B /* DDVDL Charge Pump Control */
  37 #define MCS_BT3CTR      0x2F /* VGH Charge Pump Control */
  38 #define MCS_BT4CTR      0x34 /* VGL Charge Pump Control */
  39 #define MCS_VCMCTR      0x46 /* VCOM Output Level Control */
  40 #define MCS_SETVGN      0x52 /* VG M/S N Control */
  41 #define MCS_SETVGP      0x54 /* VG M/S P Control */
  42 #define MCS_SW_CTRL     0x5F /* Interface Control for PFM and MIPI */
  43
  44 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
  45 #define GOA_VSTV1               0x00
  46 #define GOA_VSTV2               0x07
  47 #define GOA_VCLK1               0x0E
  48 #define GOA_VCLK2               0x17
  49 #define GOA_VCLK_OPT1           0x20
  50 #define GOA_BICLK1              0x2A
  51 #define GOA_BICLK2              0x37
  52 #define GOA_BICLK3              0x44
  53 #define GOA_BICLK4              0x4F
  54 #define GOA_BICLK_OPT1          0x5B
  55 #define GOA_BICLK_OPT2          0x60
  56 #define MCS_GOA_GPO1            0x6D
  57 #define MCS_GOA_GPO2            0x71
  58 #define MCS_GOA_EQ              0x74
  59 #define MCS_GOA_CLK_GALLON      0x7C
  60 #define MCS_GOA_FS_SEL0         0x7E
  61 #define MCS_GOA_FS_SEL1         0x87
  62 #define MCS_GOA_FS_SEL2         0x91
  63 #define MCS_GOA_FS_SEL3         0x9B
  64 #define MCS_GOA_BS_SEL0         0xAC
  65 #define MCS_GOA_BS_SEL1         0xB5
  66 #define MCS_GOA_BS_SEL2         0xBF
  67 #define MCS_GOA_BS_SEL3         0xC9
  68 #define MCS_GOA_BS_SEL4         0xD3
  69
  70 /* CMD2 P3 commands (Gamma) */
  71 #define MCS_GAMMA_VP            0x60 /* Gamma VP1~VP16 */
  72 #define MCS_GAMMA_VN            0x70 /* Gamma VN1~VN16 */
  73
  74 struct rm68200_panel_priv {
  75         struct udevice *reg;
  76         struct udevice *backlight;
  77         struct gpio_desc reset;
  78         unsigned int lanes;
  79         enum mipi_dsi_pixel_format format;
  80         unsigned long mode_flags;
  81 };
  82
  83 static const struct display_timing default_timing = {
  84         .pixelclock.typ         = 54000000,
  85         .hactive.typ            = 720,
  86         .hfront_porch.typ       = 48,
  87         .hback_porch.typ        = 48,
  88         .hsync_len.typ          = 9,
  89         .vactive.typ            = 1280,
  90         .vfront_porch.typ       = 12,
  91         .vback_porch.typ        = 12,
  92         .vsync_len.typ          = 5,
  93 };
  94
  95 static void rm68200_dcs_write_buf(struct udevice *dev, const void *data,
  96                                   size_t len)
  97 {
  98         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  99         struct mipi_dsi_device *device = plat->device;
 100         int err;
 101
 102         err = mipi_dsi_dcs_write_buffer(device, data, len);
 103         if (err < 0)
 104                 dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err);
 105 }
 106
 107 static void rm68200_dcs_write_cmd(struct udevice *dev, u8 cmd, u8 value)
 108 {
 109         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 110         struct mipi_dsi_device *device = plat->device;
 111         int err;
 112
 113         err = mipi_dsi_dcs_write(device, cmd, &value, 1);
 114         if (err < 0)
 115                 dev_err(dev, "MIPI DSI DCS write failed: %d\n", err);
 116 }
 117
 118 #define dcs_write_seq(ctx, seq...)                              \
 119 ({                                                              \
 120         static const u8 d[] = { seq };                          \
 121                                                                 \
 122         rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d));           \
 123 })
 124
 125 /*
 126  * This panel is not able to auto-increment all cmd addresses so for some of
 127  * them, we need to send them one by one...
 128  */
 129 #define dcs_write_cmd_seq(ctx, cmd, seq...)                     \
 130 ({                                                              \
 131         static const u8 d[] = { seq };                          \
 132         unsigned int i;                                         \
 133                                                                 \
 134         for (i = 0; i < ARRAY_SIZE(d) ; i++)                    \
 135                 rm68200_dcs_write_cmd(ctx, cmd + i, d[i]);      \
 136 })
 137
 138 static void rm68200_init_sequence(struct udevice *dev)
 139 {
 140         /* Enter CMD2 with page 0 */
 141         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P0);
 142         dcs_write_cmd_seq(dev, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
 143         dcs_write_seq(dev, MCS_BT2CTR, 0xE5);
 144         dcs_write_seq(dev, MCS_SETAVDD, 0x0A);
 145         dcs_write_seq(dev, MCS_SETAVEE, 0x0A);
 146         dcs_write_seq(dev, MCS_SGOPCTR, 0x52);
 147         dcs_write_seq(dev, MCS_BT3CTR, 0x53);
 148         dcs_write_seq(dev, MCS_BT4CTR, 0x5A);
 149         dcs_write_seq(dev, MCS_INVCTR, 0x00);
 150         dcs_write_seq(dev, MCS_STBCTR, 0x0A);
 151         dcs_write_seq(dev, MCS_SDCTR, 0x06);
 152         dcs_write_seq(dev, MCS_VCMCTR, 0x56);
 153         dcs_write_seq(dev, MCS_SETVGN, 0xA0, 0x00);
 154         dcs_write_seq(dev, MCS_SETVGP, 0xA0, 0x00);
 155         dcs_write_seq(dev, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
 156
 157         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P2);
 158         dcs_write_seq(dev, GOA_VSTV1, 0x05);
 159         dcs_write_seq(dev, 0x02, 0x0B);
 160         dcs_write_seq(dev, 0x03, 0x0F);
 161         dcs_write_seq(dev, 0x04, 0x7D, 0x00, 0x50);
 162         dcs_write_cmd_seq(dev, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
 163                           0x50);
 164         dcs_write_cmd_seq(dev, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
 165                           0x00, 0x85, 0x08);
 166         dcs_write_cmd_seq(dev, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
 167                           0x00, 0x85, 0x08);
 168         dcs_write_seq(dev, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 169                       0x00, 0x00, 0x00, 0x00);
 170         dcs_write_cmd_seq(dev, GOA_BICLK1, 0x07, 0x08);
 171         dcs_write_seq(dev, 0x2D, 0x01);
 172         dcs_write_seq(dev, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
 173                       0x00);
 174         dcs_write_cmd_seq(dev, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
 175         dcs_write_seq(dev, 0x3D, 0x40);
 176         dcs_write_seq(dev, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
 177         dcs_write_seq(dev, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 178                       0x00, 0x00, 0x00, 0x00, 0x00);
 179         dcs_write_seq(dev, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 180                       0x00, 0x00);
 181         dcs_write_seq(dev, 0x58, 0x00, 0x00, 0x00);
 182         dcs_write_seq(dev, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
 183         dcs_write_seq(dev, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 184                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 185         dcs_write_seq(dev, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
 186         dcs_write_seq(dev, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
 187         dcs_write_seq(dev, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
 188                       0x00, 0x00);
 189         dcs_write_seq(dev, MCS_GOA_CLK_GALLON, 0x00, 0x00);
 190         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
 191                           0x16, 0x12, 0x08, 0x3F);
 192         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
 193                           0x0A, 0x0E, 0x3F, 0x3F, 0x00);
 194         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
 195                           0x05, 0x01, 0x3F, 0x3F, 0x0F);
 196         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
 197                           0x3F);
 198         dcs_write_cmd_seq(dev, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
 199         dcs_write_cmd_seq(dev, 0xA9, 0x07, 0x03, 0x3F);
 200         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
 201                           0x15, 0x11, 0x0F, 0x3F);
 202         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
 203                           0x0D, 0x09, 0x3F, 0x3F, 0x07);
 204         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
 205                           0x02, 0x06, 0x3F, 0x3F, 0x08);
 206         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
 207                           0x3F, 0x3F, 0x0E, 0x10, 0x14);
 208         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
 209         dcs_write_seq(dev, 0xDC, 0x02);
 210         dcs_write_seq(dev, 0xDE, 0x12);
 211
 212         dcs_write_seq(dev, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
 213         dcs_write_seq(dev, 0x01, 0x75);
 214
 215         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P3);
 216         dcs_write_cmd_seq(dev, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 217                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 218                           0x12, 0x0C, 0x00);
 219         dcs_write_cmd_seq(dev, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 220                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 221                           0x12, 0x0C, 0x00);
 222
 223         /* Exit CMD2 */
 224         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
 225 }
 226
 227 static int rm68200_panel_enable_backlight(struct udevice *dev)
 228 {
 229         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 230         struct mipi_dsi_device *device = plat->device;
 231         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 232         int ret;
 233
 234         ret = mipi_dsi_attach(device);
 235         if (ret < 0)
 236                 return ret;
 237
 238         rm68200_init_sequence(dev);
 239
 240         ret = mipi_dsi_dcs_exit_sleep_mode(device);
 241         if (ret)
 242                 return ret;
 243
 244         mdelay(125);
 245
 246         ret = mipi_dsi_dcs_set_display_on(device);
 247         if (ret)
 248                 return ret;
 249
 250         mdelay(20);
 251
 252         ret = backlight_enable(priv->backlight);
 253         if (ret)
 254                 return ret;
 255
 256         return 0;
 257 }
 258
 259 static int rm68200_panel_get_display_timing(struct udevice *dev,
 260                                             struct display_timing *timings)
 261 {
 262         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 263         struct mipi_dsi_device *device = plat->device;
 264         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 265
 266         memcpy(timings, &default_timing, sizeof(*timings));
 267
 268         /* fill characteristics of DSI data link */
 269         device->lanes = priv->lanes;
 270         device->format = priv->format;
 271         device->mode_flags = priv->mode_flags;
 272
 273         return 0;
 274 }
 275
 276 static int rm68200_panel_ofdata_to_platdata(struct udevice *dev)
 277 {
 278         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 279         int ret;
 280
 281         if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
 282                 ret =  device_get_supply_regulator(dev, "power-supply",
 283                                                    &priv->reg);
 284                 if (ret && ret != -ENOENT) {
 285                         dev_err(dev, "Warning: cannot get power supply\n");
 286                         return ret;
 287                 }
 288         }
 289
 290         ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
 291                                    GPIOD_IS_OUT);
 292         if (ret) {
 293                 dev_err(dev, "Warning: cannot get reset GPIO\n");
 294                 if (ret != -ENOENT)
 295                         return ret;
 296         }
 297
 298         ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
 299                                            "backlight", &priv->backlight);
 300         if (ret) {
 301                 dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
 302                 return ret;
 303         }
 304
 305         return 0;
 306 }
 307
 308 static int rm68200_panel_probe(struct udevice *dev)
 309 {
 310         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 311         int ret;
 312
 313         if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
 314                 ret = regulator_set_enable(priv->reg, true);
 315                 if (ret)
 316                         return ret;
 317         }
 318
 319         /* reset panel */
 320         dm_gpio_set_value(&priv->reset, true);
 321         mdelay(1);
 322         dm_gpio_set_value(&priv->reset, false);
 323         mdelay(10);
 324
 325         priv->lanes = 2;
 326         priv->format = MIPI_DSI_FMT_RGB888;
 327         priv->mode_flags = MIPI_DSI_MODE_VIDEO |
 328                            MIPI_DSI_MODE_VIDEO_BURST |
 329                            MIPI_DSI_MODE_LPM;
 330
 331         return 0;
 332 }
 333
 334 static const struct panel_ops rm68200_panel_ops = {
 335         .enable_backlight = rm68200_panel_enable_backlight,
 336         .get_display_timing = rm68200_panel_get_display_timing,
 337 };
 338
 339 static const struct udevice_id rm68200_panel_ids[] = {
 340         { .compatible = "raydium,rm68200" },
 341         { }
 342 };
 343
 344 U_BOOT_DRIVER(rm68200_panel) = {
 345         .name                     = "rm68200_panel",
 346         .id                       = UCLASS_PANEL,
 347         .of_match                 = rm68200_panel_ids,
 348         .ops                      = &rm68200_panel_ops,
 349         .ofdata_to_platdata       = rm68200_panel_ofdata_to_platdata,
 350         .probe                    = rm68200_panel_probe,
 351         .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
 352         .priv_auto_alloc_size   = sizeof(struct rm68200_panel_priv),
 353 };