drivers/video/orisetech_otm8009a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
   4  * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
   5  *            Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
   6  *
   7  * This otm8009a panel driver is inspired from the Linux Kernel driver
   8  * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c.
   9  */
  10 #include <common.h>
  11 #include <backlight.h>
  12 #include <dm.h>
  13 #include <mipi_dsi.h>
  14 #include <panel.h>
  15 #include <asm/gpio.h>
  16 #include <dm/device_compat.h>
  17 #include <power/regulator.h>
  18
  19 #define OTM8009A_BACKLIGHT_DEFAULT      240
  20 #define OTM8009A_BACKLIGHT_MAX          255
  21
  22 /* Manufacturer Command Set */
  23 #define MCS_ADRSFT      0x0000  /* Address Shift Function */
  24 #define MCS_PANSET      0xB3A6  /* Panel Type Setting */
  25 #define MCS_SD_CTRL     0xC0A2  /* Source Driver Timing Setting */
  26 #define MCS_P_DRV_M     0xC0B4  /* Panel Driving Mode */
  27 #define MCS_OSC_ADJ     0xC181  /* Oscillator Adjustment for Idle/Normal mode */
  28 #define MCS_RGB_VID_SET 0xC1A1  /* RGB Video Mode Setting */
  29 #define MCS_SD_PCH_CTRL 0xC480  /* Source Driver Precharge Control */
  30 #define MCS_NO_DOC1     0xC48A  /* Command not documented */
  31 #define MCS_PWR_CTRL1   0xC580  /* Power Control Setting 1 */
  32 #define MCS_PWR_CTRL2   0xC590  /* Power Control Setting 2 for Normal Mode */
  33 #define MCS_PWR_CTRL4   0xC5B0  /* Power Control Setting 4 for DC Voltage */
  34 #define MCS_PANCTRLSET1 0xCB80  /* Panel Control Setting 1 */
  35 #define MCS_PANCTRLSET2 0xCB90  /* Panel Control Setting 2 */
  36 #define MCS_PANCTRLSET3 0xCBA0  /* Panel Control Setting 3 */
  37 #define MCS_PANCTRLSET4 0xCBB0  /* Panel Control Setting 4 */
  38 #define MCS_PANCTRLSET5 0xCBC0  /* Panel Control Setting 5 */
  39 #define MCS_PANCTRLSET6 0xCBD0  /* Panel Control Setting 6 */
  40 #define MCS_PANCTRLSET7 0xCBE0  /* Panel Control Setting 7 */
  41 #define MCS_PANCTRLSET8 0xCBF0  /* Panel Control Setting 8 */
  42 #define MCS_PANU2D1     0xCC80  /* Panel U2D Setting 1 */
  43 #define MCS_PANU2D2     0xCC90  /* Panel U2D Setting 2 */
  44 #define MCS_PANU2D3     0xCCA0  /* Panel U2D Setting 3 */
  45 #define MCS_PAND2U1     0xCCB0  /* Panel D2U Setting 1 */
  46 #define MCS_PAND2U2     0xCCC0  /* Panel D2U Setting 2 */
  47 #define MCS_PAND2U3     0xCCD0  /* Panel D2U Setting 3 */
  48 #define MCS_GOAVST      0xCE80  /* GOA VST Setting */
  49 #define MCS_GOACLKA1    0xCEA0  /* GOA CLKA1 Setting */
  50 #define MCS_GOACLKA3    0xCEB0  /* GOA CLKA3 Setting */
  51 #define MCS_GOAECLK     0xCFC0  /* GOA ECLK Setting */
  52 #define MCS_NO_DOC2     0xCFD0  /* Command not documented */
  53 #define MCS_GVDDSET     0xD800  /* GVDD/NGVDD */
  54 #define MCS_VCOMDC      0xD900  /* VCOM Voltage Setting */
  55 #define MCS_GMCT2_2P    0xE100  /* Gamma Correction 2.2+ Setting */
  56 #define MCS_GMCT2_2N    0xE200  /* Gamma Correction 2.2- Setting */
  57 #define MCS_NO_DOC3     0xF5B6  /* Command not documented */
  58 #define MCS_CMD2_ENA1   0xFF00  /* Enable Access Command2 "CMD2" */
  59 #define MCS_CMD2_ENA2   0xFF80  /* Enable Access Orise Command2 */
  60
  61 struct otm8009a_panel_priv {
  62         struct udevice *reg;
  63         struct gpio_desc reset;
  64         unsigned int lanes;
  65         enum mipi_dsi_pixel_format format;
  66         unsigned long mode_flags;
  67 };
  68
  69 static const struct display_timing default_timing = {
  70         .pixelclock.typ         = 29700000,
  71         .hactive.typ            = 480,
  72         .hfront_porch.typ       = 98,
  73         .hback_porch.typ        = 98,
  74         .hsync_len.typ          = 32,
  75         .vactive.typ            = 800,
  76         .vfront_porch.typ       = 15,
  77         .vback_porch.typ        = 14,
  78         .vsync_len.typ          = 10,
  79 };
  80
  81 static void otm8009a_dcs_write_buf(struct udevice *dev, const void *data,
  82                                    size_t len)
  83 {
  84         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  85         struct mipi_dsi_device *device = plat->device;
  86
  87         if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
  88                 dev_err(dev, "mipi dsi dcs write buffer failed\n");
  89 }
  90
  91 static void otm8009a_dcs_write_buf_hs(struct udevice *dev, const void *data,
  92                                       size_t len)
  93 {
  94         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  95         struct mipi_dsi_device *device = plat->device;
  96
  97         /* data will be sent in dsi hs mode (ie. no lpm) */
  98         device->mode_flags &= ~MIPI_DSI_MODE_LPM;
  99
 100         if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
 101                 dev_err(dev, "mipi dsi dcs write buffer failed\n");
 102
 103         /* restore back the dsi lpm mode */
 104         device->mode_flags |= MIPI_DSI_MODE_LPM;
 105 }
 106
 107 #define dcs_write_seq(dev, seq...)                              \
 108 ({                                                              \
 109         static const u8 d[] = { seq };                          \
 110         otm8009a_dcs_write_buf(dev, d, ARRAY_SIZE(d));          \
 111 })
 112
 113 #define dcs_write_seq_hs(dev, seq...)                           \
 114 ({                                                              \
 115         static const u8 d[] = { seq };                          \
 116         otm8009a_dcs_write_buf_hs(dev, d, ARRAY_SIZE(d));       \
 117 })
 118
 119 #define dcs_write_cmd_at(dev, cmd, seq...)              \
 120 ({                                                      \
 121         static const u16 c = cmd;                       \
 122         struct udevice *device = dev;                   \
 123         dcs_write_seq(device, MCS_ADRSFT, (c) & 0xFF);  \
 124         dcs_write_seq(device, (c) >> 8, seq);           \
 125 })
 126
 127 static int otm8009a_init_sequence(struct udevice *dev)
 128 {
 129         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 130         struct mipi_dsi_device *device = plat->device;
 131         int ret;
 132
 133         /* Enter CMD2 */
 134         dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
 135
 136         /* Enter Orise Command2 */
 137         dcs_write_cmd_at(dev, MCS_CMD2_ENA2, 0x80, 0x09);
 138
 139         dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL, 0x30);
 140         mdelay(10);
 141
 142         dcs_write_cmd_at(dev, MCS_NO_DOC1, 0x40);
 143         mdelay(10);
 144
 145         dcs_write_cmd_at(dev, MCS_PWR_CTRL4 + 1, 0xA9);
 146         dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 1, 0x34);
 147         dcs_write_cmd_at(dev, MCS_P_DRV_M, 0x50);
 148         dcs_write_cmd_at(dev, MCS_VCOMDC, 0x4E);
 149         dcs_write_cmd_at(dev, MCS_OSC_ADJ, 0x66); /* 65Hz */
 150         dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 2, 0x01);
 151         dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 5, 0x34);
 152         dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 4, 0x33);
 153         dcs_write_cmd_at(dev, MCS_GVDDSET, 0x79, 0x79);
 154         dcs_write_cmd_at(dev, MCS_SD_CTRL + 1, 0x1B);
 155         dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 2, 0x83);
 156         dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL + 1, 0x83);
 157         dcs_write_cmd_at(dev, MCS_RGB_VID_SET, 0x0E);
 158         dcs_write_cmd_at(dev, MCS_PANSET, 0x00, 0x01);
 159
 160         dcs_write_cmd_at(dev, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
 161         dcs_write_cmd_at(dev, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
 162                          0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
 163         dcs_write_cmd_at(dev, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
 164                          0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
 165         dcs_write_cmd_at(dev, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
 166                          0x01, 0x02, 0x00, 0x00);
 167
 168         dcs_write_cmd_at(dev, MCS_NO_DOC2, 0x00);
 169
 170         dcs_write_cmd_at(dev, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
 171         dcs_write_cmd_at(dev, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 172                          0, 0, 0, 0, 0);
 173         dcs_write_cmd_at(dev, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 174                          0, 0, 0, 0, 0);
 175         dcs_write_cmd_at(dev, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
 176         dcs_write_cmd_at(dev, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
 177                          0, 0, 0, 0, 0);
 178         dcs_write_cmd_at(dev, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
 179                          4, 0, 0, 0, 0);
 180         dcs_write_cmd_at(dev, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
 181         dcs_write_cmd_at(dev, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 182                          0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
 183
 184         dcs_write_cmd_at(dev, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
 185                          0x00, 0x00, 0x00, 0x00);
 186         dcs_write_cmd_at(dev, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 187                          0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
 188         dcs_write_cmd_at(dev, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
 189                          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 190         dcs_write_cmd_at(dev, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
 191                          0x00, 0x00, 0x00, 0x00);
 192         dcs_write_cmd_at(dev, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 193                          0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
 194         dcs_write_cmd_at(dev, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
 195                          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 196
 197         dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 1, 0x66);
 198
 199         dcs_write_cmd_at(dev, MCS_NO_DOC3, 0x06);
 200
 201         dcs_write_cmd_at(dev, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
 202                          0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
 203                          0x01);
 204         dcs_write_cmd_at(dev, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
 205                          0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
 206                          0x01);
 207
 208         /* Exit CMD2 */
 209         dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
 210
 211         ret =  mipi_dsi_dcs_nop(device);
 212         if (ret)
 213                 return ret;
 214
 215         ret = mipi_dsi_dcs_exit_sleep_mode(device);
 216         if (ret)
 217                 return ret;
 218
 219         /* Wait for sleep out exit */
 220         mdelay(120);
 221
 222         /* Default portrait 480x800 rgb24 */
 223         dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
 224
 225         ret =  mipi_dsi_dcs_set_column_address(device, 0,
 226                                                default_timing.hactive.typ - 1);
 227         if (ret)
 228                 return ret;
 229
 230         ret =  mipi_dsi_dcs_set_page_address(device, 0,
 231                                              default_timing.vactive.typ - 1);
 232         if (ret)
 233                 return ret;
 234
 235         /* See otm8009a driver documentation for pixel format descriptions */
 236         ret =  mipi_dsi_dcs_set_pixel_format(device, MIPI_DCS_PIXEL_FMT_24BIT |
 237                                              MIPI_DCS_PIXEL_FMT_24BIT << 4);
 238         if (ret)
 239                 return ret;
 240
 241         /* Disable CABC feature */
 242         dcs_write_seq(dev, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
 243
 244         ret = mipi_dsi_dcs_set_display_on(device);
 245         if (ret)
 246                 return ret;
 247
 248         ret = mipi_dsi_dcs_nop(device);
 249         if (ret)
 250                 return ret;
 251
 252         /* Send Command GRAM memory write (no parameters) */
 253         dcs_write_seq(dev, MIPI_DCS_WRITE_MEMORY_START);
 254
 255         return 0;
 256 }
 257
 258 static int otm8009a_panel_enable_backlight(struct udevice *dev)
 259 {
 260         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 261         struct mipi_dsi_device *device = plat->device;
 262         int ret;
 263
 264         ret = mipi_dsi_attach(device);
 265         if (ret < 0)
 266                 return ret;
 267
 268         ret = otm8009a_init_sequence(dev);
 269         if (ret)
 270                 return ret;
 271
 272         /*
 273          * Power on the backlight with the requested brightness
 274          * Note We can not use mipi_dsi_dcs_set_display_brightness()
 275          * as otm8009a driver support only 8-bit brightness (1 param).
 276          */
 277         dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
 278                       OTM8009A_BACKLIGHT_DEFAULT);
 279
 280         /* Update Brightness Control & Backlight */
 281         dcs_write_seq(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
 282
 283         /* Update Brightness Control & Backlight */
 284         dcs_write_seq_hs(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY);
 285
 286         /* Need to wait a few time before sending the first image */
 287         mdelay(10);
 288
 289         return 0;
 290 }
 291
 292 static int otm8009a_panel_get_display_timing(struct udevice *dev,
 293                                              struct display_timing *timings)
 294 {
 295         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 296         struct mipi_dsi_device *device = plat->device;
 297         struct otm8009a_panel_priv *priv = dev_get_priv(dev);
 298
 299         memcpy(timings, &default_timing, sizeof(*timings));
 300
 301         /* fill characteristics of DSI data link */
 302         device->lanes = priv->lanes;
 303         device->format = priv->format;
 304         device->mode_flags = priv->mode_flags;
 305
 306         return 0;
 307 }
 308
 309 static int otm8009a_panel_ofdata_to_platdata(struct udevice *dev)
 310 {
 311         struct otm8009a_panel_priv *priv = dev_get_priv(dev);
 312         int ret;
 313
 314         if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
 315                 ret =  device_get_supply_regulator(dev, "power-supply",
 316                                                    &priv->reg);
 317                 if (ret && ret != -ENOENT) {
 318                         dev_err(dev, "Warning: cannot get power supply\n");
 319                         return ret;
 320                 }
 321         }
 322
 323         ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
 324                                    GPIOD_IS_OUT);
 325         if (ret) {
 326                 dev_err(dev, "warning: cannot get reset GPIO\n");
 327                 if (ret != -ENOENT)
 328                         return ret;
 329         }
 330
 331         return 0;
 332 }
 333
 334 static int otm8009a_panel_probe(struct udevice *dev)
 335 {
 336         struct otm8009a_panel_priv *priv = dev_get_priv(dev);
 337         int ret;
 338
 339         if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
 340                 dev_dbg(dev, "enable regulator '%s'\n", priv->reg->name);
 341                 ret = regulator_set_enable(priv->reg, true);
 342                 if (ret)
 343                         return ret;
 344         }
 345
 346         /* reset panel */
 347         dm_gpio_set_value(&priv->reset, true);
 348         mdelay(1); /* >50us */
 349         dm_gpio_set_value(&priv->reset, false);
 350         mdelay(10); /* >5ms */
 351
 352         priv->lanes = 2;
 353         priv->format = MIPI_DSI_FMT_RGB888;
 354         priv->mode_flags = MIPI_DSI_MODE_VIDEO |
 355                            MIPI_DSI_MODE_VIDEO_BURST |
 356                            MIPI_DSI_MODE_LPM;
 357
 358         return 0;
 359 }
 360
 361 static const struct panel_ops otm8009a_panel_ops = {
 362         .enable_backlight = otm8009a_panel_enable_backlight,
 363         .get_display_timing = otm8009a_panel_get_display_timing,
 364 };
 365
 366 static const struct udevice_id otm8009a_panel_ids[] = {
 367         { .compatible = "orisetech,otm8009a" },
 368         { }
 369 };
 370
 371 U_BOOT_DRIVER(otm8009a_panel) = {
 372         .name                     = "otm8009a_panel",
 373         .id                       = UCLASS_PANEL,
 374         .of_match                 = otm8009a_panel_ids,
 375         .ops                      = &otm8009a_panel_ops,
 376         .ofdata_to_platdata       = otm8009a_panel_ofdata_to_platdata,
 377         .probe                    = otm8009a_panel_probe,
 378         .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
 379         .priv_auto_alloc_size   = sizeof(struct otm8009a_panel_priv),
 380 };