drivers/video/mxsfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale i.MX23/i.MX28 LCDIF driver
   4  *
   5  * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
   6  */
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <env.h>
  11 #include <log.h>
  12 #include <asm/cache.h>
  13 #include <dm/device_compat.h>
  14 #include <linux/delay.h>
  15 #include <linux/errno.h>
  16 #include <malloc.h>
  17 #include <video.h>
  18 #include <video_fb.h>
  19
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/mach-imx/dma.h>
  24 #include <asm/io.h>
  25
  26 #include "videomodes.h"
  27
  28 #define PS2KHZ(ps)      (1000000000UL / (ps))
  29 #define HZ2PS(hz)       (1000000000UL / ((hz) / 1000))
  30
  31 #define BITS_PP         18
  32 #define BYTES_PP        4
  33
  34 struct mxs_dma_desc desc;
  35
  36 /**
  37  * mxsfb_system_setup() - Fine-tune LCDIF configuration
  38  *
  39  * This function is used to adjust the LCDIF configuration. This is usually
  40  * needed when driving the controller in System-Mode to operate an 8080 or
  41  * 6800 connected SmartLCD.
  42  */
  43 __weak void mxsfb_system_setup(void)
  44 {
  45 }
  46
  47 /*
  48  * ARIES M28EVK:
  49  * setenv videomode
  50  * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  51  *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  52  *
  53  * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  54  * setenv videomode
  55  * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  56  *       le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  57  */
  58
  59 static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
  60                          struct display_timing *timings, int bpp)
  61 {
  62         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  63         const enum display_flags flags = timings->flags;
  64         uint32_t word_len = 0, bus_width = 0;
  65         uint8_t valid_data = 0;
  66         uint32_t vdctrl0;
  67
  68 #if CONFIG_IS_ENABLED(CLK)
  69         struct clk per_clk;
  70         int ret;
  71
  72         ret = clk_get_by_name(dev, "per", &per_clk);
  73         if (ret) {
  74                 dev_err(dev, "Failed to get mxs clk: %d\n", ret);
  75                 return;
  76         }
  77
  78         ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
  79         if (ret < 0) {
  80                 dev_err(dev, "Failed to set mxs clk: %d\n", ret);
  81                 return;
  82         }
  83
  84         ret = clk_enable(&per_clk);
  85         if (ret < 0) {
  86                 dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
  87                 return;
  88         }
  89 #else
  90         /* Kick in the LCDIF clock */
  91         mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
  92 #endif
  93
  94         /* Restart the LCDIF block */
  95         mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  96
  97         switch (bpp) {
  98         case 24:
  99                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
 100                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
 101                 valid_data = 0x7;
 102                 break;
 103         case 18:
 104                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
 105                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
 106                 valid_data = 0x7;
 107                 break;
 108         case 16:
 109                 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
 110                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
 111                 valid_data = 0xf;
 112                 break;
 113         case 8:
 114                 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
 115                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
 116                 valid_data = 0xf;
 117                 break;
 118         }
 119
 120         writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
 121                 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
 122                 &regs->hw_lcdif_ctrl);
 123
 124         writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
 125                 &regs->hw_lcdif_ctrl1);
 126
 127         mxsfb_system_setup();
 128
 129         writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
 130                 timings->hactive.typ, &regs->hw_lcdif_transfer_count);
 131
 132         vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
 133                   LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 134                   LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 135                   timings->vsync_len.typ;
 136
 137         if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
 138                 vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
 139         if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
 140                 vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
 141         if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 142                 vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
 143         if(flags & DISPLAY_FLAGS_DE_HIGH)
 144                 vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
 145
 146         writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
 147         writel(timings->vback_porch.typ + timings->vfront_porch.typ +
 148                 timings->vsync_len.typ + timings->vactive.typ,
 149                 &regs->hw_lcdif_vdctrl1);
 150         writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
 151                 (timings->hback_porch.typ + timings->hfront_porch.typ +
 152                 timings->hsync_len.typ + timings->hactive.typ),
 153                 &regs->hw_lcdif_vdctrl2);
 154         writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
 155                 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
 156                 (timings->vback_porch.typ + timings->vsync_len.typ),
 157                 &regs->hw_lcdif_vdctrl3);
 158         writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
 159                 &regs->hw_lcdif_vdctrl4);
 160
 161         writel(fb_addr, &regs->hw_lcdif_cur_buf);
 162         writel(fb_addr, &regs->hw_lcdif_next_buf);
 163
 164         /* Flush FIFO first */
 165         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
 166
 167 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
 168         /* Sync signals ON */
 169         setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
 170 #endif
 171
 172         /* FIFO cleared */
 173         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
 174
 175         /* RUN! */
 176         writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 177 }
 178
 179 static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
 180                             int bpp, u32 fb)
 181 {
 182         /* Start framebuffer */
 183         mxs_lcd_init(dev, fb, timings, bpp);
 184
 185 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
 186         /*
 187          * If the LCD runs in system mode, the LCD refresh has to be triggered
 188          * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
 189          * having to set this bit manually after every single change in the
 190          * framebuffer memory, we set up specially crafted circular DMA, which
 191          * sets the RUN bit, then waits until it gets cleared and repeats this
 192          * infinitelly. This way, we get smooth continuous updates of the LCD.
 193          */
 194         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 195
 196         memset(&desc, 0, sizeof(struct mxs_dma_desc));
 197         desc.address = (dma_addr_t)&desc;
 198         desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
 199                         MXS_DMA_DESC_WAIT4END |
 200                         (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
 201         desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
 202         desc.cmd.next = (uint32_t)&desc.cmd;
 203
 204         /* Execute the DMA chain. */
 205         mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
 206 #endif
 207
 208         return 0;
 209 }
 210
 211 static int mxs_remove_common(u32 fb)
 212 {
 213         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 214         int timeout = 1000000;
 215
 216         if (!fb)
 217                 return -EINVAL;
 218
 219         writel(fb, &regs->hw_lcdif_cur_buf_reg);
 220         writel(fb, &regs->hw_lcdif_next_buf_reg);
 221         writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
 222         while (--timeout) {
 223                 if (readl(&regs->hw_lcdif_ctrl1_reg) &
 224                     LCDIF_CTRL1_VSYNC_EDGE_IRQ)
 225                         break;
 226                 udelay(1);
 227         }
 228         mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
 229
 230         return 0;
 231 }
 232
 233 #ifndef CONFIG_DM_VIDEO
 234
 235 static GraphicDevice panel;
 236
 237 void lcdif_power_down(void)
 238 {
 239         mxs_remove_common(panel.frameAdrs);
 240 }
 241
 242 void *video_hw_init(void)
 243 {
 244         int bpp = -1;
 245         int ret = 0;
 246         char *penv;
 247         void *fb = NULL;
 248         struct ctfb_res_modes mode;
 249         struct display_timing timings;
 250
 251         puts("Video: ");
 252
 253         /* Suck display configuration from "videomode" variable */
 254         penv = env_get("videomode");
 255         if (!penv) {
 256                 puts("MXSFB: 'videomode' variable not set!\n");
 257                 return NULL;
 258         }
 259
 260         bpp = video_get_params(&mode, penv);
 261
 262         /* fill in Graphic device struct */
 263         sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
 264
 265         panel.winSizeX = mode.xres;
 266         panel.winSizeY = mode.yres;
 267         panel.plnSizeX = mode.xres;
 268         panel.plnSizeY = mode.yres;
 269
 270         switch (bpp) {
 271         case 24:
 272         case 18:
 273                 panel.gdfBytesPP = 4;
 274                 panel.gdfIndex = GDF_32BIT_X888RGB;
 275                 break;
 276         case 16:
 277                 panel.gdfBytesPP = 2;
 278                 panel.gdfIndex = GDF_16BIT_565RGB;
 279                 break;
 280         case 8:
 281                 panel.gdfBytesPP = 1;
 282                 panel.gdfIndex = GDF__8BIT_INDEX;
 283                 break;
 284         default:
 285                 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
 286                 return NULL;
 287         }
 288
 289         panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
 290
 291         /* Allocate framebuffer */
 292         fb = memalign(ARCH_DMA_MINALIGN,
 293                       roundup(panel.memSize, ARCH_DMA_MINALIGN));
 294         if (!fb) {
 295                 printf("MXSFB: Error allocating framebuffer!\n");
 296                 return NULL;
 297         }
 298
 299         /* Wipe framebuffer */
 300         memset(fb, 0, panel.memSize);
 301
 302         panel.frameAdrs = (u32)fb;
 303
 304         printf("%s\n", panel.modeIdent);
 305
 306         video_ctfb_mode_to_display_timing(&mode, &timings);
 307
 308         ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
 309         if (ret)
 310                 goto dealloc_fb;
 311
 312         return (void *)&panel;
 313
 314 dealloc_fb:
 315         free(fb);
 316
 317         return NULL;
 318 }
 319 #else /* ifndef CONFIG_DM_VIDEO */
 320
 321 static int mxs_of_get_timings(struct udevice *dev,
 322                               struct display_timing *timings,
 323                               u32 *bpp)
 324 {
 325         int ret = 0;
 326         u32 display_phandle;
 327         ofnode display_node;
 328
 329         ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
 330         if (ret) {
 331                 dev_err(dev, "required display property isn't provided\n");
 332                 return -EINVAL;
 333         }
 334
 335         display_node = ofnode_get_by_phandle(display_phandle);
 336         if (!ofnode_valid(display_node)) {
 337                 dev_err(dev, "failed to find display subnode\n");
 338                 return -EINVAL;
 339         }
 340
 341         ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
 342         if (ret) {
 343                 dev_err(dev,
 344                         "required bits-per-pixel property isn't provided\n");
 345                 return -EINVAL;
 346         }
 347
 348         ret = ofnode_decode_display_timing(display_node, 0, timings);
 349         if (ret) {
 350                 dev_err(dev, "failed to get any display timings\n");
 351                 return -EINVAL;
 352         }
 353
 354         return ret;
 355 }
 356
 357 static int mxs_video_probe(struct udevice *dev)
 358 {
 359         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 360         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 361
 362         struct display_timing timings;
 363         u32 bpp = 0;
 364         u32 fb_start, fb_end;
 365         int ret;
 366
 367         debug("%s() plat: base 0x%lx, size 0x%x\n",
 368                __func__, plat->base, plat->size);
 369
 370         ret = mxs_of_get_timings(dev, &timings, &bpp);
 371         if (ret)
 372                 return ret;
 373
 374         ret = mxs_probe_common(dev, &timings, bpp, plat->base);
 375         if (ret)
 376                 return ret;
 377
 378         switch (bpp) {
 379         case 32:
 380         case 24:
 381         case 18:
 382                 uc_priv->bpix = VIDEO_BPP32;
 383                 break;
 384         case 16:
 385                 uc_priv->bpix = VIDEO_BPP16;
 386                 break;
 387         case 8:
 388                 uc_priv->bpix = VIDEO_BPP8;
 389                 break;
 390         default:
 391                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 392                 return -EINVAL;
 393         }
 394
 395         uc_priv->xsize = timings.hactive.typ;
 396         uc_priv->ysize = timings.vactive.typ;
 397
 398         /* Enable dcache for the frame buffer */
 399         fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
 400         fb_end = plat->base + plat->size;
 401         fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
 402         mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 403                                         DCACHE_WRITEBACK);
 404         video_set_flush_dcache(dev, true);
 405         gd->fb_base = plat->base;
 406
 407         return ret;
 408 }
 409
 410 static int mxs_video_bind(struct udevice *dev)
 411 {
 412         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 413         struct display_timing timings;
 414         u32 bpp = 0;
 415         u32 bytes_pp = 0;
 416         int ret;
 417
 418         ret = mxs_of_get_timings(dev, &timings, &bpp);
 419         if (ret)
 420                 return ret;
 421
 422         switch (bpp) {
 423         case 32:
 424         case 24:
 425         case 18:
 426                 bytes_pp = 4;
 427                 break;
 428         case 16:
 429                 bytes_pp = 2;
 430                 break;
 431         case 8:
 432                 bytes_pp = 1;
 433                 break;
 434         default:
 435                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 436                 return -EINVAL;
 437         }
 438
 439         plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
 440
 441         return 0;
 442 }
 443
 444 static int mxs_video_remove(struct udevice *dev)
 445 {
 446         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 447
 448         mxs_remove_common(plat->base);
 449
 450         return 0;
 451 }
 452
 453 static const struct udevice_id mxs_video_ids[] = {
 454         { .compatible = "fsl,imx23-lcdif" },
 455         { .compatible = "fsl,imx28-lcdif" },
 456         { .compatible = "fsl,imx7ulp-lcdif" },
 457         { .compatible = "fsl,imxrt-lcdif" },
 458         { /* sentinel */ }
 459 };
 460
 461 U_BOOT_DRIVER(mxs_video) = {
 462         .name   = "mxs_video",
 463         .id     = UCLASS_VIDEO,
 464         .of_match = mxs_video_ids,
 465         .bind   = mxs_video_bind,
 466         .probe  = mxs_video_probe,
 467         .remove = mxs_video_remove,
 468         .flags  = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
 469 };
 470 #endif /* ifndef CONFIG_DM_VIDEO */