1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX23/i.MX28 LCDIF driver
5 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
14 #include <linux/errno.h>
17 #include <asm/mach-imx/dma.h>
19 #include "videomodes.h"
21 #define PS2KHZ(ps) (1000000000UL / (ps))
23 static GraphicDevice panel;
24 struct mxs_dma_desc desc;
27 * mxsfb_system_setup() - Fine-tune LCDIF configuration
29 * This function is used to adjust the LCDIF configuration. This is usually
30 * needed when driving the controller in System-Mode to operate an 8080 or
31 * 6800 connected SmartLCD.
33 __weak void mxsfb_system_setup(void)
40 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
41 * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
43 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
45 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
46 * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
49 static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
51 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
52 uint32_t word_len = 0, bus_width = 0;
53 uint8_t valid_data = 0;
55 /* Kick in the LCDIF clock */
56 mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
58 /* Restart the LCDIF block */
59 mxs_reset_block(®s->hw_lcdif_ctrl_reg);
63 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
64 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
68 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
69 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
73 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
74 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
78 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
79 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
84 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
85 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
86 ®s->hw_lcdif_ctrl);
88 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
89 ®s->hw_lcdif_ctrl1);
93 writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
94 ®s->hw_lcdif_transfer_count);
96 writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
97 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
98 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
99 mode->vsync_len, ®s->hw_lcdif_vdctrl0);
100 writel(mode->upper_margin + mode->lower_margin +
101 mode->vsync_len + mode->yres,
102 ®s->hw_lcdif_vdctrl1);
103 writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
104 (mode->left_margin + mode->right_margin +
105 mode->hsync_len + mode->xres),
106 ®s->hw_lcdif_vdctrl2);
107 writel(((mode->left_margin + mode->hsync_len) <<
108 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
109 (mode->upper_margin + mode->vsync_len),
110 ®s->hw_lcdif_vdctrl3);
111 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
112 ®s->hw_lcdif_vdctrl4);
114 writel(fb_addr, ®s->hw_lcdif_cur_buf);
115 writel(fb_addr, ®s->hw_lcdif_next_buf);
117 /* Flush FIFO first */
118 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
120 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
121 /* Sync signals ON */
122 setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
126 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
129 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
132 void lcdif_power_down(void)
134 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
135 int timeout = 1000000;
137 if (!panel.frameAdrs)
140 writel(panel.frameAdrs, ®s->hw_lcdif_cur_buf_reg);
141 writel(panel.frameAdrs, ®s->hw_lcdif_next_buf_reg);
142 writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
144 if (readl(®s->hw_lcdif_ctrl1_reg) &
145 LCDIF_CTRL1_VSYNC_EDGE_IRQ)
149 mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
152 void *video_hw_init(void)
157 struct ctfb_res_modes mode;
161 /* Suck display configuration from "videomode" variable */
162 penv = env_get("videomode");
164 puts("MXSFB: 'videomode' variable not set!\n");
168 bpp = video_get_params(&mode, penv);
170 /* fill in Graphic device struct */
171 sprintf(panel.modeIdent, "%dx%dx%d",
172 mode.xres, mode.yres, bpp);
174 panel.winSizeX = mode.xres;
175 panel.winSizeY = mode.yres;
176 panel.plnSizeX = mode.xres;
177 panel.plnSizeY = mode.yres;
182 panel.gdfBytesPP = 4;
183 panel.gdfIndex = GDF_32BIT_X888RGB;
186 panel.gdfBytesPP = 2;
187 panel.gdfIndex = GDF_16BIT_565RGB;
190 panel.gdfBytesPP = 1;
191 panel.gdfIndex = GDF__8BIT_INDEX;
194 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
198 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
200 /* Allocate framebuffer */
201 fb = memalign(ARCH_DMA_MINALIGN,
202 roundup(panel.memSize, ARCH_DMA_MINALIGN));
204 printf("MXSFB: Error allocating framebuffer!\n");
208 /* Wipe framebuffer */
209 memset(fb, 0, panel.memSize);
211 panel.frameAdrs = (u32)fb;
213 printf("%s\n", panel.modeIdent);
215 /* Start framebuffer */
216 mxs_lcd_init(panel.frameAdrs, &mode, bpp);
218 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
220 * If the LCD runs in system mode, the LCD refresh has to be triggered
221 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
222 * having to set this bit manually after every single change in the
223 * framebuffer memory, we set up specially crafted circular DMA, which
224 * sets the RUN bit, then waits until it gets cleared and repeats this
225 * infinitelly. This way, we get smooth continuous updates of the LCD.
227 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
229 memset(&desc, 0, sizeof(struct mxs_dma_desc));
230 desc.address = (dma_addr_t)&desc;
231 desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
232 MXS_DMA_DESC_WAIT4END |
233 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
234 desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
235 desc.cmd.next = (uint32_t)&desc.cmd;
237 /* Execute the DMA chain. */
238 mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
241 return (void *)&panel;