drivers/video/mxsfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale i.MX23/i.MX28 LCDIF driver
   4  *
   5  * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
   6  */
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <env.h>
  11 #include <log.h>
  12 #include <asm/cache.h>
  13 #include <dm/device_compat.h>
  14 #include <linux/errno.h>
  15 #include <malloc.h>
  16 #include <video.h>
  17 #include <video_fb.h>
  18
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/mach-imx/dma.h>
  23 #include <asm/io.h>
  24
  25 #include "videomodes.h"
  26
  27 #define PS2KHZ(ps)      (1000000000UL / (ps))
  28 #define HZ2PS(hz)       (1000000000UL / ((hz) / 1000))
  29
  30 #define BITS_PP         18
  31 #define BYTES_PP        4
  32
  33 struct mxs_dma_desc desc;
  34
  35 /**
  36  * mxsfb_system_setup() - Fine-tune LCDIF configuration
  37  *
  38  * This function is used to adjust the LCDIF configuration. This is usually
  39  * needed when driving the controller in System-Mode to operate an 8080 or
  40  * 6800 connected SmartLCD.
  41  */
  42 __weak void mxsfb_system_setup(void)
  43 {
  44 }
  45
  46 /*
  47  * ARIES M28EVK:
  48  * setenv videomode
  49  * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  50  *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  51  *
  52  * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  53  * setenv videomode
  54  * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  55  *       le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  56  */
  57
  58 static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
  59                          struct display_timing *timings, int bpp)
  60 {
  61         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  62         const enum display_flags flags = timings->flags;
  63         uint32_t word_len = 0, bus_width = 0;
  64         uint8_t valid_data = 0;
  65         uint32_t vdctrl0;
  66
  67 #if CONFIG_IS_ENABLED(CLK)
  68         struct clk per_clk;
  69         int ret;
  70
  71         ret = clk_get_by_name(dev, "per", &per_clk);
  72         if (ret) {
  73                 dev_err(dev, "Failed to get mxs clk: %d\n", ret);
  74                 return;
  75         }
  76
  77         ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
  78         if (ret < 0) {
  79                 dev_err(dev, "Failed to set mxs clk: %d\n", ret);
  80                 return;
  81         }
  82
  83         ret = clk_enable(&per_clk);
  84         if (ret < 0) {
  85                 dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
  86                 return;
  87         }
  88 #else
  89         /* Kick in the LCDIF clock */
  90         mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
  91 #endif
  92
  93         /* Restart the LCDIF block */
  94         mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  95
  96         switch (bpp) {
  97         case 24:
  98                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  99                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
 100                 valid_data = 0x7;
 101                 break;
 102         case 18:
 103                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
 104                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
 105                 valid_data = 0x7;
 106                 break;
 107         case 16:
 108                 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
 109                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
 110                 valid_data = 0xf;
 111                 break;
 112         case 8:
 113                 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
 114                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
 115                 valid_data = 0xf;
 116                 break;
 117         }
 118
 119         writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
 120                 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
 121                 &regs->hw_lcdif_ctrl);
 122
 123         writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
 124                 &regs->hw_lcdif_ctrl1);
 125
 126         mxsfb_system_setup();
 127
 128         writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
 129                 timings->hactive.typ, &regs->hw_lcdif_transfer_count);
 130
 131         vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
 132                   LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 133                   LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 134                   timings->vsync_len.typ;
 135
 136         if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
 137                 vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
 138         if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
 139                 vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
 140         if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 141                 vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
 142         if(flags & DISPLAY_FLAGS_DE_HIGH)
 143                 vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
 144
 145         writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
 146         writel(timings->vback_porch.typ + timings->vfront_porch.typ +
 147                 timings->vsync_len.typ + timings->vactive.typ,
 148                 &regs->hw_lcdif_vdctrl1);
 149         writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
 150                 (timings->hback_porch.typ + timings->hfront_porch.typ +
 151                 timings->hsync_len.typ + timings->hactive.typ),
 152                 &regs->hw_lcdif_vdctrl2);
 153         writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
 154                 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
 155                 (timings->vback_porch.typ + timings->vsync_len.typ),
 156                 &regs->hw_lcdif_vdctrl3);
 157         writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
 158                 &regs->hw_lcdif_vdctrl4);
 159
 160         writel(fb_addr, &regs->hw_lcdif_cur_buf);
 161         writel(fb_addr, &regs->hw_lcdif_next_buf);
 162
 163         /* Flush FIFO first */
 164         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
 165
 166 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
 167         /* Sync signals ON */
 168         setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
 169 #endif
 170
 171         /* FIFO cleared */
 172         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
 173
 174         /* RUN! */
 175         writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 176 }
 177
 178 static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
 179                             int bpp, u32 fb)
 180 {
 181         /* Start framebuffer */
 182         mxs_lcd_init(dev, fb, timings, bpp);
 183
 184 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
 185         /*
 186          * If the LCD runs in system mode, the LCD refresh has to be triggered
 187          * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
 188          * having to set this bit manually after every single change in the
 189          * framebuffer memory, we set up specially crafted circular DMA, which
 190          * sets the RUN bit, then waits until it gets cleared and repeats this
 191          * infinitelly. This way, we get smooth continuous updates of the LCD.
 192          */
 193         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 194
 195         memset(&desc, 0, sizeof(struct mxs_dma_desc));
 196         desc.address = (dma_addr_t)&desc;
 197         desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
 198                         MXS_DMA_DESC_WAIT4END |
 199                         (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
 200         desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
 201         desc.cmd.next = (uint32_t)&desc.cmd;
 202
 203         /* Execute the DMA chain. */
 204         mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
 205 #endif
 206
 207         return 0;
 208 }
 209
 210 static int mxs_remove_common(u32 fb)
 211 {
 212         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 213         int timeout = 1000000;
 214
 215         if (!fb)
 216                 return -EINVAL;
 217
 218         writel(fb, &regs->hw_lcdif_cur_buf_reg);
 219         writel(fb, &regs->hw_lcdif_next_buf_reg);
 220         writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
 221         while (--timeout) {
 222                 if (readl(&regs->hw_lcdif_ctrl1_reg) &
 223                     LCDIF_CTRL1_VSYNC_EDGE_IRQ)
 224                         break;
 225                 udelay(1);
 226         }
 227         mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
 228
 229         return 0;
 230 }
 231
 232 #ifndef CONFIG_DM_VIDEO
 233
 234 static GraphicDevice panel;
 235
 236 void lcdif_power_down(void)
 237 {
 238         mxs_remove_common(panel.frameAdrs);
 239 }
 240
 241 void *video_hw_init(void)
 242 {
 243         int bpp = -1;
 244         int ret = 0;
 245         char *penv;
 246         void *fb = NULL;
 247         struct ctfb_res_modes mode;
 248         struct display_timing timings;
 249
 250         puts("Video: ");
 251
 252         /* Suck display configuration from "videomode" variable */
 253         penv = env_get("videomode");
 254         if (!penv) {
 255                 puts("MXSFB: 'videomode' variable not set!\n");
 256                 return NULL;
 257         }
 258
 259         bpp = video_get_params(&mode, penv);
 260
 261         /* fill in Graphic device struct */
 262         sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
 263
 264         panel.winSizeX = mode.xres;
 265         panel.winSizeY = mode.yres;
 266         panel.plnSizeX = mode.xres;
 267         panel.plnSizeY = mode.yres;
 268
 269         switch (bpp) {
 270         case 24:
 271         case 18:
 272                 panel.gdfBytesPP = 4;
 273                 panel.gdfIndex = GDF_32BIT_X888RGB;
 274                 break;
 275         case 16:
 276                 panel.gdfBytesPP = 2;
 277                 panel.gdfIndex = GDF_16BIT_565RGB;
 278                 break;
 279         case 8:
 280                 panel.gdfBytesPP = 1;
 281                 panel.gdfIndex = GDF__8BIT_INDEX;
 282                 break;
 283         default:
 284                 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
 285                 return NULL;
 286         }
 287
 288         panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
 289
 290         /* Allocate framebuffer */
 291         fb = memalign(ARCH_DMA_MINALIGN,
 292                       roundup(panel.memSize, ARCH_DMA_MINALIGN));
 293         if (!fb) {
 294                 printf("MXSFB: Error allocating framebuffer!\n");
 295                 return NULL;
 296         }
 297
 298         /* Wipe framebuffer */
 299         memset(fb, 0, panel.memSize);
 300
 301         panel.frameAdrs = (u32)fb;
 302
 303         printf("%s\n", panel.modeIdent);
 304
 305         video_ctfb_mode_to_display_timing(&mode, &timings);
 306
 307         ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
 308         if (ret)
 309                 goto dealloc_fb;
 310
 311         return (void *)&panel;
 312
 313 dealloc_fb:
 314         free(fb);
 315
 316         return NULL;
 317 }
 318 #else /* ifndef CONFIG_DM_VIDEO */
 319
 320 static int mxs_of_get_timings(struct udevice *dev,
 321                               struct display_timing *timings,
 322                               u32 *bpp)
 323 {
 324         int ret = 0;
 325         u32 display_phandle;
 326         ofnode display_node;
 327
 328         ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
 329         if (ret) {
 330                 dev_err(dev, "required display property isn't provided\n");
 331                 return -EINVAL;
 332         }
 333
 334         display_node = ofnode_get_by_phandle(display_phandle);
 335         if (!ofnode_valid(display_node)) {
 336                 dev_err(dev, "failed to find display subnode\n");
 337                 return -EINVAL;
 338         }
 339
 340         ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
 341         if (ret) {
 342                 dev_err(dev,
 343                         "required bits-per-pixel property isn't provided\n");
 344                 return -EINVAL;
 345         }
 346
 347         ret = ofnode_decode_display_timing(display_node, 0, timings);
 348         if (ret) {
 349                 dev_err(dev, "failed to get any display timings\n");
 350                 return -EINVAL;
 351         }
 352
 353         return ret;
 354 }
 355
 356 static int mxs_video_probe(struct udevice *dev)
 357 {
 358         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 359         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 360
 361         struct display_timing timings;
 362         u32 bpp = 0;
 363         u32 fb_start, fb_end;
 364         int ret;
 365
 366         debug("%s() plat: base 0x%lx, size 0x%x\n",
 367                __func__, plat->base, plat->size);
 368
 369         ret = mxs_of_get_timings(dev, &timings, &bpp);
 370         if (ret)
 371                 return ret;
 372
 373         ret = mxs_probe_common(dev, &timings, bpp, plat->base);
 374         if (ret)
 375                 return ret;
 376
 377         switch (bpp) {
 378         case 32:
 379         case 24:
 380         case 18:
 381                 uc_priv->bpix = VIDEO_BPP32;
 382                 break;
 383         case 16:
 384                 uc_priv->bpix = VIDEO_BPP16;
 385                 break;
 386         case 8:
 387                 uc_priv->bpix = VIDEO_BPP8;
 388                 break;
 389         default:
 390                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 391                 return -EINVAL;
 392         }
 393
 394         uc_priv->xsize = timings.hactive.typ;
 395         uc_priv->ysize = timings.vactive.typ;
 396
 397         /* Enable dcache for the frame buffer */
 398         fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
 399         fb_end = plat->base + plat->size;
 400         fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
 401         mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 402                                         DCACHE_WRITEBACK);
 403         video_set_flush_dcache(dev, true);
 404         gd->fb_base = plat->base;
 405
 406         return ret;
 407 }
 408
 409 static int mxs_video_bind(struct udevice *dev)
 410 {
 411         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 412         struct display_timing timings;
 413         u32 bpp = 0;
 414         u32 bytes_pp = 0;
 415         int ret;
 416
 417         ret = mxs_of_get_timings(dev, &timings, &bpp);
 418         if (ret)
 419                 return ret;
 420
 421         switch (bpp) {
 422         case 32:
 423         case 24:
 424         case 18:
 425                 bytes_pp = 4;
 426                 break;
 427         case 16:
 428                 bytes_pp = 2;
 429                 break;
 430         case 8:
 431                 bytes_pp = 1;
 432                 break;
 433         default:
 434                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 435                 return -EINVAL;
 436         }
 437
 438         plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
 439
 440         return 0;
 441 }
 442
 443 static int mxs_video_remove(struct udevice *dev)
 444 {
 445         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 446
 447         mxs_remove_common(plat->base);
 448
 449         return 0;
 450 }
 451
 452 static const struct udevice_id mxs_video_ids[] = {
 453         { .compatible = "fsl,imx23-lcdif" },
 454         { .compatible = "fsl,imx28-lcdif" },
 455         { .compatible = "fsl,imx7ulp-lcdif" },
 456         { .compatible = "fsl,imxrt-lcdif" },
 457         { /* sentinel */ }
 458 };
 459
 460 U_BOOT_DRIVER(mxs_video) = {
 461         .name   = "mxs_video",
 462         .id     = UCLASS_VIDEO,
 463         .of_match = mxs_video_ids,
 464         .bind   = mxs_video_bind,
 465         .probe  = mxs_video_probe,
 466         .remove = mxs_video_remove,
 467         .flags  = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
 468 };
 469 #endif /* ifndef CONFIG_DM_VIDEO */