1 // SPDX-License-Identifier: GPL-2.0+
4 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
6 * HALE electronic GmbH, <helmut.raiger@hale.at>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <linux/errno.h>
19 #include "videomodes.h"
21 /* this might need panel specific set-up as-well */
24 /* -------------- controller specific stuff -------------- */
26 /* IPU DMA Controller channel definitions. */
28 IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
29 IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
37 IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
44 IDMAC_SDC_0 = 14, /* Background synchronous display data */
45 IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
64 /* More formats can be copied from the Linux driver if needed */
74 struct pixel_fmt_cfg {
81 static struct pixel_fmt_cfg fmt_cfg[] = {
82 [IPU_PIX_FMT_RGB24] = {
83 0x1600AAAA, 0x00E05555, 0x00070000, 3,
85 [IPU_PIX_FMT_RGB666] = {
86 0x0005000F, 0x000B000F, 0x0011000F, 1,
88 [IPU_PIX_FMT_BGR666] = {
89 0x0011000F, 0x000B000F, 0x0005000F, 1,
91 [IPU_PIX_FMT_RGB565] = {
92 0x0004003F, 0x000A000F, 0x000F003F, 1,
101 /* IPU Common registers */
102 /* IPU_CONF and its bits already defined in imx-regs.h */
103 #define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
104 #define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
105 #define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)
106 #define IPU_CHA_CUR_BUF (0x10 + IPU_BASE)
107 #define IPU_FS_PROC_FLOW (0x14 + IPU_BASE)
108 #define IPU_FS_DISP_FLOW (0x18 + IPU_BASE)
109 #define IPU_TASKS_STAT (0x1C + IPU_BASE)
110 #define IPU_IMA_ADDR (0x20 + IPU_BASE)
111 #define IPU_IMA_DATA (0x24 + IPU_BASE)
112 #define IPU_INT_CTRL_1 (0x28 + IPU_BASE)
113 #define IPU_INT_CTRL_2 (0x2C + IPU_BASE)
114 #define IPU_INT_CTRL_3 (0x30 + IPU_BASE)
115 #define IPU_INT_CTRL_4 (0x34 + IPU_BASE)
116 #define IPU_INT_CTRL_5 (0x38 + IPU_BASE)
117 #define IPU_INT_STAT_1 (0x3C + IPU_BASE)
118 #define IPU_INT_STAT_2 (0x40 + IPU_BASE)
119 #define IPU_INT_STAT_3 (0x44 + IPU_BASE)
120 #define IPU_INT_STAT_4 (0x48 + IPU_BASE)
121 #define IPU_INT_STAT_5 (0x4C + IPU_BASE)
122 #define IPU_BRK_CTRL_1 (0x50 + IPU_BASE)
123 #define IPU_BRK_CTRL_2 (0x54 + IPU_BASE)
124 #define IPU_BRK_STAT (0x58 + IPU_BASE)
125 #define IPU_DIAGB_CTRL (0x5C + IPU_BASE)
127 /* Image Converter Registers */
128 #define IC_CONF (0x88 + IPU_BASE)
129 #define IC_PRP_ENC_RSC (0x8C + IPU_BASE)
130 #define IC_PRP_VF_RSC (0x90 + IPU_BASE)
131 #define IC_PP_RSC (0x94 + IPU_BASE)
132 #define IC_CMBP_1 (0x98 + IPU_BASE)
133 #define IC_CMBP_2 (0x9C + IPU_BASE)
134 #define PF_CONF (0xA0 + IPU_BASE)
135 #define IDMAC_CONF (0xA4 + IPU_BASE)
136 #define IDMAC_CHA_EN (0xA8 + IPU_BASE)
137 #define IDMAC_CHA_PRI (0xAC + IPU_BASE)
138 #define IDMAC_CHA_BUSY (0xB0 + IPU_BASE)
140 /* Image Converter Register bits */
141 #define IC_CONF_PRPENC_EN 0x00000001
142 #define IC_CONF_PRPENC_CSC1 0x00000002
143 #define IC_CONF_PRPENC_ROT_EN 0x00000004
144 #define IC_CONF_PRPVF_EN 0x00000100
145 #define IC_CONF_PRPVF_CSC1 0x00000200
146 #define IC_CONF_PRPVF_CSC2 0x00000400
147 #define IC_CONF_PRPVF_CMB 0x00000800
148 #define IC_CONF_PRPVF_ROT_EN 0x00001000
149 #define IC_CONF_PP_EN 0x00010000
150 #define IC_CONF_PP_CSC1 0x00020000
151 #define IC_CONF_PP_CSC2 0x00040000
152 #define IC_CONF_PP_CMB 0x00080000
153 #define IC_CONF_PP_ROT_EN 0x00100000
154 #define IC_CONF_IC_GLB_LOC_A 0x10000000
155 #define IC_CONF_KEY_COLOR_EN 0x20000000
156 #define IC_CONF_RWS_EN 0x40000000
157 #define IC_CONF_CSI_MEM_WR_EN 0x80000000
160 #define SDC_COM_CONF (0xB4 + IPU_BASE)
161 #define SDC_GW_CTRL (0xB8 + IPU_BASE)
162 #define SDC_FG_POS (0xBC + IPU_BASE)
163 #define SDC_BG_POS (0xC0 + IPU_BASE)
164 #define SDC_CUR_POS (0xC4 + IPU_BASE)
165 #define SDC_PWM_CTRL (0xC8 + IPU_BASE)
166 #define SDC_CUR_MAP (0xCC + IPU_BASE)
167 #define SDC_HOR_CONF (0xD0 + IPU_BASE)
168 #define SDC_VER_CONF (0xD4 + IPU_BASE)
169 #define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE)
170 #define SDC_SHARP_CONF_2 (0xDC + IPU_BASE)
173 #define SDC_COM_TFT_COLOR 0x00000001UL
174 #define SDC_COM_FG_EN 0x00000010UL
175 #define SDC_COM_GWSEL 0x00000020UL
176 #define SDC_COM_GLB_A 0x00000040UL
177 #define SDC_COM_KEY_COLOR_G 0x00000080UL
178 #define SDC_COM_BG_EN 0x00000200UL
179 #define SDC_COM_SHARP 0x00001000UL
181 #define SDC_V_SYNC_WIDTH_L 0x00000001UL
183 /* Display Interface registers */
184 #define DI_DISP_IF_CONF (0x0124 + IPU_BASE)
185 #define DI_DISP_SIG_POL (0x0128 + IPU_BASE)
186 #define DI_SER_DISP1_CONF (0x012C + IPU_BASE)
187 #define DI_SER_DISP2_CONF (0x0130 + IPU_BASE)
188 #define DI_HSP_CLK_PER (0x0134 + IPU_BASE)
189 #define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE)
190 #define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE)
191 #define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE)
192 #define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE)
193 #define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE)
194 #define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE)
195 #define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE)
196 #define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE)
197 #define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE)
198 #define DI_DISP3_TIME_CONF (0x015C + IPU_BASE)
199 #define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE)
200 #define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE)
201 #define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE)
202 #define DI_DISP0_CB0_MAP (0x016C + IPU_BASE)
203 #define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE)
204 #define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE)
205 #define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE)
206 #define DI_DISP1_DB1_MAP (0x017C + IPU_BASE)
207 #define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE)
208 #define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE)
209 #define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE)
210 #define DI_DISP1_CB2_MAP (0x018C + IPU_BASE)
211 #define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE)
212 #define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE)
213 #define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE)
214 #define DI_DISP2_CB0_MAP (0x019C + IPU_BASE)
215 #define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE)
216 #define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE)
217 #define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE)
218 #define DI_DISP3_B1_MAP (0x01AC + IPU_BASE)
219 #define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE)
220 #define DI_DISP_ACC_CC (0x01B4 + IPU_BASE)
221 #define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE)
222 #define DI_DISP_LLA_DATA (0x01BC + IPU_BASE)
224 /* DI_DISP_SIG_POL bits */
225 #define DI_D3_VSYNC_POL (1 << 28)
226 #define DI_D3_HSYNC_POL (1 << 27)
227 #define DI_D3_DRDY_SHARP_POL (1 << 26)
228 #define DI_D3_CLK_POL (1 << 25)
229 #define DI_D3_DATA_POL (1 << 24)
231 /* DI_DISP_IF_CONF bits */
232 #define DI_D3_CLK_IDLE (1 << 26)
233 #define DI_D3_CLK_SEL (1 << 25)
234 #define DI_D3_DATAMSK (1 << 24)
236 #define IOMUX_PADNUM_MASK 0x1ff
237 #define IOMUX_GPIONUM_SHIFT 9
238 #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
240 #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
242 #define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
244 struct chan_param_mem_planar {
282 } __attribute__ ((packed));
284 struct chan_param_mem_interleaved {
341 } __attribute__ ((packed));
343 union chan_param_mem {
344 struct chan_param_mem_planar pp;
345 struct chan_param_mem_interleaved ip;
349 static GraphicDevice panel;
350 static struct ctfb_res_modes *mode;
351 static struct ctfb_res_modes var_mode;
354 * sdc_init_panel() - initialize a synchronous LCD panel.
355 * @width: width of panel in pixels.
356 * @height: height of panel in pixels.
357 * @di_setup: pixel format of the frame buffer
358 * @di_panel: either SHARP or normal TFT
359 * @return: 0 on success or negative error code on failure.
361 static int sdc_init_panel(u16 width, u16 height,
362 enum pixel_fmt di_setup, enum ipu_panel di_panel)
368 debug("%s(width=%d, height=%d)\n", __func__, width, height);
370 /* Init clocking, the IPU receives its clock from the hsp divder */
371 clock = mxc_get_clock(MXC_IPU_CLK);
375 /* Init panel size and blanking periods */
376 reg = width + mode->left_margin + mode->right_margin - 1;
378 printf("mx3fb: Display width too large, coerced to 1023!");
381 reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
382 writel(reg, SDC_HOR_CONF);
384 reg = height + mode->upper_margin + mode->lower_margin - 1;
386 printf("mx3fb: Display height too large, coerced to 1023!");
389 reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
390 writel(reg, SDC_VER_CONF);
393 case IPU_PANEL_SHARP_TFT:
394 writel(0x00FD0102L, SDC_SHARP_CONF_1);
395 writel(0x00F500F4L, SDC_SHARP_CONF_2);
396 writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
397 /* TODO: probably IF_CONF must be adapted (see below)! */
400 writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
407 * Calculate divider: The fractional part is 4 bits so simply
408 * multiple by 2^4 to get it.
410 * Opposed to the kernel driver mode->pixclock is the time of one
411 * pixel in pico seconds, so:
412 * pixel_clk = 1e12 / mode->pixclock
413 * div = ipu_clk * 16 / pixel_clk
415 * div = ipu_clk * 16 / (1e12 / mode->pixclock)
417 * div = ipu_clk * 16 * mode->pixclock / 1e12
419 * To avoid integer overflows this is split into 2 shifts and
420 * one divide with sufficient accuracy:
421 * 16*1024*128*476837 = 0.9999996682e12
423 div = ((clock/1024) * (mode->pixclock/128)) / 476837;
424 debug("hsp_clk is %d, div=%d\n", clock, div);
425 /* coerce to not less than 4.0, not more than 255.9375 */
428 else if (div > 0xFFF)
430 /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
431 * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
432 * based on timing debug DISP3_IF_CLK_UP_WR is 0
434 writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
436 /* DI settings for display 3: clock idle (bit 26) during vsync */
437 old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
438 writel(old_conf | IF_CONF, DI_DISP_IF_CONF);
440 /* only set display 3 polarity bits */
441 old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
442 writel(old_conf | mode->sync, DI_DISP_SIG_POL);
444 writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
445 writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
446 writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
447 writel(readl(DI_DISP_ACC_CC) |
448 ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
450 debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF));
451 debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL));
452 debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF));
453 debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF));
454 debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF));
459 static void ipu_ch_param_set_size(union chan_param_mem *params,
460 uint pixelfmt, uint16_t width,
461 uint16_t height, uint16_t stride)
463 debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
464 __func__, pixelfmt, width, height, stride);
466 params->pp.fw = width - 1;
467 params->pp.fh_l = height - 1;
468 params->pp.fh_h = (height - 1) >> 8;
469 params->pp.sl = stride - 1;
471 /* See above, for further formats see the Linux driver */
473 case GDF_16BIT_565RGB:
477 params->ip.sat = 2; /* SAT = 32-bit access */
478 params->ip.ofs0 = 0; /* Red bit offset */
479 params->ip.ofs1 = 5; /* Green bit offset */
480 params->ip.ofs2 = 11; /* Blue bit offset */
481 params->ip.ofs3 = 16; /* Alpha bit offset */
482 params->ip.wid0 = 4; /* Red bit width - 1 */
483 params->ip.wid1 = 5; /* Green bit width - 1 */
484 params->ip.wid2 = 4; /* Blue bit width - 1 */
486 case GDF_32BIT_X888RGB:
487 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
490 params->ip.sat = 2; /* SAT = 32-bit access */
491 params->ip.ofs0 = 16; /* Red bit offset */
492 params->ip.ofs1 = 8; /* Green bit offset */
493 params->ip.ofs2 = 0; /* Blue bit offset */
494 params->ip.ofs3 = 24; /* Alpha bit offset */
495 params->ip.wid0 = 7; /* Red bit width - 1 */
496 params->ip.wid1 = 7; /* Green bit width - 1 */
497 params->ip.wid2 = 7; /* Blue bit width - 1 */
500 printf("mx3fb: Pixel format not supported!\n");
507 static void ipu_ch_param_set_buffer(union chan_param_mem *params,
508 void *buf0, void *buf1)
510 params->pp.eba0 = (u32)buf0;
511 params->pp.eba1 = (u32)buf1;
514 static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
517 for (; num_words > 0; num_words--) {
518 writel(addr, IPU_IMA_ADDR);
519 writel(*data++, IPU_IMA_DATA);
521 if ((addr & 0x7) == 5) {
522 addr &= ~0x7; /* set to word 0 */
523 addr += 8; /* increment to next row */
528 static uint32_t dma_param_addr(enum ipu_channel channel)
530 /* Channel Parameter Memory */
531 return 0x10000 | (channel << 4);
534 static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
536 union chan_param_mem params = {};
538 uint32_t stride_bytes;
540 stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
542 debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem);
544 /* Build parameter memory data for DMA channel */
545 ipu_ch_param_set_size(¶ms, panel.gdfIndex,
546 panel.plnSizeX, panel.plnSizeY, stride_bytes);
547 ipu_ch_param_set_buffer(¶ms, fbmem, NULL);
549 /* Some channels (rotation) have restriction on burst length */
553 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
554 params.pp.npb = 16 - 1;
560 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10);
562 /* Disable double-buffering */
563 reg = readl(IPU_CHA_DB_MODE_SEL);
564 reg &= ~(1UL << channel);
565 writel(reg, IPU_CHA_DB_MODE_SEL);
568 static void ipu_channel_set_priority(enum ipu_channel channel,
571 u32 reg = readl(IDMAC_CHA_PRI);
574 reg |= 1UL << channel;
576 reg &= ~(1UL << channel);
578 writel(reg, IDMAC_CHA_PRI);
582 * ipu_enable_channel() - enable an IPU channel.
583 * @channel: channel ID.
584 * @return: 0 on success or negative error code on failure.
586 static int ipu_enable_channel(enum ipu_channel channel)
590 /* Reset to buffer 0 */
591 writel(1UL << channel, IPU_CHA_CUR_BUF);
595 ipu_channel_set_priority(channel, 1);
601 reg = readl(IDMAC_CHA_EN);
602 writel(reg | (1UL << channel), IDMAC_CHA_EN);
607 static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
611 reg = readl(IPU_CHA_BUF0_RDY);
612 if (reg & (1UL << channel))
615 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
616 writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
617 writel((u32)buf, IPU_IMA_DATA);
622 static int idmac_tx_submit(enum ipu_channel channel, void *buf)
626 ipu_init_channel_buffer(channel, buf);
629 /* ipu_idmac.c::ipu_submit_channel_buffers() */
630 ret = ipu_update_channel_buffer(channel, buf);
634 /* ipu_idmac.c::ipu_select_buffer() */
635 /* Mark buffer 0 as ready. */
636 writel(1UL << channel, IPU_CHA_BUF0_RDY);
639 ret = ipu_enable_channel(channel);
643 static void sdc_enable_channel(void *fbmem)
648 ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
650 /* mx3fb.c::sdc_fb_init() */
652 reg = readl(SDC_COM_CONF);
653 writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
657 * Attention! Without this msleep the channel keeps generating
658 * interrupts. Next sdc_set_brightness() is going to be called
659 * from mx3fb_blank().
665 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
666 * @return: 0 on success or negative error code on failure.
667 * TODO: currently only 666 and TFT as DI setup supported
669 static int mx3fb_set_par(void)
673 ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
674 IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
678 writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
683 static void ll_disp3_enable(void *base)
687 debug("%s(base=0x%x)\n", __func__, (u32) base);
688 /* pcm037.c::mxc_board_init() */
690 /* Display Interface #3 */
691 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
692 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
693 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
694 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
695 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
696 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
697 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
698 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
699 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
700 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
701 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
702 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
703 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
704 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
705 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
706 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
707 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
708 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
709 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
710 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
711 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
712 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
713 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
714 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
715 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
716 mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
719 /* ipu_idmac.c::ipu_probe() */
721 /* Start the clock */
722 __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
725 /* ipu_idmac.c::ipu_idmac_init() */
727 /* Service request counter to maximum - shouldn't be needed */
728 writel(0x00000070, IDMAC_CONF);
731 /* ipu_idmac.c::ipu_init_channel() */
733 /* Enable IPU sub modules */
734 reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
735 writel(reg, IPU_CONF);
738 /* mx3fb.c::init_fb_chan() */
740 /* set Display Interface clock period */
741 writel(0x00100010L, DI_HSP_CLK_PER);
742 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
745 /* mx3fb.c::sdc_set_brightness() */
747 /* This might be board-specific */
748 writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
751 /* mx3fb.c::sdc_set_global_alpha() */
753 /* Use global - not per-pixel - Alpha-blending */
754 reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL;
755 writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
757 reg = readl(SDC_COM_CONF);
758 writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
761 /* mx3fb.c::sdc_set_color_key() */
763 /* Disable colour-keying for background */
764 reg = readl(SDC_COM_CONF) &
765 ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
766 writel(reg, SDC_COM_CONF);
771 sdc_enable_channel(base);
774 * Linux driver calls sdc_set_brightness() here again,
775 * once is enough for us
777 debug("%s() done\n", __func__);
780 /* ------------------------ public part ------------------- */
781 ulong calc_fbsize(void)
783 return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
787 * The current implementation is only tested for GDF_16BIT_565RGB!
788 * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
789 * because the lcd code seemed loaded with color table stuff, that
790 * does not relate to most modern TFTs. cfb_console.c looks more
792 * This is the environment setting for the original setup
793 * "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
794 * up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
795 * "videomode=unknown"
797 * Settings for VBEST VGG322403 display:
798 * "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000,
799 * "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0"
801 * Settings for COM57H5M10XRC display:
802 * "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,
803 * "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0"
805 void *video_hw_init(void)
809 unsigned long t1, hsynch, vsynch;
810 int bits_per_pixel, i, tmp, videomode;
816 videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
817 /* get video mode via environment */
818 penv = env_get("videomode");
820 /* decide if it is a string */
821 if (penv[0] <= '9') {
822 videomode = (int) simple_strtoul(penv, NULL, 16);
829 /* parameter are vesa modes */
831 for (i = 0; i < VESA_MODES_COUNT; i++) {
832 if (vesa_modes[i].vesanr == videomode)
835 if (i == VESA_MODES_COUNT) {
836 printf("No VESA Mode found, switching to mode 0x%x ",
837 CONFIG_SYS_DEFAULT_VIDEO_MODE);
840 mode = (struct ctfb_res_modes *)
841 &res_mode_init[vesa_modes[i].resindex];
842 bits_per_pixel = vesa_modes[i].bits_per_pixel;
844 mode = (struct ctfb_res_modes *) &var_mode;
845 bits_per_pixel = video_get_params(mode, penv);
848 /* calculate hsynch and vsynch freq (info only) */
849 t1 = (mode->left_margin + mode->xres +
850 mode->right_margin + mode->hsync_len) / 8;
852 t1 *= mode->pixclock;
854 hsynch = 1000000000L / t1;
855 t1 *= (mode->upper_margin + mode->yres +
856 mode->lower_margin + mode->vsync_len);
858 vsynch = 1000000000L / t1;
860 /* fill in Graphic device struct */
861 sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
862 mode->xres, mode->yres,
863 bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
864 printf("%s\n", panel.modeIdent);
865 panel.winSizeX = mode->xres;
866 panel.winSizeY = mode->yres;
867 panel.plnSizeX = mode->xres;
868 panel.plnSizeY = mode->yres;
870 switch (bits_per_pixel) {
872 panel.gdfBytesPP = 4;
873 panel.gdfIndex = GDF_32BIT_X888RGB;
876 panel.gdfBytesPP = 2;
877 panel.gdfIndex = GDF_16BIT_565RGB;
880 panel.gdfBytesPP = 1;
881 panel.gdfIndex = GDF__8BIT_INDEX;
885 /* set up Hardware */
886 memsize = calc_fbsize();
888 debug("%s() allocating %d bytes\n", __func__, memsize);
890 /* fill in missing Graphic device struct */
891 panel.frameAdrs = (u32) malloc(memsize);
892 if (panel.frameAdrs == 0) {
893 printf("%s() malloc(%d) failed\n", __func__, memsize);
896 panel.memSize = memsize;
898 ll_disp3_enable((void *) panel.frameAdrs);
899 memset((void *) panel.frameAdrs, 0, memsize);
901 debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
902 __func__, panel.frameAdrs, memsize);
904 return (void *) &panel;