drivers/video/meson/meson_vclk.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Amlogic Meson Video Processing Unit driver
   4  *
   5  * Copyright (c) 2018 BayLibre, SAS.
   6  * Author: Neil Armstrong <narmstrong@baylibre.com>
   7  */
   8
   9 #include <edid.h>
  10 #include "meson_vpu.h"
  11 #include <linux/iopoll.h>
  12 #include <linux/math64.h>
  13
  14 #define writel_bits(mask, val, addr) \
  15         writel((readl(addr) & ~(mask)) | (val), addr)
  16
  17 enum {
  18         MESON_VCLK_TARGET_CVBS = 0,
  19         MESON_VCLK_TARGET_HDMI = 1,
  20         MESON_VCLK_TARGET_DMT = 2,
  21 };
  22
  23 /* HHI Registers */
  24 #define HHI_VID_PLL_CLK_DIV     0x1a0 /* 0x68 offset in data sheet */
  25 #define VID_PLL_EN              BIT(19)
  26 #define VID_PLL_BYPASS          BIT(18)
  27 #define VID_PLL_PRESET          BIT(15)
  28 #define HHI_VIID_CLK_DIV        0x128 /* 0x4a offset in data sheet */
  29 #define VCLK2_DIV_MASK          0xff
  30 #define VCLK2_DIV_EN            BIT(16)
  31 #define VCLK2_DIV_RESET         BIT(17)
  32 #define CTS_VDAC_SEL_MASK       (0xf << 28)
  33 #define CTS_VDAC_SEL_SHIFT      28
  34 #define HHI_VIID_CLK_CNTL       0x12c /* 0x4b offset in data sheet */
  35 #define VCLK2_EN                BIT(19)
  36 #define VCLK2_SEL_MASK          (0x7 << 16)
  37 #define VCLK2_SEL_SHIFT         16
  38 #define VCLK2_SOFT_RESET        BIT(15)
  39 #define VCLK2_DIV1_EN           BIT(0)
  40 #define HHI_VID_CLK_DIV         0x164 /* 0x59 offset in data sheet */
  41 #define VCLK_DIV_MASK           0xff
  42 #define VCLK_DIV_EN             BIT(16)
  43 #define VCLK_DIV_RESET          BIT(17)
  44 #define CTS_ENCP_SEL_MASK       (0xf << 24)
  45 #define CTS_ENCP_SEL_SHIFT      24
  46 #define CTS_ENCI_SEL_MASK       (0xf << 28)
  47 #define CTS_ENCI_SEL_SHIFT      28
  48 #define HHI_VID_CLK_CNTL        0x17c /* 0x5f offset in data sheet */
  49 #define VCLK_EN                 BIT(19)
  50 #define VCLK_SEL_MASK           (0x7 << 16)
  51 #define VCLK_SEL_SHIFT          16
  52 #define VCLK_SOFT_RESET         BIT(15)
  53 #define VCLK_DIV1_EN            BIT(0)
  54 #define VCLK_DIV2_EN            BIT(1)
  55 #define VCLK_DIV4_EN            BIT(2)
  56 #define VCLK_DIV6_EN            BIT(3)
  57 #define VCLK_DIV12_EN           BIT(4)
  58 #define HHI_VID_CLK_CNTL2       0x194 /* 0x65 offset in data sheet */
  59 #define CTS_ENCI_EN             BIT(0)
  60 #define CTS_ENCP_EN             BIT(2)
  61 #define CTS_VDAC_EN             BIT(4)
  62 #define HDMI_TX_PIXEL_EN        BIT(5)
  63 #define HHI_HDMI_CLK_CNTL       0x1cc /* 0x73 offset in data sheet */
  64 #define HDMI_TX_PIXEL_SEL_MASK  (0xf << 16)
  65 #define HDMI_TX_PIXEL_SEL_SHIFT 16
  66 #define CTS_HDMI_SYS_SEL_MASK   (0x7 << 9)
  67 #define CTS_HDMI_SYS_DIV_MASK   (0x7f)
  68 #define CTS_HDMI_SYS_EN         BIT(8)
  69
  70 #define HHI_HDMI_PLL_CNTL       0x320 /* 0xc8 offset in data sheet */
  71 #define HHI_HDMI_PLL_CNTL_EN    BIT(30)
  72 #define HHI_HDMI_PLL_CNTL2      0x324 /* 0xc9 offset in data sheet */
  73 #define HHI_HDMI_PLL_CNTL3      0x328 /* 0xca offset in data sheet */
  74 #define HHI_HDMI_PLL_CNTL4      0x32C /* 0xcb offset in data sheet */
  75 #define HHI_HDMI_PLL_CNTL5      0x330 /* 0xcc offset in data sheet */
  76 #define HHI_HDMI_PLL_CNTL6      0x334 /* 0xcd offset in data sheet */
  77 #define HHI_HDMI_PLL_CNTL7      0x338 /* 0xce offset in data sheet */
  78
  79 #define HDMI_PLL_RESET          BIT(28)
  80 #define HDMI_PLL_RESET_G12A     BIT(29)
  81 #define HDMI_PLL_LOCK           BIT(31)
  82 #define HDMI_PLL_LOCK_G12A      (3 << 30)
  83
  84 #define FREQ_1000_1001(_freq)   DIV_ROUND_CLOSEST(_freq * 1000, 1001)
  85
  86 /* VID PLL Dividers */
  87 enum {
  88         VID_PLL_DIV_1 = 0,
  89         VID_PLL_DIV_2,
  90         VID_PLL_DIV_2p5,
  91         VID_PLL_DIV_3,
  92         VID_PLL_DIV_3p5,
  93         VID_PLL_DIV_3p75,
  94         VID_PLL_DIV_4,
  95         VID_PLL_DIV_5,
  96         VID_PLL_DIV_6,
  97         VID_PLL_DIV_6p25,
  98         VID_PLL_DIV_7,
  99         VID_PLL_DIV_7p5,
 100         VID_PLL_DIV_12,
 101         VID_PLL_DIV_14,
 102         VID_PLL_DIV_15,
 103 };
 104
 105 void meson_vid_pll_set(struct meson_vpu_priv *priv, unsigned int div)
 106 {
 107         unsigned int shift_val = 0;
 108         unsigned int shift_sel = 0;
 109
 110         /* Disable vid_pll output clock */
 111         hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
 112         hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
 113
 114         switch (div) {
 115         case VID_PLL_DIV_2:
 116                 shift_val = 0x0aaa;
 117                 shift_sel = 0;
 118                 break;
 119         case VID_PLL_DIV_2p5:
 120                 shift_val = 0x5294;
 121                 shift_sel = 2;
 122                 break;
 123         case VID_PLL_DIV_3:
 124                 shift_val = 0x0db6;
 125                 shift_sel = 0;
 126                 break;
 127         case VID_PLL_DIV_3p5:
 128                 shift_val = 0x36cc;
 129                 shift_sel = 1;
 130                 break;
 131         case VID_PLL_DIV_3p75:
 132                 shift_val = 0x6666;
 133                 shift_sel = 2;
 134                 break;
 135         case VID_PLL_DIV_4:
 136                 shift_val = 0x0ccc;
 137                 shift_sel = 0;
 138                 break;
 139         case VID_PLL_DIV_5:
 140                 shift_val = 0x739c;
 141                 shift_sel = 2;
 142                 break;
 143         case VID_PLL_DIV_6:
 144                 shift_val = 0x0e38;
 145                 shift_sel = 0;
 146                 break;
 147         case VID_PLL_DIV_6p25:
 148                 shift_val = 0x0000;
 149                 shift_sel = 3;
 150                 break;
 151         case VID_PLL_DIV_7:
 152                 shift_val = 0x3c78;
 153                 shift_sel = 1;
 154                 break;
 155         case VID_PLL_DIV_7p5:
 156                 shift_val = 0x78f0;
 157                 shift_sel = 2;
 158                 break;
 159         case VID_PLL_DIV_12:
 160                 shift_val = 0x0fc0;
 161                 shift_sel = 0;
 162                 break;
 163         case VID_PLL_DIV_14:
 164                 shift_val = 0x3f80;
 165                 shift_sel = 1;
 166                 break;
 167         case VID_PLL_DIV_15:
 168                 shift_val = 0x7f80;
 169                 shift_sel = 2;
 170                 break;
 171         }
 172
 173         if (div == VID_PLL_DIV_1) {
 174                 /* Enable vid_pll bypass to HDMI pll */
 175                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 176                                 VID_PLL_BYPASS, VID_PLL_BYPASS);
 177         } else {
 178                 /* Disable Bypass */
 179                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 180                                 VID_PLL_BYPASS, 0);
 181                 /* Clear sel */
 182                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 183                                 3 << 16, 0);
 184                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 185                                 VID_PLL_PRESET, 0);
 186                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 187                                 0x7fff, 0);
 188
 189                 /* Setup sel and val */
 190                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 191                                 3 << 16, shift_sel << 16);
 192                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 193                                 VID_PLL_PRESET, VID_PLL_PRESET);
 194                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 195                                 0x7fff, shift_val);
 196
 197                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 198                                 VID_PLL_PRESET, 0);
 199         }
 200
 201         /* Enable the vid_pll output clock */
 202         hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 203                         VID_PLL_EN, VID_PLL_EN);
 204 }
 205
 206 /*
 207  * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
 208  *
 209  * TOFIX: Refactor into table to also handle HDMI frequency and paths
 210  */
 211 static void meson_venci_cvbs_clock_config(struct meson_vpu_priv *priv)
 212 {
 213         unsigned int val;
 214
 215         /* Setup PLL to output 1.485GHz */
 216         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 217                 hhi_write(HHI_HDMI_PLL_CNTL, 0x5800023d);
 218                 hhi_write(HHI_HDMI_PLL_CNTL2, 0x00404e00);
 219                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 220                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x801da72c);
 221                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x71486980);
 222                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x00000e55);
 223                 hhi_write(HHI_HDMI_PLL_CNTL, 0x4800023d);
 224
 225                 /* Poll for lock bit */
 226                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 227                                    (val & HDMI_PLL_LOCK), 10);
 228         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 229                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 230                 hhi_write(HHI_HDMI_PLL_CNTL, 0x4000027b);
 231                 hhi_write(HHI_HDMI_PLL_CNTL2, 0x800cb300);
 232                 hhi_write(HHI_HDMI_PLL_CNTL3, 0xa6212844);
 233                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
 234                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x001fa729);
 235                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x01a31500);
 236
 237                 /* Reset PLL */
 238                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 239                                 HDMI_PLL_RESET, HDMI_PLL_RESET);
 240                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 241                                 HDMI_PLL_RESET, 0);
 242
 243                 /* Poll for lock bit */
 244                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 245                                    (val & HDMI_PLL_LOCK), 10);
 246         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 247                 hhi_write(HHI_HDMI_PLL_CNTL, 0x1a0504f7);
 248                 hhi_write(HHI_HDMI_PLL_CNTL2, 0x00010000);
 249                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x00000000);
 250                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
 251                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x65771290);
 252                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x39272000);
 253                 hhi_write(HHI_HDMI_PLL_CNTL7, 0x56540000);
 254                 hhi_write(HHI_HDMI_PLL_CNTL, 0x3a0504f7);
 255                 hhi_write(HHI_HDMI_PLL_CNTL, 0x1a0504f7);
 256
 257                 /* Poll for lock bit */
 258                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 259                         ((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
 260                         10);
 261         }
 262
 263         /* Disable VCLK2 */
 264         hhi_update_bits(HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
 265
 266         /* Setup vid_pll to /1 */
 267         meson_vid_pll_set(priv, VID_PLL_DIV_1);
 268
 269         /* Setup the VCLK2 divider value to achieve 27MHz */
 270         hhi_update_bits(HHI_VIID_CLK_DIV,
 271                         VCLK2_DIV_MASK, (55 - 1));
 272
 273         /* select vid_pll for vclk2 */
 274         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 275                 hhi_update_bits(HHI_VIID_CLK_CNTL,
 276                                 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
 277         else
 278                 hhi_update_bits(HHI_VIID_CLK_CNTL,
 279                                 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
 280
 281         /* enable vclk2 gate */
 282         hhi_update_bits(HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
 283
 284         /* select vclk_div1 for enci */
 285         hhi_update_bits(HHI_VID_CLK_DIV,
 286                         CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
 287         /* select vclk_div1 for vdac */
 288         hhi_update_bits(HHI_VIID_CLK_DIV,
 289                         CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
 290
 291         /* release vclk2_div_reset and enable vclk2_div */
 292         hhi_update_bits(HHI_VIID_CLK_DIV,
 293                         VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
 294
 295         /* enable vclk2_div1 gate */
 296         hhi_update_bits(HHI_VIID_CLK_CNTL,
 297                         VCLK2_DIV1_EN, VCLK2_DIV1_EN);
 298
 299         /* reset vclk2 */
 300         hhi_update_bits(HHI_VIID_CLK_CNTL,
 301                         VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
 302         hhi_update_bits(HHI_VIID_CLK_CNTL,
 303                         VCLK2_SOFT_RESET, 0);
 304
 305         /* enable enci_clk */
 306         hhi_update_bits(HHI_VID_CLK_CNTL2,
 307                         CTS_ENCI_EN, CTS_ENCI_EN);
 308         /* enable vdac_clk */
 309         hhi_update_bits(HHI_VID_CLK_CNTL2,
 310                         CTS_VDAC_EN, CTS_VDAC_EN);
 311 }
 312
 313 enum {
 314 /* PLL  O1 O2 O3 VP DV     EN TX */
 315 /* 4320 /4 /4 /1 /5 /1  => /2 /2 */
 316         MESON_VCLK_HDMI_ENCI_54000 = 0,
 317 /* 4320 /4 /4 /1 /5 /1  => /1 /2 */
 318         MESON_VCLK_HDMI_DDR_54000,
 319 /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
 320         MESON_VCLK_HDMI_DDR_148500,
 321 /* 2970 /2 /2 /2 /5 /1  => /1 /1 */
 322         MESON_VCLK_HDMI_74250,
 323 /* 2970 /1 /2 /2 /5 /1  => /1 /1 */
 324         MESON_VCLK_HDMI_148500,
 325 /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
 326         MESON_VCLK_HDMI_297000,
 327 /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
 328         MESON_VCLK_HDMI_594000
 329 };
 330
 331 struct meson_vclk_params {
 332         unsigned int pixel_freq;
 333         unsigned int pll_base_freq;
 334         unsigned int pll_od1;
 335         unsigned int pll_od2;
 336         unsigned int pll_od3;
 337         unsigned int vid_pll_div;
 338         unsigned int vclk_div;
 339 } params[] = {
 340         [MESON_VCLK_HDMI_ENCI_54000] = {
 341                 .pixel_freq = 54000,
 342                 .pll_base_freq = 4320000,
 343                 .pll_od1 = 4,
 344                 .pll_od2 = 4,
 345                 .pll_od3 = 1,
 346                 .vid_pll_div = VID_PLL_DIV_5,
 347                 .vclk_div = 1,
 348         },
 349         [MESON_VCLK_HDMI_DDR_54000] = {
 350                 .pixel_freq = 54000,
 351                 .pll_base_freq = 4320000,
 352                 .pll_od1 = 4,
 353                 .pll_od2 = 4,
 354                 .pll_od3 = 1,
 355                 .vid_pll_div = VID_PLL_DIV_5,
 356                 .vclk_div = 1,
 357         },
 358         [MESON_VCLK_HDMI_DDR_148500] = {
 359                 .pixel_freq = 148500,
 360                 .pll_base_freq = 2970000,
 361                 .pll_od1 = 4,
 362                 .pll_od2 = 1,
 363                 .pll_od3 = 1,
 364                 .vid_pll_div = VID_PLL_DIV_5,
 365                 .vclk_div = 1,
 366         },
 367         [MESON_VCLK_HDMI_74250] = {
 368                 .pixel_freq = 74250,
 369                 .pll_base_freq = 2970000,
 370                 .pll_od1 = 2,
 371                 .pll_od2 = 2,
 372                 .pll_od3 = 2,
 373                 .vid_pll_div = VID_PLL_DIV_5,
 374                 .vclk_div = 1,
 375         },
 376         [MESON_VCLK_HDMI_148500] = {
 377                 .pixel_freq = 148500,
 378                 .pll_base_freq = 2970000,
 379                 .pll_od1 = 1,
 380                 .pll_od2 = 2,
 381                 .pll_od3 = 2,
 382                 .vid_pll_div = VID_PLL_DIV_5,
 383                 .vclk_div = 1,
 384         },
 385         [MESON_VCLK_HDMI_297000] = {
 386                 .pixel_freq = 297000,
 387                 .pll_base_freq = 5940000,
 388                 .pll_od1 = 2,
 389                 .pll_od2 = 1,
 390                 .pll_od3 = 1,
 391                 .vid_pll_div = VID_PLL_DIV_5,
 392                 .vclk_div = 2,
 393         },
 394         [MESON_VCLK_HDMI_594000] = {
 395                 .pixel_freq = 594000,
 396                 .pll_base_freq = 5940000,
 397                 .pll_od1 = 1,
 398                 .pll_od2 = 1,
 399                 .pll_od3 = 2,
 400                 .vid_pll_div = VID_PLL_DIV_5,
 401                 .vclk_div = 1,
 402         },
 403         { /* sentinel */ },
 404 };
 405
 406 static inline unsigned int pll_od_to_reg(unsigned int od)
 407 {
 408         switch (od) {
 409         case 1:
 410                 return 0;
 411         case 2:
 412                 return 1;
 413         case 4:
 414                 return 2;
 415         case 8:
 416                 return 3;
 417         }
 418
 419         /* Invalid */
 420         return 0;
 421 }
 422
 423 void meson_hdmi_pll_set_params(struct meson_vpu_priv *priv, unsigned int m,
 424                                unsigned int frac, unsigned int od1,
 425                                unsigned int od2, unsigned int od3)
 426 {
 427         unsigned int val;
 428
 429         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 430                 hhi_write(HHI_HDMI_PLL_CNTL, 0x58000200 | m);
 431                 if (frac)
 432                         hhi_write(HHI_HDMI_PLL_CNTL2,
 433                                   0x00004000 | frac);
 434                 else
 435                         hhi_write(HHI_HDMI_PLL_CNTL2,
 436                                   0x00000000);
 437                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 438                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x801da72c);
 439                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x71486980);
 440                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x00000e55);
 441
 442                 /* Enable and unreset */
 443                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 444                                 0x7 << 28, 0x4 << 28);
 445
 446                 /* Poll for lock bit */
 447                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 448                                    (val & HDMI_PLL_LOCK), 10);
 449         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 450                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 451                 hhi_write(HHI_HDMI_PLL_CNTL, 0x40000200 | m);
 452                 hhi_write(HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
 453                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 454                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 455                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x001fa729);
 456                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x01a31500);
 457
 458                 /* Reset PLL */
 459                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 460                                 HDMI_PLL_RESET, HDMI_PLL_RESET);
 461                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 462                                 HDMI_PLL_RESET, 0);
 463
 464                 /* Poll for lock bit */
 465                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 466                                    (val & HDMI_PLL_LOCK), 10);
 467         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 468                 hhi_write(HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
 469
 470                 /* Enable and reset */
 471                 hhi_update_bits(HHI_HDMI_PLL_CNTL, 0x3 << 28, 0x3 << 28);
 472
 473                 hhi_write(HHI_HDMI_PLL_CNTL2, frac);
 474                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x00000000);
 475
 476                 /* G12A HDMI PLL Needs specific parameters for 5.4GHz */
 477                 if (m >= 0xf7) {
 478                         if (frac < 0x10000) {
 479                                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x6a685c00);
 480                                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x11551293);
 481                         } else {
 482                                 hhi_write(HHI_HDMI_PLL_CNTL4, 0xea68dc00);
 483                                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x65771290);
 484                         }
 485                         hhi_write(HHI_HDMI_PLL_CNTL6, 0x39272000);
 486                         hhi_write(HHI_HDMI_PLL_CNTL7, 0x55540000);
 487                 } else {
 488                         hhi_write(HHI_HDMI_PLL_CNTL4, 0x0a691c00);
 489                         hhi_write(HHI_HDMI_PLL_CNTL5, 0x33771290);
 490                         hhi_write(HHI_HDMI_PLL_CNTL6, 0x39270000);
 491                         hhi_write(HHI_HDMI_PLL_CNTL7, 0x50540000);
 492                 }
 493
 494                 do {
 495                         /* Reset PLL */
 496                         hhi_update_bits(HHI_HDMI_PLL_CNTL,
 497                                         HDMI_PLL_RESET_G12A,
 498                                         HDMI_PLL_RESET_G12A);
 499
 500                         /* UN-Reset PLL */
 501                         hhi_update_bits(HHI_HDMI_PLL_CNTL,
 502                                         HDMI_PLL_RESET_G12A, 0);
 503
 504                         /* Poll for lock bits */
 505                         if (!readl_poll_timeout(
 506                                         priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 507                                         ((val & HDMI_PLL_LOCK_G12A)
 508                                                 == HDMI_PLL_LOCK_G12A), 100))
 509                                 break;
 510                 } while (1);
 511         }
 512
 513         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 514                 hhi_update_bits(HHI_HDMI_PLL_CNTL2,
 515                                 3 << 16, pll_od_to_reg(od1) << 16);
 516         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 517                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 518                 hhi_update_bits(HHI_HDMI_PLL_CNTL3,
 519                                 3 << 21, pll_od_to_reg(od1) << 21);
 520         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 521                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 522                                 3 << 16, pll_od_to_reg(od1) << 16);
 523
 524         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 525                 hhi_update_bits(HHI_HDMI_PLL_CNTL2,
 526                                 3 << 22, pll_od_to_reg(od2) << 22);
 527         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 528                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 529                 hhi_update_bits(HHI_HDMI_PLL_CNTL3,
 530                                 3 << 23, pll_od_to_reg(od2) << 23);
 531         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 532                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 533                                 3 << 18, pll_od_to_reg(od2) << 18);
 534
 535         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 536                 hhi_update_bits(HHI_HDMI_PLL_CNTL2,
 537                                 3 << 18, pll_od_to_reg(od3) << 18);
 538         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 539                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 540                 hhi_update_bits(HHI_HDMI_PLL_CNTL3,
 541                                 3 << 19, pll_od_to_reg(od3) << 19);
 542         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 543                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 544                                 3 << 20, pll_od_to_reg(od3) << 20);
 545 }
 546
 547 #define XTAL_FREQ 24000
 548
 549 static unsigned int meson_hdmi_pll_get_m(struct meson_vpu_priv *priv,
 550                                          unsigned int pll_freq)
 551 {
 552         /* The GXBB PLL has a /2 pre-multiplier */
 553         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 554                 pll_freq /= 2;
 555
 556         return pll_freq / XTAL_FREQ;
 557 }
 558
 559 #define HDMI_FRAC_MAX_GXBB      4096
 560 #define HDMI_FRAC_MAX_GXL       1024
 561 #define HDMI_FRAC_MAX_G12A      131072
 562
 563 static unsigned int meson_hdmi_pll_get_frac(struct meson_vpu_priv *priv,
 564                                             unsigned int m,
 565                                             unsigned int pll_freq)
 566 {
 567         unsigned int parent_freq = XTAL_FREQ;
 568         unsigned int frac_max = HDMI_FRAC_MAX_GXL;
 569         unsigned int frac_m;
 570         unsigned int frac;
 571
 572         /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
 573         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 574                 frac_max = HDMI_FRAC_MAX_GXBB;
 575                 parent_freq *= 2;
 576         }
 577
 578         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 579                 frac_max = HDMI_FRAC_MAX_G12A;
 580
 581         /* We can have a perfect match !*/
 582         if (pll_freq / m == parent_freq &&
 583             pll_freq % m == 0)
 584                 return 0;
 585
 586         frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq);
 587         frac_m = m * frac_max;
 588         if (frac_m > frac)
 589                 return frac_max;
 590         frac -= frac_m;
 591
 592         return min((u16)frac, (u16)(frac_max - 1));
 593 }
 594
 595 static bool meson_hdmi_pll_validate_params(struct meson_vpu_priv *priv,
 596                                            unsigned int m,
 597                                            unsigned int frac)
 598 {
 599         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 600                 /* Empiric supported min/max dividers */
 601                 if (m < 53 || m > 123)
 602                         return false;
 603                 if (frac >= HDMI_FRAC_MAX_GXBB)
 604                         return false;
 605         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 606                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 607                 /* Empiric supported min/max dividers */
 608                 if (m < 106 || m > 247)
 609                         return false;
 610                 if (frac >= HDMI_FRAC_MAX_GXL)
 611                         return false;
 612         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 613                 /* Empiric supported min/max dividers */
 614                 if (m < 106 || m > 247)
 615                         return false;
 616                 if (frac >= HDMI_FRAC_MAX_G12A)
 617                         return false;
 618         }
 619
 620         return true;
 621 }
 622
 623 static bool meson_hdmi_pll_find_params(struct meson_vpu_priv *priv,
 624                                        unsigned int freq,
 625                                        unsigned int *m,
 626                                        unsigned int *frac,
 627                                        unsigned int *od)
 628 {
 629         /* Cycle from /16 to /2 */
 630         for (*od = 16 ; *od > 1 ; *od >>= 1) {
 631                 *m = meson_hdmi_pll_get_m(priv, freq * *od);
 632                 if (!*m)
 633                         continue;
 634                 *frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
 635
 636                 debug("PLL params for %dkHz: m=%x frac=%x od=%d\n",
 637                       freq, *m, *frac, *od);
 638
 639                 if (meson_hdmi_pll_validate_params(priv, *m, *frac))
 640                         return true;
 641         }
 642
 643         return false;
 644 }
 645
 646 /* pll_freq is the frequency after the OD dividers */
 647 bool meson_vclk_dmt_supported_freq(struct meson_vpu_priv *priv,
 648                                    unsigned int freq)
 649 {
 650         unsigned int od, m, frac;
 651
 652         /* In DMT mode, path after PLL is always /10 */
 653         freq *= 10;
 654
 655         if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
 656                 return true;
 657
 658         return false;
 659 }
 660
 661 /* pll_freq is the frequency after the OD dividers */
 662 static void meson_hdmi_pll_generic_set(struct meson_vpu_priv *priv,
 663                                        unsigned int pll_freq)
 664 {
 665         unsigned int od, m, frac, od1, od2, od3;
 666
 667         if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
 668                 od3 = 1;
 669                 if (od < 4) {
 670                         od1 = 2;
 671                         od2 = 1;
 672                 } else {
 673                         od2 = od / 4;
 674                         od1 = od / od2;
 675                 }
 676
 677                 debug("PLL params for %dkHz: m=%x frac=%x od=%d/%d/%d\n",
 678                       pll_freq, m, frac, od1, od2, od3);
 679
 680                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 681
 682                 return;
 683         }
 684
 685         printf("Fatal, unable to find parameters for PLL freq %d\n",
 686                pll_freq);
 687 }
 688
 689 static void
 690 meson_vclk_set(struct meson_vpu_priv *priv, unsigned int pll_base_freq,
 691                unsigned int od1, unsigned int od2, unsigned int od3,
 692                unsigned int vid_pll_div, unsigned int vclk_div,
 693                unsigned int hdmi_tx_div, unsigned int venc_div,
 694                bool hdmi_use_enci, bool vic_alternate_clock)
 695 {
 696         unsigned int m = 0, frac = 0;
 697
 698         /* Set HDMI-TX sys clock */
 699         hhi_update_bits(HHI_HDMI_CLK_CNTL,
 700                         CTS_HDMI_SYS_SEL_MASK, 0);
 701         hhi_update_bits(HHI_HDMI_CLK_CNTL,
 702                         CTS_HDMI_SYS_DIV_MASK, 0);
 703         hhi_update_bits(HHI_HDMI_CLK_CNTL,
 704                         CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
 705
 706         /* Set HDMI PLL rate */
 707         if (!od1 && !od2 && !od3) {
 708                 meson_hdmi_pll_generic_set(priv, pll_base_freq);
 709         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 710                 switch (pll_base_freq) {
 711                 case 2970000:
 712                         m = 0x3d;
 713                         frac = vic_alternate_clock ? 0xd02 : 0xe00;
 714                         break;
 715                 case 4320000:
 716                         m = vic_alternate_clock ? 0x59 : 0x5a;
 717                         frac = vic_alternate_clock ? 0xe8f : 0;
 718                         break;
 719                 case 5940000:
 720                         m = 0x7b;
 721                         frac = vic_alternate_clock ? 0xa05 : 0xc00;
 722                         break;
 723                 }
 724
 725                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 726         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 727                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 728                 switch (pll_base_freq) {
 729                 case 2970000:
 730                         m = 0x7b;
 731                         frac = vic_alternate_clock ? 0x281 : 0x300;
 732                         break;
 733                 case 4320000:
 734                         m = vic_alternate_clock ? 0xb3 : 0xb4;
 735                         frac = vic_alternate_clock ? 0x347 : 0;
 736                         break;
 737                 case 5940000:
 738                         m = 0xf7;
 739                         frac = vic_alternate_clock ? 0x102 : 0x200;
 740                         break;
 741                 }
 742
 743                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 744         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 745                 switch (pll_base_freq) {
 746                 case 2970000:
 747                         m = 0x7b;
 748                         frac = vic_alternate_clock ? 0x140b4 : 0x18000;
 749                         break;
 750                 case 4320000:
 751                         m = vic_alternate_clock ? 0xb3 : 0xb4;
 752                         frac = vic_alternate_clock ? 0x1a3ee : 0;
 753                         break;
 754                 case 5940000:
 755                         m = 0xf7;
 756                         frac = vic_alternate_clock ? 0x8148 : 0x10000;
 757                         break;
 758                 }
 759
 760                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 761         }
 762
 763         /* Setup vid_pll divider */
 764         meson_vid_pll_set(priv, vid_pll_div);
 765
 766         /* Set VCLK div */
 767         hhi_update_bits(HHI_VID_CLK_CNTL,
 768                         VCLK_SEL_MASK, 0);
 769         hhi_update_bits(HHI_VID_CLK_DIV,
 770                         VCLK_DIV_MASK, vclk_div - 1);
 771
 772         /* Set HDMI-TX source */
 773         switch (hdmi_tx_div) {
 774         case 1:
 775                 /* enable vclk_div1 gate */
 776                 hhi_update_bits(HHI_VID_CLK_CNTL,
 777                                 VCLK_DIV1_EN, VCLK_DIV1_EN);
 778
 779                 /* select vclk_div1 for HDMI-TX */
 780                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 781                                 HDMI_TX_PIXEL_SEL_MASK, 0);
 782                 break;
 783         case 2:
 784                 /* enable vclk_div2 gate */
 785                 hhi_update_bits(HHI_VID_CLK_CNTL,
 786                                 VCLK_DIV2_EN, VCLK_DIV2_EN);
 787
 788                 /* select vclk_div2 for HDMI-TX */
 789                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 790                                 HDMI_TX_PIXEL_SEL_MASK,
 791                                 1 << HDMI_TX_PIXEL_SEL_SHIFT);
 792                 break;
 793         case 4:
 794                 /* enable vclk_div4 gate */
 795                 hhi_update_bits(HHI_VID_CLK_CNTL,
 796                                 VCLK_DIV4_EN, VCLK_DIV4_EN);
 797
 798                 /* select vclk_div4 for HDMI-TX */
 799                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 800                                 HDMI_TX_PIXEL_SEL_MASK,
 801                                 2 << HDMI_TX_PIXEL_SEL_SHIFT);
 802                 break;
 803         case 6:
 804                 /* enable vclk_div6 gate */
 805                 hhi_update_bits(HHI_VID_CLK_CNTL,
 806                                 VCLK_DIV6_EN, VCLK_DIV6_EN);
 807
 808                 /* select vclk_div6 for HDMI-TX */
 809                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 810                                 HDMI_TX_PIXEL_SEL_MASK,
 811                                 3 << HDMI_TX_PIXEL_SEL_SHIFT);
 812                 break;
 813         case 12:
 814                 /* enable vclk_div12 gate */
 815                 hhi_update_bits(HHI_VID_CLK_CNTL,
 816                                 VCLK_DIV12_EN, VCLK_DIV12_EN);
 817
 818                 /* select vclk_div12 for HDMI-TX */
 819                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 820                                 HDMI_TX_PIXEL_SEL_MASK,
 821                                 4 << HDMI_TX_PIXEL_SEL_SHIFT);
 822                 break;
 823         }
 824         hhi_update_bits(HHI_VID_CLK_CNTL2,
 825                         HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
 826
 827         /* Set ENCI/ENCP Source */
 828         switch (venc_div) {
 829         case 1:
 830                 /* enable vclk_div1 gate */
 831                 hhi_update_bits(HHI_VID_CLK_CNTL,
 832                                 VCLK_DIV1_EN, VCLK_DIV1_EN);
 833
 834                 if (hdmi_use_enci)
 835                         /* select vclk_div1 for enci */
 836                         hhi_update_bits(HHI_VID_CLK_DIV,
 837                                         CTS_ENCI_SEL_MASK, 0);
 838                 else
 839                         /* select vclk_div1 for encp */
 840                         hhi_update_bits(HHI_VID_CLK_DIV,
 841                                         CTS_ENCP_SEL_MASK, 0);
 842                 break;
 843         case 2:
 844                 /* enable vclk_div2 gate */
 845                 hhi_update_bits(HHI_VID_CLK_CNTL,
 846                                 VCLK_DIV2_EN, VCLK_DIV2_EN);
 847
 848                 if (hdmi_use_enci)
 849                         /* select vclk_div2 for enci */
 850                         hhi_update_bits(HHI_VID_CLK_DIV,
 851                                         CTS_ENCI_SEL_MASK,
 852                                         1 << CTS_ENCI_SEL_SHIFT);
 853                 else
 854                         /* select vclk_div2 for encp */
 855                         hhi_update_bits(HHI_VID_CLK_DIV,
 856                                         CTS_ENCP_SEL_MASK,
 857                                         1 << CTS_ENCP_SEL_SHIFT);
 858                 break;
 859         case 4:
 860                 /* enable vclk_div4 gate */
 861                 hhi_update_bits(HHI_VID_CLK_CNTL,
 862                                 VCLK_DIV4_EN, VCLK_DIV4_EN);
 863
 864                 if (hdmi_use_enci)
 865                         /* select vclk_div4 for enci */
 866                         hhi_update_bits(HHI_VID_CLK_DIV,
 867                                         CTS_ENCI_SEL_MASK,
 868                                         2 << CTS_ENCI_SEL_SHIFT);
 869                 else
 870                         /* select vclk_div4 for encp */
 871                         hhi_update_bits(HHI_VID_CLK_DIV,
 872                                         CTS_ENCP_SEL_MASK,
 873                                         2 << CTS_ENCP_SEL_SHIFT);
 874                 break;
 875         case 6:
 876                 /* enable vclk_div6 gate */
 877                 hhi_update_bits(HHI_VID_CLK_CNTL,
 878                                 VCLK_DIV6_EN, VCLK_DIV6_EN);
 879
 880                 if (hdmi_use_enci)
 881                         /* select vclk_div6 for enci */
 882                         hhi_update_bits(HHI_VID_CLK_DIV,
 883                                         CTS_ENCI_SEL_MASK,
 884                                         3 << CTS_ENCI_SEL_SHIFT);
 885                 else
 886                         /* select vclk_div6 for encp */
 887                         hhi_update_bits(HHI_VID_CLK_DIV,
 888                                         CTS_ENCP_SEL_MASK,
 889                                         3 << CTS_ENCP_SEL_SHIFT);
 890                 break;
 891         case 12:
 892                 /* enable vclk_div12 gate */
 893                 hhi_update_bits(HHI_VID_CLK_CNTL,
 894                                 VCLK_DIV12_EN, VCLK_DIV12_EN);
 895
 896                 if (hdmi_use_enci)
 897                         /* select vclk_div12 for enci */
 898                         hhi_update_bits(HHI_VID_CLK_DIV,
 899                                         CTS_ENCI_SEL_MASK,
 900                                         4 << CTS_ENCI_SEL_SHIFT);
 901                 else
 902                         /* select vclk_div12 for encp */
 903                         hhi_update_bits(HHI_VID_CLK_DIV,
 904                                         CTS_ENCP_SEL_MASK,
 905                                         4 << CTS_ENCP_SEL_SHIFT);
 906                 break;
 907         }
 908
 909         if (hdmi_use_enci)
 910                 /* Enable ENCI clock gate */
 911                 hhi_update_bits(HHI_VID_CLK_CNTL2,
 912                                 CTS_ENCI_EN, CTS_ENCI_EN);
 913         else
 914                 /* Enable ENCP clock gate */
 915                 hhi_update_bits(HHI_VID_CLK_CNTL2,
 916                                 CTS_ENCP_EN, CTS_ENCP_EN);
 917
 918         hhi_update_bits(HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
 919 }
 920
 921 static void meson_vclk_setup(struct meson_vpu_priv *priv, unsigned int target,
 922                              unsigned int vclk_freq, unsigned int venc_freq,
 923                              unsigned int dac_freq, bool hdmi_use_enci)
 924 {
 925         bool vic_alternate_clock = false;
 926         unsigned int freq;
 927         unsigned int hdmi_tx_div;
 928         unsigned int venc_div;
 929
 930         if (target == MESON_VCLK_TARGET_CVBS) {
 931                 meson_venci_cvbs_clock_config(priv);
 932                 return;
 933         } else if (target == MESON_VCLK_TARGET_DMT) {
 934                 /* The DMT clock path is fixed after the PLL:
 935                  * - automatic PLL freq + OD management
 936                  * - vid_pll_div = VID_PLL_DIV_5
 937                  * - vclk_div = 2
 938                  * - hdmi_tx_div = 1
 939                  * - venc_div = 1
 940                  * - encp encoder
 941                  */
 942                 meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
 943                                VID_PLL_DIV_5, 2, 1, 1, false, false);
 944                 return;
 945         }
 946
 947         hdmi_tx_div = vclk_freq / dac_freq;
 948
 949         if (hdmi_tx_div == 0) {
 950                 printf("Fatal Error, invalid HDMI-TX freq %d\n",
 951                        dac_freq);
 952                 return;
 953         }
 954
 955         venc_div = vclk_freq / venc_freq;
 956
 957         if (venc_div == 0) {
 958                 printf("Fatal Error, invalid HDMI venc freq %d\n",
 959                        venc_freq);
 960                 return;
 961         }
 962
 963         for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
 964                 if (vclk_freq == params[freq].pixel_freq ||
 965                     vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) {
 966                         if (vclk_freq != params[freq].pixel_freq)
 967                                 vic_alternate_clock = true;
 968                         else
 969                                 vic_alternate_clock = false;
 970
 971                         if (freq == MESON_VCLK_HDMI_ENCI_54000 &&
 972                             !hdmi_use_enci)
 973                                 continue;
 974
 975                         if (freq == MESON_VCLK_HDMI_DDR_54000 &&
 976                             hdmi_use_enci)
 977                                 continue;
 978
 979                         if (freq == MESON_VCLK_HDMI_DDR_148500 &&
 980                             dac_freq == vclk_freq)
 981                                 continue;
 982
 983                         if (freq == MESON_VCLK_HDMI_148500 &&
 984                             dac_freq != vclk_freq)
 985                                 continue;
 986                         break;
 987                 }
 988         }
 989
 990         if (!params[freq].pixel_freq) {
 991                 pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq);
 992                 return;
 993         }
 994
 995         meson_vclk_set(priv, params[freq].pll_base_freq,
 996                        params[freq].pll_od1, params[freq].pll_od2,
 997                        params[freq].pll_od3, params[freq].vid_pll_div,
 998                        params[freq].vclk_div, hdmi_tx_div, venc_div,
 999                        hdmi_use_enci, vic_alternate_clock);
1000 }
1001
1002 void meson_vpu_setup_vclk(struct udevice *dev,
1003                           const struct display_timing *mode, bool is_cvbs)
1004 {
1005         struct meson_vpu_priv *priv = dev_get_priv(dev);
1006         unsigned int vclk_freq;
1007
1008         if (is_cvbs)
1009                 return meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,
1010                                         0, 0, 0, false);
1011
1012         vclk_freq = mode->pixelclock.typ / 1000;
1013
1014         return meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT,
1015                                 vclk_freq, vclk_freq, vclk_freq, false);
1016 }