1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2019 Toradex AG
6 * FSL DCU Framebuffer driver
11 #include <fdt_support.h>
12 #include <fsl_dcu_fb.h>
16 #include "videomodes.h"
18 /* Convert the X,Y resolution pair into a single number */
19 #define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
21 #ifdef CONFIG_SYS_FSL_DCU_LE
22 #define dcu_read32 in_le32
23 #define dcu_write32 out_le32
24 #elif defined(CONFIG_SYS_FSL_DCU_BE)
25 #define dcu_read32 in_be32
26 #define dcu_write32 out_be32
29 #define DCU_MODE_BLEND_ITER(x) ((x) << 20)
30 #define DCU_MODE_RASTER_EN (1 << 14)
31 #define DCU_MODE_NORMAL 1
32 #define DCU_MODE_COLORBAR 3
33 #define DCU_BGND_R(x) ((x) << 16)
34 #define DCU_BGND_G(x) ((x) << 8)
35 #define DCU_BGND_B(x) (x)
36 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
37 #define DCU_DISP_SIZE_DELTA_X(x) (x)
38 #define DCU_HSYN_PARA_BP(x) ((x) << 22)
39 #define DCU_HSYN_PARA_PW(x) ((x) << 11)
40 #define DCU_HSYN_PARA_FP(x) (x)
41 #define DCU_VSYN_PARA_BP(x) ((x) << 22)
42 #define DCU_VSYN_PARA_PW(x) ((x) << 11)
43 #define DCU_VSYN_PARA_FP(x) (x)
44 #define DCU_SYN_POL_INV_PXCK_FALL (1 << 6)
45 #define DCU_SYN_POL_NEG_REMAIN (0 << 5)
46 #define DCU_SYN_POL_INV_VS_LOW (1 << 1)
47 #define DCU_SYN_POL_INV_HS_LOW (1)
48 #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
49 #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
50 #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
51 #define DCU_UPDATE_MODE_MODE (1 << 31)
52 #define DCU_UPDATE_MODE_READREG (1 << 30)
54 #define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16)
55 #define DCU_CTRLDESCLN_1_WIDTH(x) (x)
56 #define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16)
57 #define DCU_CTRLDESCLN_2_POSX(x) (x)
58 #define DCU_CTRLDESCLN_4_EN (1 << 31)
59 #define DCU_CTRLDESCLN_4_TILE_EN (1 << 30)
60 #define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29)
61 #define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28)
62 #define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20)
63 #define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16)
64 #define DCU_CTRLDESCLN_4_RLE_EN (1 << 15)
65 #define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4)
66 #define DCU_CTRLDESCLN_4_BB_ON (1 << 2)
67 #define DCU_CTRLDESCLN_4_AB(x) (x)
68 #define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16)
69 #define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8)
70 #define DCU_CTRLDESCLN_5_CKMAX_B(x) (x)
71 #define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16)
72 #define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8)
73 #define DCU_CTRLDESCLN_6_CKMIN_B(x) (x)
74 #define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16)
75 #define DCU_CTRLDESCLN_7_TILE_HOR(x) (x)
76 #define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x)
77 #define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x)
79 #define BPP_16_RGB565 4
80 #define BPP_24_RGB888 5
81 #define BPP_32_ARGB8888 6
83 DECLARE_GLOBAL_DATA_PTR;
86 * This setting is used for the TWR_LCD_RGB card
88 static struct fb_videomode fsl_dcu_mode_480_272 = {
100 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
101 .vmode = FB_VMODE_NONINTERLACED
105 * This setting is used for Siliconimage SiI9022A HDMI
107 static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
108 .name = "640x480-60",
120 .vmode = FB_VMODE_NONINTERLACED,
123 static struct fb_videomode fsl_dcu_mode_640_480 = {
124 .name = "640x480-60",
136 .vmode = FB_VMODE_NONINTERLACED,
139 static struct fb_videomode fsl_dcu_mode_800_480 = {
140 .name = "800x480-60",
152 .vmode = FB_VMODE_NONINTERLACED,
155 static struct fb_videomode fsl_dcu_mode_1024_600 = {
156 .name = "1024x600-60",
168 .vmode = FB_VMODE_NONINTERLACED,
189 u8 res_064[0x6c-0x64];
190 u32 parr_err_status1;
191 u8 res_070[0x7c-0x70];
192 u32 parr_err_status3;
193 u32 mparr_err_status1;
194 u8 res_084[0x90-0x84];
195 u32 mparr_err_status3;
196 u32 threshold_inp_buf[2];
197 u8 res_09c[0xa0-0x9c];
208 u8 res_0c4[0xcc-0xc8];
211 u8 res_0d4[0x100-0xd4];
218 u8 res_120[0x200-0x120];
219 u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
222 static struct fb_info info;
224 static void reset_total_layers(void)
226 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
229 for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
230 dcu_write32(®s->ctrldescl[i][0], 0);
231 dcu_write32(®s->ctrldescl[i][1], 0);
232 dcu_write32(®s->ctrldescl[i][2], 0);
233 dcu_write32(®s->ctrldescl[i][3], 0);
234 dcu_write32(®s->ctrldescl[i][4], 0);
235 dcu_write32(®s->ctrldescl[i][5], 0);
236 dcu_write32(®s->ctrldescl[i][6], 0);
237 dcu_write32(®s->ctrldescl[i][7], 0);
238 dcu_write32(®s->ctrldescl[i][8], 0);
239 dcu_write32(®s->ctrldescl[i][9], 0);
240 dcu_write32(®s->ctrldescl[i][10], 0);
244 static int layer_ctrldesc_init(struct fb_info fbinfo,
245 int index, u32 pixel_format)
247 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
248 unsigned int bpp = BPP_24_RGB888;
250 dcu_write32(®s->ctrldescl[index][0],
251 DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) |
252 DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres));
254 dcu_write32(®s->ctrldescl[index][1],
255 DCU_CTRLDESCLN_2_POSY(0) |
256 DCU_CTRLDESCLN_2_POSX(0));
258 dcu_write32(®s->ctrldescl[index][2],
259 (unsigned int)fbinfo.screen_base);
261 switch (pixel_format) {
269 bpp = BPP_32_ARGB8888;
272 printf("unsupported color depth: %u\n", pixel_format);
275 dcu_write32(®s->ctrldescl[index][3],
276 DCU_CTRLDESCLN_4_EN |
277 DCU_CTRLDESCLN_4_TRANS(0xff) |
278 DCU_CTRLDESCLN_4_BPP(bpp) |
279 DCU_CTRLDESCLN_4_AB(0));
281 dcu_write32(®s->ctrldescl[index][4],
282 DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
283 DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
284 DCU_CTRLDESCLN_5_CKMAX_B(0xff));
285 dcu_write32(®s->ctrldescl[index][5],
286 DCU_CTRLDESCLN_6_CKMIN_R(0) |
287 DCU_CTRLDESCLN_6_CKMIN_G(0) |
288 DCU_CTRLDESCLN_6_CKMIN_B(0));
290 dcu_write32(®s->ctrldescl[index][6],
291 DCU_CTRLDESCLN_7_TILE_VER(0) |
292 DCU_CTRLDESCLN_7_TILE_HOR(0));
294 dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
295 dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
300 int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres,
301 unsigned int yres, unsigned int pixel_format)
303 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
304 unsigned int div, mode;
306 fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres *
307 (fbinfo->var.bits_per_pixel / 8);
309 if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
310 fbinfo->screen_size = 0;
314 /* Reserve framebuffer at the end of memory */
315 gd->fb_base = gd->bd->bi_dram[0].start +
316 gd->bd->bi_dram[0].size - fbinfo->screen_size;
317 fbinfo->screen_base = (char *)gd->fb_base;
319 memset(fbinfo->screen_base, 0, fbinfo->screen_size);
321 reset_total_layers();
323 dcu_write32(®s->disp_size,
324 DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) |
325 DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16));
327 dcu_write32(®s->hsyn_para,
328 DCU_HSYN_PARA_BP(fbinfo->var.left_margin) |
329 DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) |
330 DCU_HSYN_PARA_FP(fbinfo->var.right_margin));
332 dcu_write32(®s->vsyn_para,
333 DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) |
334 DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) |
335 DCU_VSYN_PARA_FP(fbinfo->var.lower_margin));
337 dcu_write32(®s->synpol,
338 DCU_SYN_POL_INV_PXCK_FALL |
339 DCU_SYN_POL_NEG_REMAIN |
340 DCU_SYN_POL_INV_VS_LOW |
341 DCU_SYN_POL_INV_HS_LOW);
343 dcu_write32(®s->bgnd,
344 DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
346 dcu_write32(®s->mode,
347 DCU_MODE_BLEND_ITER(2) |
350 dcu_write32(®s->threshold,
351 DCU_THRESHOLD_LS_BF_VS(0x3) |
352 DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
353 DCU_THRESHOLD_OUT_BUF_LOW(0));
355 mode = dcu_read32(®s->mode);
356 dcu_write32(®s->mode, mode | DCU_MODE_NORMAL);
358 layer_ctrldesc_init(*fbinfo, 0, pixel_format);
360 div = dcu_set_pixel_clock(fbinfo->var.pixclock);
361 dcu_write32(®s->div_ratio, (div - 1));
363 dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
368 ulong board_get_usable_ram_top(ulong total_size)
370 return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
373 int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x,
377 unsigned int depth = 0, freq = 0;
379 struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
381 if (!video_get_video_mode(win_x, win_y, &depth, &freq,
385 /* Find the monitor port, which is a required option */
389 if (strncmp(options, "monitor=", 8) != 0)
392 switch (RESOLUTION(*win_x, *win_y)) {
393 case RESOLUTION(480, 272):
394 fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
396 case RESOLUTION(640, 480):
397 if (!strncmp(options, "monitor=hdmi", 12))
398 fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
400 fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
402 case RESOLUTION(800, 480):
403 fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
405 case RESOLUTION(1024, 600):
406 fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
409 printf("unsupported resolution %ux%u\n",
413 fbinfo->var.xres = fsl_dcu_mode_db->xres;
414 fbinfo->var.yres = fsl_dcu_mode_db->yres;
415 fbinfo->var.bits_per_pixel = 32;
416 fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock;
417 fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin;
418 fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin;
419 fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin;
420 fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin;
421 fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len;
422 fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len;
423 fbinfo->var.sync = fsl_dcu_mode_db->sync;
424 fbinfo->var.vmode = fsl_dcu_mode_db->vmode;
425 fbinfo->fix.line_length = fbinfo->var.xres *
426 fbinfo->var.bits_per_pixel / 8;
428 return platform_dcu_init(fbinfo, *win_x, *win_y,
429 options + 8, fsl_dcu_mode_db);
432 void *video_hw_init(void)
434 static GraphicDevice ctfb;
436 if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0)
439 ctfb.frameAdrs = (unsigned int)info.screen_base;
440 ctfb.plnSizeX = ctfb.winSizeX;
441 ctfb.plnSizeY = ctfb.winSizeY;
444 ctfb.gdfIndex = GDF_32BIT_X888RGB;
446 ctfb.memSize = info.screen_size;
451 #if defined(CONFIG_OF_BOARD_SETUP)
452 int fsl_dcu_fixedfb_setup(void *blob)
457 start = gd->bd->bi_dram[0].start;
458 size = gd->bd->bi_dram[0].size - info.screen_size;
461 * Align size on section size (1 MiB).
464 ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
466 eprintf("Cannot setup fb: Error reserving memory\n");