drivers/video/fsl_dcu_fb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 Toradex AG
   5  *
   6  * FSL DCU Framebuffer driver
   7  */
   8
   9 #include <asm/io.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <fdt_support.h>
  13 #include <fsl_dcu_fb.h>
  14 #include <linux/fb.h>
  15 #include <malloc.h>
  16 #include <video.h>
  17 #include <video_fb.h>
  18 #include "videomodes.h"
  19
  20 /* Convert the X,Y resolution pair into a single number */
  21 #define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
  22
  23 #ifdef CONFIG_SYS_FSL_DCU_LE
  24 #define dcu_read32      in_le32
  25 #define dcu_write32     out_le32
  26 #elif defined(CONFIG_SYS_FSL_DCU_BE)
  27 #define dcu_read32      in_be32
  28 #define dcu_write32     out_be32
  29 #endif
  30
  31 #define DCU_MODE_BLEND_ITER(x)          ((x) << 20)
  32 #define DCU_MODE_RASTER_EN              (1 << 14)
  33 #define DCU_MODE_NORMAL                 1
  34 #define DCU_MODE_COLORBAR               3
  35 #define DCU_BGND_R(x)                   ((x) << 16)
  36 #define DCU_BGND_G(x)                   ((x) << 8)
  37 #define DCU_BGND_B(x)                   (x)
  38 #define DCU_DISP_SIZE_DELTA_Y(x)        ((x) << 16)
  39 #define DCU_DISP_SIZE_DELTA_X(x)        (x)
  40 #define DCU_HSYN_PARA_BP(x)             ((x) << 22)
  41 #define DCU_HSYN_PARA_PW(x)             ((x) << 11)
  42 #define DCU_HSYN_PARA_FP(x)             (x)
  43 #define DCU_VSYN_PARA_BP(x)             ((x) << 22)
  44 #define DCU_VSYN_PARA_PW(x)             ((x) << 11)
  45 #define DCU_VSYN_PARA_FP(x)             (x)
  46 #define DCU_SYN_POL_INV_PXCK_FALL       (1 << 6)
  47 #define DCU_SYN_POL_NEG_REMAIN          (0 << 5)
  48 #define DCU_SYN_POL_INV_VS_LOW          (1 << 1)
  49 #define DCU_SYN_POL_INV_HS_LOW          (1)
  50 #define DCU_THRESHOLD_LS_BF_VS(x)       ((x) << 16)
  51 #define DCU_THRESHOLD_OUT_BUF_HIGH(x)   ((x) << 8)
  52 #define DCU_THRESHOLD_OUT_BUF_LOW(x)    (x)
  53 #define DCU_UPDATE_MODE_MODE            (1 << 31)
  54 #define DCU_UPDATE_MODE_READREG         (1 << 30)
  55
  56 #define DCU_CTRLDESCLN_1_HEIGHT(x)      ((x) << 16)
  57 #define DCU_CTRLDESCLN_1_WIDTH(x)       (x)
  58 #define DCU_CTRLDESCLN_2_POSY(x)        ((x) << 16)
  59 #define DCU_CTRLDESCLN_2_POSX(x)        (x)
  60 #define DCU_CTRLDESCLN_4_EN             (1 << 31)
  61 #define DCU_CTRLDESCLN_4_TILE_EN        (1 << 30)
  62 #define DCU_CTRLDESCLN_4_DATA_SEL_CLUT  (1 << 29)
  63 #define DCU_CTRLDESCLN_4_SAFETY_EN      (1 << 28)
  64 #define DCU_CTRLDESCLN_4_TRANS(x)       ((x) << 20)
  65 #define DCU_CTRLDESCLN_4_BPP(x)         ((x) << 16)
  66 #define DCU_CTRLDESCLN_4_RLE_EN         (1 << 15)
  67 #define DCU_CTRLDESCLN_4_LUOFFS(x)      ((x) << 4)
  68 #define DCU_CTRLDESCLN_4_BB_ON          (1 << 2)
  69 #define DCU_CTRLDESCLN_4_AB(x)          (x)
  70 #define DCU_CTRLDESCLN_5_CKMAX_R(x)     ((x) << 16)
  71 #define DCU_CTRLDESCLN_5_CKMAX_G(x)     ((x) << 8)
  72 #define DCU_CTRLDESCLN_5_CKMAX_B(x)     (x)
  73 #define DCU_CTRLDESCLN_6_CKMIN_R(x)     ((x) << 16)
  74 #define DCU_CTRLDESCLN_6_CKMIN_G(x)     ((x) << 8)
  75 #define DCU_CTRLDESCLN_6_CKMIN_B(x)     (x)
  76 #define DCU_CTRLDESCLN_7_TILE_VER(x)    ((x) << 16)
  77 #define DCU_CTRLDESCLN_7_TILE_HOR(x)    (x)
  78 #define DCU_CTRLDESCLN_8_FG_FCOLOR(x)   (x)
  79 #define DCU_CTRLDESCLN_9_BG_BCOLOR(x)   (x)
  80
  81 #define BPP_16_RGB565                   4
  82 #define BPP_24_RGB888                   5
  83 #define BPP_32_ARGB8888                 6
  84
  85 DECLARE_GLOBAL_DATA_PTR;
  86
  87 /*
  88  * This setting is used for the TWR_LCD_RGB card
  89  */
  90 static struct fb_videomode fsl_dcu_mode_480_272 = {
  91         .name           = "480x272-60",
  92         .refresh        = 60,
  93         .xres           = 480,
  94         .yres           = 272,
  95         .pixclock       = 91996,
  96         .left_margin    = 2,
  97         .right_margin   = 2,
  98         .upper_margin   = 1,
  99         .lower_margin   = 1,
 100         .hsync_len      = 41,
 101         .vsync_len      = 2,
 102         .sync           = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 103         .vmode          = FB_VMODE_NONINTERLACED
 104 };
 105
 106 /*
 107  * This setting is used for Siliconimage SiI9022A HDMI
 108  */
 109 static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
 110         .name           = "640x480-60",
 111         .refresh        = 60,
 112         .xres           = 640,
 113         .yres           = 480,
 114         .pixclock       = 39722,
 115         .left_margin    = 48,
 116         .right_margin   = 16,
 117         .upper_margin   = 33,
 118         .lower_margin   = 10,
 119         .hsync_len      = 96,
 120         .vsync_len      = 2,
 121         .sync           = 0,
 122         .vmode          = FB_VMODE_NONINTERLACED,
 123 };
 124
 125 static struct fb_videomode fsl_dcu_mode_640_480 = {
 126         .name           = "640x480-60",
 127         .refresh        = 60,
 128         .xres           = 640,
 129         .yres           = 480,
 130         .pixclock       = 25175,
 131         .left_margin    = 40,
 132         .right_margin   = 24,
 133         .upper_margin   = 32,
 134         .lower_margin   = 11,
 135         .hsync_len      = 96,
 136         .vsync_len      = 2,
 137         .sync           = 0,
 138         .vmode          = FB_VMODE_NONINTERLACED,
 139 };
 140
 141 static struct fb_videomode fsl_dcu_mode_800_480 = {
 142         .name           = "800x480-60",
 143         .refresh        = 60,
 144         .xres           = 800,
 145         .yres           = 480,
 146         .pixclock       = 33260,
 147         .left_margin    = 216,
 148         .right_margin   = 40,
 149         .upper_margin   = 35,
 150         .lower_margin   = 10,
 151         .hsync_len      = 128,
 152         .vsync_len      = 2,
 153         .sync           = 0,
 154         .vmode          = FB_VMODE_NONINTERLACED,
 155 };
 156
 157 static struct fb_videomode fsl_dcu_mode_1024_600 = {
 158         .name           = "1024x600-60",
 159         .refresh        = 60,
 160         .xres           = 1024,
 161         .yres           = 600,
 162         .pixclock       = 48000,
 163         .left_margin    = 104,
 164         .right_margin   = 43,
 165         .upper_margin   = 24,
 166         .lower_margin   = 20,
 167         .hsync_len      = 5,
 168         .vsync_len      = 5,
 169         .sync           = 0,
 170         .vmode          = FB_VMODE_NONINTERLACED,
 171 };
 172
 173 /*
 174  * DCU register map
 175  */
 176 struct dcu_reg {
 177         u32 desc_cursor[4];
 178         u32 mode;
 179         u32 bgnd;
 180         u32 disp_size;
 181         u32 hsyn_para;
 182         u32 vsyn_para;
 183         u32 synpol;
 184         u32 threshold;
 185         u32 int_status;
 186         u32 int_mask;
 187         u32 colbar[8];
 188         u32 div_ratio;
 189         u32 sign_calc[2];
 190         u32 crc_val;
 191         u8 res_064[0x6c-0x64];
 192         u32 parr_err_status1;
 193         u8 res_070[0x7c-0x70];
 194         u32 parr_err_status3;
 195         u32 mparr_err_status1;
 196         u8 res_084[0x90-0x84];
 197         u32 mparr_err_status3;
 198         u32 threshold_inp_buf[2];
 199         u8 res_09c[0xa0-0x9c];
 200         u32 luma_comp;
 201         u32 chroma_red;
 202         u32 chroma_green;
 203         u32 chroma_blue;
 204         u32 crc_pos;
 205         u32 lyr_intpol_en;
 206         u32 lyr_luma_comp;
 207         u32 lyr_chrm_red;
 208         u32 lyr_chrm_grn;
 209         u32 lyr_chrm_blue;
 210         u8 res_0c4[0xcc-0xc8];
 211         u32 update_mode;
 212         u32 underrun;
 213         u8 res_0d4[0x100-0xd4];
 214         u32 gpr;
 215         u32 slr_l[2];
 216         u32 slr_disp_size;
 217         u32 slr_hvsync_para;
 218         u32 slr_pol;
 219         u32 slr_l_transp[2];
 220         u8 res_120[0x200-0x120];
 221         u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
 222 };
 223
 224 static void reset_total_layers(void)
 225 {
 226         struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
 227         int i;
 228
 229         for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
 230                 dcu_write32(&regs->ctrldescl[i][0], 0);
 231                 dcu_write32(&regs->ctrldescl[i][1], 0);
 232                 dcu_write32(&regs->ctrldescl[i][2], 0);
 233                 dcu_write32(&regs->ctrldescl[i][3], 0);
 234                 dcu_write32(&regs->ctrldescl[i][4], 0);
 235                 dcu_write32(&regs->ctrldescl[i][5], 0);
 236                 dcu_write32(&regs->ctrldescl[i][6], 0);
 237                 dcu_write32(&regs->ctrldescl[i][7], 0);
 238                 dcu_write32(&regs->ctrldescl[i][8], 0);
 239                 dcu_write32(&regs->ctrldescl[i][9], 0);
 240                 dcu_write32(&regs->ctrldescl[i][10], 0);
 241         }
 242 }
 243
 244 static int layer_ctrldesc_init(struct fb_info fbinfo,
 245                                int index, u32 pixel_format)
 246 {
 247         struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
 248         unsigned int bpp = BPP_24_RGB888;
 249
 250         dcu_write32(&regs->ctrldescl[index][0],
 251                     DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) |
 252                     DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres));
 253
 254         dcu_write32(&regs->ctrldescl[index][1],
 255                     DCU_CTRLDESCLN_2_POSY(0) |
 256                     DCU_CTRLDESCLN_2_POSX(0));
 257
 258         dcu_write32(&regs->ctrldescl[index][2],
 259                     (unsigned int)fbinfo.screen_base);
 260
 261         switch (pixel_format) {
 262         case 16:
 263                 bpp = BPP_16_RGB565;
 264                 break;
 265         case 24:
 266                 bpp = BPP_24_RGB888;
 267                 break;
 268         case 32:
 269                 bpp = BPP_32_ARGB8888;
 270                 break;
 271         default:
 272                 printf("unsupported color depth: %u\n", pixel_format);
 273         }
 274
 275         dcu_write32(&regs->ctrldescl[index][3],
 276                     DCU_CTRLDESCLN_4_EN |
 277                     DCU_CTRLDESCLN_4_TRANS(0xff) |
 278                     DCU_CTRLDESCLN_4_BPP(bpp) |
 279                     DCU_CTRLDESCLN_4_AB(0));
 280
 281         dcu_write32(&regs->ctrldescl[index][4],
 282                     DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
 283                     DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
 284                     DCU_CTRLDESCLN_5_CKMAX_B(0xff));
 285         dcu_write32(&regs->ctrldescl[index][5],
 286                     DCU_CTRLDESCLN_6_CKMIN_R(0) |
 287                     DCU_CTRLDESCLN_6_CKMIN_G(0) |
 288                     DCU_CTRLDESCLN_6_CKMIN_B(0));
 289
 290         dcu_write32(&regs->ctrldescl[index][6],
 291                     DCU_CTRLDESCLN_7_TILE_VER(0) |
 292                     DCU_CTRLDESCLN_7_TILE_HOR(0));
 293
 294         dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
 295         dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
 296
 297         return 0;
 298 }
 299
 300 int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres,
 301                  unsigned int yres, unsigned int pixel_format)
 302 {
 303         struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
 304         unsigned int div, mode;
 305 /*
 306  * When DM_VIDEO is enabled reservation of framebuffer is done
 307  * in advance during bind() call.
 308  */
 309 #if !CONFIG_IS_ENABLED(DM_VIDEO)
 310         fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres *
 311                              (fbinfo->var.bits_per_pixel / 8);
 312
 313         if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
 314                 fbinfo->screen_size = 0;
 315                 return -ENOMEM;
 316         }
 317         /* Reserve framebuffer at the end of memory */
 318         gd->fb_base = gd->bd->bi_dram[0].start +
 319                         gd->bd->bi_dram[0].size - fbinfo->screen_size;
 320         fbinfo->screen_base = (char *)gd->fb_base;
 321
 322         memset(fbinfo->screen_base, 0, fbinfo->screen_size);
 323 #endif
 324
 325         reset_total_layers();
 326
 327         dcu_write32(&regs->disp_size,
 328                     DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) |
 329                     DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16));
 330
 331         dcu_write32(&regs->hsyn_para,
 332                     DCU_HSYN_PARA_BP(fbinfo->var.left_margin) |
 333                     DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) |
 334                     DCU_HSYN_PARA_FP(fbinfo->var.right_margin));
 335
 336         dcu_write32(&regs->vsyn_para,
 337                     DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) |
 338                     DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) |
 339                     DCU_VSYN_PARA_FP(fbinfo->var.lower_margin));
 340
 341         dcu_write32(&regs->synpol,
 342                     DCU_SYN_POL_INV_PXCK_FALL |
 343                     DCU_SYN_POL_NEG_REMAIN |
 344                     DCU_SYN_POL_INV_VS_LOW |
 345                     DCU_SYN_POL_INV_HS_LOW);
 346
 347         dcu_write32(&regs->bgnd,
 348                     DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
 349
 350         dcu_write32(&regs->mode,
 351                     DCU_MODE_BLEND_ITER(2) |
 352                     DCU_MODE_RASTER_EN);
 353
 354         dcu_write32(&regs->threshold,
 355                     DCU_THRESHOLD_LS_BF_VS(0x3) |
 356                     DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
 357                     DCU_THRESHOLD_OUT_BUF_LOW(0));
 358
 359         mode = dcu_read32(&regs->mode);
 360         dcu_write32(&regs->mode, mode | DCU_MODE_NORMAL);
 361
 362         layer_ctrldesc_init(*fbinfo, 0, pixel_format);
 363
 364         div = dcu_set_pixel_clock(fbinfo->var.pixclock);
 365         dcu_write32(&regs->div_ratio, (div - 1));
 366
 367         dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
 368
 369         return 0;
 370 }
 371
 372 ulong board_get_usable_ram_top(ulong total_size)
 373 {
 374         return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
 375 }
 376
 377 int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x,
 378                      unsigned int *win_y)
 379 {
 380         const char *options;
 381         unsigned int depth = 0, freq = 0;
 382
 383         struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
 384
 385         if (!video_get_video_mode(win_x, win_y, &depth, &freq,
 386                                   &options))
 387                 return -EINVAL;
 388
 389         /* Find the monitor port, which is a required option */
 390         if (!options)
 391                 return -EINVAL;
 392
 393         if (strncmp(options, "monitor=", 8) != 0)
 394                 return -EINVAL;
 395
 396         switch (RESOLUTION(*win_x, *win_y)) {
 397         case RESOLUTION(480, 272):
 398                 fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
 399                 break;
 400         case RESOLUTION(640, 480):
 401                 if (!strncmp(options, "monitor=hdmi", 12))
 402                         fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
 403                 else
 404                         fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
 405                 break;
 406         case RESOLUTION(800, 480):
 407                 fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
 408                 break;
 409         case RESOLUTION(1024, 600):
 410                 fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
 411                 break;
 412         default:
 413                 printf("unsupported resolution %ux%u\n",
 414                        *win_x, *win_y);
 415         }
 416
 417         fbinfo->var.xres = fsl_dcu_mode_db->xres;
 418         fbinfo->var.yres = fsl_dcu_mode_db->yres;
 419         fbinfo->var.bits_per_pixel = 32;
 420         fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock;
 421         fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin;
 422         fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin;
 423         fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin;
 424         fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin;
 425         fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len;
 426         fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len;
 427         fbinfo->var.sync = fsl_dcu_mode_db->sync;
 428         fbinfo->var.vmode = fsl_dcu_mode_db->vmode;
 429         fbinfo->fix.line_length = fbinfo->var.xres *
 430                                   fbinfo->var.bits_per_pixel / 8;
 431
 432         return platform_dcu_init(fbinfo, *win_x, *win_y,
 433                                  options + 8, fsl_dcu_mode_db);
 434 }
 435
 436 #ifndef CONFIG_DM_VIDEO
 437 static struct fb_info info;
 438
 439 #if defined(CONFIG_OF_BOARD_SETUP)
 440 int fsl_dcu_fixedfb_setup(void *blob)
 441 {
 442         u64 start, size;
 443         int ret;
 444
 445         start = gd->bd->bi_dram[0].start;
 446         size = gd->bd->bi_dram[0].size - info.screen_size;
 447
 448         /*
 449          * Align size on section size (1 MiB).
 450          */
 451         size &= 0xfff00000;
 452         ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
 453         if (ret) {
 454                 eprintf("Cannot setup fb: Error reserving memory\n");
 455                 return ret;
 456         }
 457
 458         return 0;
 459 }
 460 #endif
 461
 462 void *video_hw_init(void)
 463 {
 464         static GraphicDevice ctfb;
 465
 466         if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0)
 467                 return NULL;
 468
 469         ctfb.frameAdrs = (unsigned int)info.screen_base;
 470         ctfb.plnSizeX = ctfb.winSizeX;
 471         ctfb.plnSizeY = ctfb.winSizeY;
 472
 473         ctfb.gdfBytesPP = 4;
 474         ctfb.gdfIndex = GDF_32BIT_X888RGB;
 475
 476         ctfb.memSize = info.screen_size;
 477
 478         return &ctfb;
 479 }
 480
 481 #else /* ifndef CONFIG_DM_VIDEO */
 482
 483 static int fsl_dcu_video_probe(struct udevice *dev)
 484 {
 485         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 486         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 487         struct fb_info fbinfo = { 0 };
 488         unsigned int win_x;
 489         unsigned int win_y;
 490         u32 fb_start, fb_end;
 491         int ret = 0;
 492
 493         fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
 494         fb_end = plat->base + plat->size;
 495         fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
 496
 497         fbinfo.screen_base = (char *)fb_start;
 498         fbinfo.screen_size = plat->size;
 499
 500         ret = fsl_probe_common(&fbinfo, &win_x, &win_y);
 501         if (ret < 0)
 502                 return ret;
 503
 504         uc_priv->bpix = VIDEO_BPP32;
 505         uc_priv->xsize = win_x;
 506         uc_priv->ysize = win_y;
 507
 508         /* Enable dcache for the frame buffer */
 509         mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 510                                         DCACHE_WRITEBACK);
 511         video_set_flush_dcache(dev, true);
 512         return ret;
 513 }
 514
 515 static int fsl_dcu_video_bind(struct udevice *dev)
 516 {
 517         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 518         unsigned int win_x;
 519         unsigned int win_y;
 520         unsigned int depth = 0, freq = 0;
 521         const char *options;
 522         int ret = 0;
 523
 524         ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options);
 525         if (ret < 0)
 526                 return ret;
 527
 528         plat->size = win_x * win_y * 32;
 529
 530         return 0;
 531 }
 532
 533 static const struct udevice_id fsl_dcu_video_ids[] = {
 534         { .compatible = "fsl,vf610-dcu" },
 535         { /* sentinel */ }
 536 };
 537
 538 U_BOOT_DRIVER(fsl_dcu_video) = {
 539         .name   = "fsl_dcu_video",
 540         .id     = UCLASS_VIDEO,
 541         .of_match = fsl_dcu_video_ids,
 542         .bind   = fsl_dcu_video_bind,
 543         .probe  = fsl_dcu_video_probe,
 544         .flags  = DM_FLAG_PRE_RELOC,
 545 };
 546 #endif /* ifndef CONFIG_DM_VIDEO */