drivers/video/exynos/exynos_dp_lowlevel.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Samsung Electronics
   4  *
   5  * Author: Donghwa Lee <dh09.lee@samsung.com>
   6  */
   7
   8 #include <config.h>
   9 #include <common.h>
  10 #include <log.h>
  11 #include <linux/err.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/dp_info.h>
  14 #include <asm/arch/dp.h>
  15 #include <fdtdec.h>
  16 #include <linux/libfdt.h>
  17 #include "exynos_dp_lowlevel.h"
  18
  19 /* Declare global data pointer */
  20 static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
  21                                          unsigned int enable)
  22 {
  23         unsigned int reg;
  24
  25         reg = readl(&dp_regs->video_ctl1);
  26         reg &= ~VIDEO_EN_MASK;
  27
  28         /* enable video input */
  29         if (enable)
  30                 reg |= VIDEO_EN_MASK;
  31
  32         writel(reg, &dp_regs->video_ctl1);
  33
  34         return;
  35 }
  36
  37 void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, unsigned int enable)
  38 {
  39         /* enable video bist */
  40         unsigned int reg;
  41
  42         reg = readl(&dp_regs->video_ctl4);
  43         reg &= ~VIDEO_BIST_MASK;
  44
  45         /* enable video bist */
  46         if (enable)
  47                 reg |= VIDEO_BIST_MASK;
  48
  49         writel(reg, &dp_regs->video_ctl4);
  50
  51         return;
  52 }
  53
  54 void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, unsigned int enable)
  55 {
  56         unsigned int reg;
  57
  58         reg = readl(&dp_regs->video_ctl1);
  59         reg &= ~(VIDEO_MUTE_MASK);
  60         if (enable)
  61                 reg |= VIDEO_MUTE_MASK;
  62
  63         writel(reg, &dp_regs->video_ctl1);
  64
  65         return;
  66 }
  67
  68
  69 static void exynos_dp_init_analog_param(struct exynos_dp *dp_regs)
  70 {
  71         unsigned int reg;
  72
  73         /*
  74          * Set termination
  75          * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
  76          * 24M Phy clock, TX digital logic power is 100:1.0625V
  77          */
  78         reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
  79                 SWING_A_30PER_G_NORMAL;
  80         writel(reg, &dp_regs->analog_ctl1);
  81
  82         reg = SEL_24M | TX_DVDD_BIT_1_0625V;
  83         writel(reg, &dp_regs->analog_ctl2);
  84
  85         /*
  86          * Set power source for internal clk driver to 1.0625v.
  87          * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
  88          * Set VCO range of PLL +- 0uA
  89          */
  90         reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
  91         writel(reg, &dp_regs->analog_ctl3);
  92
  93         /*
  94          * Set AUX TX terminal resistor to 102 ohm
  95          * Set AUX channel amplitude control
  96          */
  97         reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
  98         writel(reg, &dp_regs->pll_filter_ctl1);
  99
 100         /*
 101          * PLL loop filter bandwidth
 102          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 103          * PLL digital power select: 1.2500V
 104          */
 105         reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
 106
 107         writel(reg, &dp_regs->amp_tuning_ctl);
 108
 109         /*
 110          * PLL loop filter bandwidth
 111          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 112          * PLL digital power select: 1.1250V
 113          */
 114         reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
 115         writel(reg, &dp_regs->pll_ctl);
 116 }
 117
 118 static void exynos_dp_init_interrupt(struct exynos_dp *dp_regs)
 119 {
 120         /* Set interrupt registers to initial states */
 121
 122         /*
 123          * Disable interrupt
 124          * INT pin assertion polarity. It must be configured
 125          * correctly according to ICU setting.
 126          * 1 = assert high, 0 = assert low
 127          */
 128         writel(INT_POL, &dp_regs->int_ctl);
 129
 130         /* Clear pending registers */
 131         writel(0xff, &dp_regs->common_int_sta1);
 132         writel(0xff, &dp_regs->common_int_sta2);
 133         writel(0xff, &dp_regs->common_int_sta3);
 134         writel(0xff, &dp_regs->common_int_sta4);
 135         writel(0xff, &dp_regs->int_sta);
 136
 137         /* 0:mask,1: unmask */
 138         writel(0x00, &dp_regs->int_sta_mask1);
 139         writel(0x00, &dp_regs->int_sta_mask2);
 140         writel(0x00, &dp_regs->int_sta_mask3);
 141         writel(0x00, &dp_regs->int_sta_mask4);
 142         writel(0x00, &dp_regs->int_sta_mask);
 143 }
 144
 145 void exynos_dp_reset(struct exynos_dp *dp_regs)
 146 {
 147         unsigned int reg_func_1;
 148
 149         /* dp tx sw reset */
 150         writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
 151
 152         exynos_dp_enable_video_input(dp_regs, DP_DISABLE);
 153         exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
 154         exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
 155
 156         /* software reset */
 157         reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 158                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 159                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 160
 161         writel(reg_func_1, &dp_regs->func_en1);
 162         writel(reg_func_1, &dp_regs->func_en2);
 163
 164         mdelay(1);
 165
 166         exynos_dp_init_analog_param(dp_regs);
 167         exynos_dp_init_interrupt(dp_regs);
 168
 169         return;
 170 }
 171
 172 void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable)
 173 {
 174         unsigned int reg;
 175
 176         reg = readl(&dp_regs->func_en1);
 177         reg &= ~(SW_FUNC_EN_N);
 178
 179         if (!enable)
 180                 reg |= SW_FUNC_EN_N;
 181
 182         writel(reg, &dp_regs->func_en1);
 183
 184         return;
 185 }
 186
 187 unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
 188                                              unsigned int block, u32 enable)
 189 {
 190         unsigned int reg;
 191
 192         reg = readl(&dp_regs->phy_pd);
 193         switch (block) {
 194         case AUX_BLOCK:
 195                 reg &= ~(AUX_PD);
 196                 if (enable)
 197                         reg |= AUX_PD;
 198                 break;
 199         case CH0_BLOCK:
 200                 reg &= ~(CH0_PD);
 201                 if (enable)
 202                         reg |= CH0_PD;
 203                 break;
 204         case CH1_BLOCK:
 205                 reg &= ~(CH1_PD);
 206                 if (enable)
 207                         reg |= CH1_PD;
 208                 break;
 209         case CH2_BLOCK:
 210                 reg &= ~(CH2_PD);
 211                 if (enable)
 212                         reg |= CH2_PD;
 213                 break;
 214         case CH3_BLOCK:
 215                 reg &= ~(CH3_PD);
 216                 if (enable)
 217                         reg |= CH3_PD;
 218                 break;
 219         case ANALOG_TOTAL:
 220                 reg &= ~PHY_PD;
 221                 if (enable)
 222                         reg |= PHY_PD;
 223                 break;
 224         case POWER_ALL:
 225                 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
 226                         CH3_PD);
 227                 if (enable)
 228                         reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
 229                                 CH2_PD | CH3_PD);
 230                 break;
 231         default:
 232                 printf("DP undefined block number : %d\n",  block);
 233                 return -1;
 234         }
 235
 236         writel(reg, &dp_regs->phy_pd);
 237
 238         return 0;
 239 }
 240
 241 unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs)
 242 {
 243         unsigned int reg;
 244
 245         reg = readl(&dp_regs->debug_ctl);
 246
 247         if (reg & PLL_LOCK)
 248                 return PLL_LOCKED;
 249         else
 250                 return PLL_UNLOCKED;
 251 }
 252
 253 static void exynos_dp_set_pll_power(struct exynos_dp *dp_regs,
 254                                     unsigned int enable)
 255 {
 256         unsigned int reg;
 257
 258         reg = readl(&dp_regs->pll_ctl);
 259         reg &= ~(DP_PLL_PD);
 260
 261         if (!enable)
 262                 reg |= DP_PLL_PD;
 263
 264         writel(reg, &dp_regs->pll_ctl);
 265 }
 266
 267 int exynos_dp_init_analog_func(struct exynos_dp *dp_regs)
 268 {
 269         int ret = EXYNOS_DP_SUCCESS;
 270         unsigned int retry_cnt = 10;
 271         unsigned int reg;
 272
 273         /* Power On All Analog block */
 274         exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, DP_DISABLE);
 275
 276         reg = PLL_LOCK_CHG;
 277         writel(reg, &dp_regs->common_int_sta1);
 278
 279         reg = readl(&dp_regs->debug_ctl);
 280         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 281         writel(reg, &dp_regs->debug_ctl);
 282
 283         /* Assert DP PLL Reset */
 284         reg = readl(&dp_regs->pll_ctl);
 285         reg |= DP_PLL_RESET;
 286         writel(reg, &dp_regs->pll_ctl);
 287
 288         mdelay(1);
 289
 290         /* Deassert DP PLL Reset */
 291         reg = readl(&dp_regs->pll_ctl);
 292         reg &= ~(DP_PLL_RESET);
 293         writel(reg, &dp_regs->pll_ctl);
 294
 295         exynos_dp_set_pll_power(dp_regs, DP_ENABLE);
 296
 297         while (exynos_dp_get_pll_lock_status(dp_regs) == PLL_UNLOCKED) {
 298                 mdelay(1);
 299                 retry_cnt--;
 300                 if (retry_cnt == 0) {
 301                         printf("DP dp's pll lock failed : retry : %d\n",
 302                                         retry_cnt);
 303                         return -EINVAL;
 304                 }
 305         }
 306
 307         debug("dp's pll lock success(%d)\n", retry_cnt);
 308
 309         /* Enable Serdes FIFO function and Link symbol clock domain module */
 310         reg = readl(&dp_regs->func_en2);
 311         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 312                 | AUX_FUNC_EN_N);
 313         writel(reg, &dp_regs->func_en2);
 314
 315         return ret;
 316 }
 317
 318 void exynos_dp_init_hpd(struct exynos_dp *dp_regs)
 319 {
 320         unsigned int reg;
 321
 322         /* Clear interrupts related to Hot Plug Detect */
 323         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 324         writel(reg, &dp_regs->common_int_sta4);
 325
 326         reg = INT_HPD;
 327         writel(reg, &dp_regs->int_sta);
 328
 329         reg = readl(&dp_regs->sys_ctl3);
 330         reg &= ~(F_HPD | HPD_CTRL);
 331         writel(reg, &dp_regs->sys_ctl3);
 332
 333         return;
 334 }
 335
 336 static inline void exynos_dp_reset_aux(struct exynos_dp *dp_regs)
 337 {
 338         unsigned int reg;
 339
 340         /* Disable AUX channel module */
 341         reg = readl(&dp_regs->func_en2);
 342         reg |= AUX_FUNC_EN_N;
 343         writel(reg, &dp_regs->func_en2);
 344
 345         return;
 346 }
 347
 348 void exynos_dp_init_aux(struct exynos_dp *dp_regs)
 349 {
 350         unsigned int reg;
 351
 352         /* Clear interrupts related to AUX channel */
 353         reg = RPLY_RECEIV | AUX_ERR;
 354         writel(reg, &dp_regs->int_sta);
 355
 356         exynos_dp_reset_aux(dp_regs);
 357
 358         /* Disable AUX transaction H/W retry */
 359         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
 360                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 361         writel(reg, &dp_regs->aux_hw_retry_ctl);
 362
 363         /* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
 364         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 365         writel(reg, &dp_regs->aux_ch_defer_ctl);
 366
 367         /* Enable AUX channel module */
 368         reg = readl(&dp_regs->func_en2);
 369         reg &= ~AUX_FUNC_EN_N;
 370         writel(reg, &dp_regs->func_en2);
 371
 372         return;
 373 }
 374
 375 void exynos_dp_config_interrupt(struct exynos_dp *dp_regs)
 376 {
 377         unsigned int reg;
 378
 379         /* 0: mask, 1: unmask */
 380         reg = COMMON_INT_MASK_1;
 381         writel(reg, &dp_regs->common_int_mask1);
 382
 383         reg = COMMON_INT_MASK_2;
 384         writel(reg, &dp_regs->common_int_mask2);
 385
 386         reg = COMMON_INT_MASK_3;
 387         writel(reg, &dp_regs->common_int_mask3);
 388
 389         reg = COMMON_INT_MASK_4;
 390         writel(reg, &dp_regs->common_int_mask4);
 391
 392         reg = INT_STA_MASK;
 393         writel(reg, &dp_regs->int_sta_mask);
 394
 395         return;
 396 }
 397
 398 unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs)
 399 {
 400         unsigned int reg;
 401
 402         reg = readl(&dp_regs->sys_ctl3);
 403         if (reg & HPD_STATUS)
 404                 return 0;
 405
 406         return -1;
 407 }
 408
 409 unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs)
 410 {
 411         int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
 412
 413         mdelay(2);
 414
 415         while (exynos_dp_get_plug_in_status(dp_regs) != 0) {
 416                 if (timeout_loop == 0)
 417                         return -EINVAL;
 418                 mdelay(10);
 419                 timeout_loop--;
 420         }
 421
 422         return EXYNOS_DP_SUCCESS;
 423 }
 424
 425 unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs)
 426 {
 427         unsigned int reg;
 428         unsigned int ret = 0;
 429         unsigned int retry_cnt;
 430
 431         /* Enable AUX CH operation */
 432         reg = readl(&dp_regs->aux_ch_ctl2);
 433         reg |= AUX_EN;
 434         writel(reg, &dp_regs->aux_ch_ctl2);
 435
 436         retry_cnt = 10;
 437         while (retry_cnt) {
 438                 reg = readl(&dp_regs->int_sta);
 439                 if (!(reg & RPLY_RECEIV)) {
 440                         if (retry_cnt == 0) {
 441                                 printf("DP Reply Timeout!!\n");
 442                                 ret = -EAGAIN;
 443                                 return ret;
 444                         }
 445                         mdelay(1);
 446                         retry_cnt--;
 447                 } else
 448                         break;
 449         }
 450
 451         /* Clear interrupt source for AUX CH command reply */
 452         writel(reg, &dp_regs->int_sta);
 453
 454         /* Clear interrupt source for AUX CH access error */
 455         reg = readl(&dp_regs->int_sta);
 456         if (reg & AUX_ERR) {
 457                 printf("DP Aux Access Error\n");
 458                 writel(AUX_ERR, &dp_regs->int_sta);
 459                 ret = -EAGAIN;
 460                 return ret;
 461         }
 462
 463         /* Check AUX CH error access status */
 464         reg = readl(&dp_regs->aux_ch_sta);
 465         if ((reg & AUX_STATUS_MASK) != 0) {
 466                 debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
 467                 ret = -EAGAIN;
 468                 return ret;
 469         }
 470
 471         return EXYNOS_DP_SUCCESS;
 472 }
 473
 474 unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
 475                                           unsigned int reg_addr,
 476                                           unsigned char data)
 477 {
 478         unsigned int reg, ret;
 479
 480         /* Clear AUX CH data buffer */
 481         reg = BUF_CLR;
 482         writel(reg, &dp_regs->buffer_data_ctl);
 483
 484         /* Select DPCD device address */
 485         reg = AUX_ADDR_7_0(reg_addr);
 486         writel(reg, &dp_regs->aux_addr_7_0);
 487         reg = AUX_ADDR_15_8(reg_addr);
 488         writel(reg, &dp_regs->aux_addr_15_8);
 489         reg = AUX_ADDR_19_16(reg_addr);
 490         writel(reg, &dp_regs->aux_addr_19_16);
 491
 492         /* Write data buffer */
 493         reg = (unsigned int)data;
 494         writel(reg, &dp_regs->buf_data0);
 495
 496         /*
 497          * Set DisplayPort transaction and write 1 byte
 498          * If bit 3 is 1, DisplayPort transaction.
 499          * If Bit 3 is 0, I2C transaction.
 500          */
 501         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 502         writel(reg, &dp_regs->aux_ch_ctl1);
 503
 504         /* Start AUX transaction */
 505         ret = exynos_dp_start_aux_transaction(dp_regs);
 506         if (ret != EXYNOS_DP_SUCCESS) {
 507                 printf("DP Aux transaction failed\n");
 508                 return ret;
 509         }
 510
 511         return ret;
 512 }
 513
 514 unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
 515                                            unsigned int reg_addr,
 516                                            unsigned char *data)
 517 {
 518         unsigned int reg;
 519         int retval;
 520
 521         /* Clear AUX CH data buffer */
 522         reg = BUF_CLR;
 523         writel(reg, &dp_regs->buffer_data_ctl);
 524
 525         /* Select DPCD device address */
 526         reg = AUX_ADDR_7_0(reg_addr);
 527         writel(reg, &dp_regs->aux_addr_7_0);
 528         reg = AUX_ADDR_15_8(reg_addr);
 529         writel(reg, &dp_regs->aux_addr_15_8);
 530         reg = AUX_ADDR_19_16(reg_addr);
 531         writel(reg, &dp_regs->aux_addr_19_16);
 532
 533         /*
 534          * Set DisplayPort transaction and read 1 byte
 535          * If bit 3 is 1, DisplayPort transaction.
 536          * If Bit 3 is 0, I2C transaction.
 537          */
 538         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 539         writel(reg, &dp_regs->aux_ch_ctl1);
 540
 541         /* Start AUX transaction */
 542         retval = exynos_dp_start_aux_transaction(dp_regs);
 543         if (!retval)
 544                 debug("DP Aux Transaction fail!\n");
 545
 546         /* Read data buffer */
 547         reg = readl(&dp_regs->buf_data0);
 548         *data = (unsigned char)(reg & 0xff);
 549
 550         return retval;
 551 }
 552
 553 unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
 554                                            unsigned int reg_addr,
 555                                            unsigned int count,
 556                                            unsigned char data[])
 557 {
 558         unsigned int reg;
 559         unsigned int start_offset;
 560         unsigned int cur_data_count;
 561         unsigned int cur_data_idx;
 562         unsigned int retry_cnt;
 563         unsigned int ret = 0;
 564
 565         /* Clear AUX CH data buffer */
 566         reg = BUF_CLR;
 567         writel(reg, &dp_regs->buffer_data_ctl);
 568
 569         start_offset = 0;
 570         while (start_offset < count) {
 571                 /* Buffer size of AUX CH is 16 * 4bytes */
 572                 if ((count - start_offset) > 16)
 573                         cur_data_count = 16;
 574                 else
 575                         cur_data_count = count - start_offset;
 576
 577                 retry_cnt = 5;
 578                 while (retry_cnt) {
 579                         /* Select DPCD device address */
 580                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 581                         writel(reg, &dp_regs->aux_addr_7_0);
 582                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 583                         writel(reg, &dp_regs->aux_addr_15_8);
 584                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 585                         writel(reg, &dp_regs->aux_addr_19_16);
 586
 587                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 588                                         cur_data_idx++) {
 589                                 reg = data[start_offset + cur_data_idx];
 590                                 writel(reg, (unsigned int)&dp_regs->buf_data0 +
 591                                                 (4 * cur_data_idx));
 592                         }
 593                         /*
 594                         * Set DisplayPort transaction and write
 595                         * If bit 3 is 1, DisplayPort transaction.
 596                         * If Bit 3 is 0, I2C transaction.
 597                         */
 598                         reg = AUX_LENGTH(cur_data_count) |
 599                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 600                         writel(reg, &dp_regs->aux_ch_ctl1);
 601
 602                         /* Start AUX transaction */
 603                         ret = exynos_dp_start_aux_transaction(dp_regs);
 604                         if (ret != EXYNOS_DP_SUCCESS) {
 605                                 if (retry_cnt == 0) {
 606                                         printf("DP Aux Transaction failed\n");
 607                                         return ret;
 608                                 }
 609                                 retry_cnt--;
 610                         } else
 611                                 break;
 612                 }
 613                 start_offset += cur_data_count;
 614         }
 615
 616         return ret;
 617 }
 618
 619 unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
 620                                             unsigned int reg_addr,
 621                                             unsigned int count,
 622                                             unsigned char data[])
 623 {
 624         unsigned int reg;
 625         unsigned int start_offset;
 626         unsigned int cur_data_count;
 627         unsigned int cur_data_idx;
 628         unsigned int retry_cnt;
 629         unsigned int ret = 0;
 630
 631         /* Clear AUX CH data buffer */
 632         reg = BUF_CLR;
 633         writel(reg, &dp_regs->buffer_data_ctl);
 634
 635         start_offset = 0;
 636         while (start_offset < count) {
 637                 /* Buffer size of AUX CH is 16 * 4bytes */
 638                 if ((count - start_offset) > 16)
 639                         cur_data_count = 16;
 640                 else
 641                         cur_data_count = count - start_offset;
 642
 643                 retry_cnt = 5;
 644                 while (retry_cnt) {
 645                         /* Select DPCD device address */
 646                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 647                         writel(reg, &dp_regs->aux_addr_7_0);
 648                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 649                         writel(reg, &dp_regs->aux_addr_15_8);
 650                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 651                         writel(reg, &dp_regs->aux_addr_19_16);
 652                         /*
 653                          * Set DisplayPort transaction and read
 654                          * If bit 3 is 1, DisplayPort transaction.
 655                          * If Bit 3 is 0, I2C transaction.
 656                          */
 657                         reg = AUX_LENGTH(cur_data_count) |
 658                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 659                         writel(reg, &dp_regs->aux_ch_ctl1);
 660
 661                         /* Start AUX transaction */
 662                         ret = exynos_dp_start_aux_transaction(dp_regs);
 663                         if (ret != EXYNOS_DP_SUCCESS) {
 664                                 if (retry_cnt == 0) {
 665                                         printf("DP Aux Transaction failed\n");
 666                                         return ret;
 667                                 }
 668                                 retry_cnt--;
 669                         } else
 670                                 break;
 671                 }
 672
 673                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 674                                 cur_data_idx++) {
 675                         reg = readl((unsigned int)&dp_regs->buf_data0 +
 676                                         4 * cur_data_idx);
 677                         data[start_offset + cur_data_idx] = (unsigned char)reg;
 678                 }
 679
 680                 start_offset += cur_data_count;
 681         }
 682
 683         return ret;
 684 }
 685
 686 int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
 687                                 unsigned int device_addr, unsigned int reg_addr)
 688 {
 689         unsigned int reg;
 690         int retval;
 691
 692         /* Set EDID device address */
 693         reg = device_addr;
 694         writel(reg, &dp_regs->aux_addr_7_0);
 695         writel(0x0, &dp_regs->aux_addr_15_8);
 696         writel(0x0, &dp_regs->aux_addr_19_16);
 697
 698         /* Set offset from base address of EDID device */
 699         writel(reg_addr, &dp_regs->buf_data0);
 700
 701         /*
 702          * Set I2C transaction and write address
 703          * If bit 3 is 1, DisplayPort transaction.
 704          * If Bit 3 is 0, I2C transaction.
 705          */
 706         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 707                 AUX_TX_COMM_WRITE;
 708         writel(reg, &dp_regs->aux_ch_ctl1);
 709
 710         /* Start AUX transaction */
 711         retval = exynos_dp_start_aux_transaction(dp_regs);
 712         if (retval != 0)
 713                 printf("%s: DP Aux Transaction fail!\n", __func__);
 714
 715         return retval;
 716 }
 717
 718 int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
 719                                  unsigned int device_addr,
 720                                  unsigned int reg_addr, unsigned int *data)
 721 {
 722         unsigned int reg;
 723         int i;
 724         int retval;
 725
 726         for (i = 0; i < 10; i++) {
 727                 /* Clear AUX CH data buffer */
 728                 reg = BUF_CLR;
 729                 writel(reg, &dp_regs->buffer_data_ctl);
 730
 731                 /* Select EDID device */
 732                 retval = exynos_dp_select_i2c_device(dp_regs, device_addr,
 733                                                      reg_addr);
 734                 if (retval != 0) {
 735                         printf("DP Select EDID device fail. retry !\n");
 736                         continue;
 737                 }
 738
 739                 /*
 740                  * Set I2C transaction and read data
 741                  * If bit 3 is 1, DisplayPort transaction.
 742                  * If Bit 3 is 0, I2C transaction.
 743                  */
 744                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 745                         AUX_TX_COMM_READ;
 746                 writel(reg, &dp_regs->aux_ch_ctl1);
 747
 748                 /* Start AUX transaction */
 749                 retval = exynos_dp_start_aux_transaction(dp_regs);
 750                 if (retval != EXYNOS_DP_SUCCESS)
 751                         printf("%s: DP Aux Transaction fail!\n", __func__);
 752         }
 753
 754         /* Read data */
 755         if (retval == 0)
 756                 *data = readl(&dp_regs->buf_data0);
 757
 758         return retval;
 759 }
 760
 761 int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
 762                                   unsigned int device_addr,
 763                                   unsigned int reg_addr, unsigned int count,
 764                                   unsigned char edid[])
 765 {
 766         unsigned int reg;
 767         unsigned int i, j;
 768         unsigned int cur_data_idx;
 769         unsigned int defer = 0;
 770         int retval = 0;
 771
 772         for (i = 0; i < count; i += 16) { /* use 16 burst */
 773                 for (j = 0; j < 100; j++) {
 774                         /* Clear AUX CH data buffer */
 775                         reg = BUF_CLR;
 776                         writel(reg, &dp_regs->buffer_data_ctl);
 777
 778                         /* Set normal AUX CH command */
 779                         reg = readl(&dp_regs->aux_ch_ctl2);
 780                         reg &= ~ADDR_ONLY;
 781                         writel(reg, &dp_regs->aux_ch_ctl2);
 782
 783                         /*
 784                          * If Rx sends defer, Tx sends only reads
 785                          * request without sending addres
 786                          */
 787                         if (!defer)
 788                                 retval = exynos_dp_select_i2c_device(
 789                                         dp_regs, device_addr, reg_addr + i);
 790                         else
 791                                 defer = 0;
 792
 793                         if (retval == EXYNOS_DP_SUCCESS) {
 794                                 /*
 795                                  * Set I2C transaction and write data
 796                                  * If bit 3 is 1, DisplayPort transaction.
 797                                  * If Bit 3 is 0, I2C transaction.
 798                                  */
 799                                 reg = AUX_LENGTH(16) |
 800                                         AUX_TX_COMM_I2C_TRANSACTION |
 801                                         AUX_TX_COMM_READ;
 802                                 writel(reg, &dp_regs->aux_ch_ctl1);
 803
 804                                 /* Start AUX transaction */
 805                                 retval = exynos_dp_start_aux_transaction(
 806                                                         dp_regs);
 807                                 if (retval == 0)
 808                                         break;
 809                                 else
 810                                         printf("DP Aux Transaction fail!\n");
 811                         }
 812                         /* Check if Rx sends defer */
 813                         reg = readl(&dp_regs->aux_rx_comm);
 814                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 815                                 reg == AUX_RX_COMM_I2C_DEFER) {
 816                                 printf("DP Defer: %d\n", reg);
 817                                 defer = 1;
 818                         }
 819                 }
 820
 821                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 822                         reg = readl((unsigned int)&dp_regs->buf_data0
 823                                                  + 4 * cur_data_idx);
 824                         edid[i + cur_data_idx] = (unsigned char)reg;
 825                 }
 826         }
 827
 828         return retval;
 829 }
 830
 831 void exynos_dp_reset_macro(struct exynos_dp *dp_regs)
 832 {
 833         unsigned int reg;
 834
 835         reg = readl(&dp_regs->phy_test);
 836         reg |= MACRO_RST;
 837         writel(reg, &dp_regs->phy_test);
 838
 839         /* 10 us is the minimum Macro reset time. */
 840         mdelay(1);
 841
 842         reg &= ~MACRO_RST;
 843         writel(reg, &dp_regs->phy_test);
 844 }
 845
 846 void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
 847                                   unsigned char bwtype)
 848 {
 849         unsigned int reg;
 850
 851         reg = (unsigned int)bwtype;
 852
 853          /* Set bandwidth to 2.7G or 1.62G */
 854         if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
 855                 writel(reg, &dp_regs->link_bw_set);
 856 }
 857
 858 unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs)
 859 {
 860         unsigned char ret;
 861         unsigned int reg;
 862
 863         reg = readl(&dp_regs->link_bw_set);
 864         ret = (unsigned char)reg;
 865
 866         return ret;
 867 }
 868
 869 void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count)
 870 {
 871         unsigned int reg;
 872
 873         reg = (unsigned int)count;
 874
 875         if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
 876                         (count == DP_LANE_CNT_4))
 877                 writel(reg, &dp_regs->lane_count_set);
 878 }
 879
 880 unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs)
 881 {
 882         return readl(&dp_regs->lane_count_set);
 883 }
 884
 885 unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
 886                                                unsigned char lanecnt)
 887 {
 888         unsigned int reg_list[DP_LANE_CNT_4] = {
 889                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 890                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 891                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 892                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 893         };
 894
 895         return readl(reg_list[lanecnt]);
 896 }
 897
 898 void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
 899                                       unsigned char request_val,
 900                                       unsigned char lanecnt)
 901 {
 902         unsigned int reg_list[DP_LANE_CNT_4] = {
 903                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 904                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 905                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 906                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 907         };
 908
 909         writel(request_val, reg_list[lanecnt]);
 910 }
 911
 912 void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
 913                                      unsigned int level, unsigned char lanecnt)
 914 {
 915         unsigned char i;
 916         unsigned int reg;
 917         unsigned int reg_list[DP_LANE_CNT_4] = {
 918                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 919                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 920                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 921                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 922         };
 923         unsigned int reg_shift[DP_LANE_CNT_4] = {
 924                 PRE_EMPHASIS_SET_0_SHIFT,
 925                 PRE_EMPHASIS_SET_1_SHIFT,
 926                 PRE_EMPHASIS_SET_2_SHIFT,
 927                 PRE_EMPHASIS_SET_3_SHIFT
 928         };
 929
 930         for (i = 0; i < lanecnt; i++) {
 931                 reg = level << reg_shift[i];
 932                 writel(reg, reg_list[i]);
 933         }
 934 }
 935
 936 void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
 937                                     unsigned int pattern)
 938 {
 939         unsigned int reg = 0;
 940
 941         switch (pattern) {
 942         case PRBS7:
 943                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 944                 break;
 945         case D10_2:
 946                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 947                 break;
 948         case TRAINING_PTN1:
 949                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 950                 break;
 951         case TRAINING_PTN2:
 952                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 953                 break;
 954         case DP_NONE:
 955                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
 956                         SW_TRAINING_PATTERN_SET_NORMAL;
 957                 break;
 958         default:
 959                 break;
 960         }
 961
 962         writel(reg, &dp_regs->training_ptn_set);
 963 }
 964
 965 void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
 966                                     unsigned char enable)
 967 {
 968         unsigned int reg;
 969
 970         reg = readl(&dp_regs->sys_ctl4);
 971         reg &= ~ENHANCED;
 972
 973         if (enable)
 974                 reg |= ENHANCED;
 975
 976         writel(reg, &dp_regs->sys_ctl4);
 977 }
 978
 979 void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, unsigned int enable)
 980 {
 981         unsigned int reg;
 982
 983         reg = readl(&dp_regs->training_ptn_set);
 984         reg &= ~(SCRAMBLING_DISABLE);
 985
 986         if (!enable)
 987                 reg |= SCRAMBLING_DISABLE;
 988
 989         writel(reg, &dp_regs->training_ptn_set);
 990 }
 991
 992 int exynos_dp_init_video(struct exynos_dp *dp_regs)
 993 {
 994         unsigned int reg;
 995
 996         /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
 997         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
 998         writel(reg, &dp_regs->common_int_sta1);
 999
1000         /* I_STRM__CLK detect : DE_CTL : Auto detect */
1001         reg &= ~DET_CTRL;
1002         writel(reg, &dp_regs->sys_ctl1);
1003
1004         return 0;
1005 }
1006
1007 void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
1008                                        struct edp_video_info *video_info)
1009 {
1010         unsigned int reg;
1011
1012         /* Video Slave mode setting */
1013         reg = readl(&dp_regs->func_en1);
1014         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1015         reg |= MASTER_VID_FUNC_EN_N;
1016         writel(reg, &dp_regs->func_en1);
1017
1018         /* Configure Interlaced for slave mode video */
1019         reg = readl(&dp_regs->video_ctl10);
1020         reg &= ~INTERACE_SCAN_CFG;
1021         reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
1022         writel(reg, &dp_regs->video_ctl10);
1023
1024         /* Configure V sync polarity for slave mode video */
1025         reg = readl(&dp_regs->video_ctl10);
1026         reg &= ~VSYNC_POLARITY_CFG;
1027         reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
1028         writel(reg, &dp_regs->video_ctl10);
1029
1030         /* Configure H sync polarity for slave mode video */
1031         reg = readl(&dp_regs->video_ctl10);
1032         reg &= ~HSYNC_POLARITY_CFG;
1033         reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1034         writel(reg, &dp_regs->video_ctl10);
1035
1036         /* Set video mode to slave mode */
1037         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1038         writel(reg, &dp_regs->soc_general_ctl);
1039 }
1040
1041 void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
1042                                       struct edp_video_info *video_info)
1043 {
1044         unsigned int reg;
1045
1046         /* Configure the input color depth, color space, dynamic range */
1047         reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1048                 (video_info->color_depth << IN_BPC_SHIFT) |
1049                 (video_info->color_space << IN_COLOR_F_SHIFT);
1050         writel(reg, &dp_regs->video_ctl2);
1051
1052         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1053         reg = readl(&dp_regs->video_ctl3);
1054         reg &= ~IN_YC_COEFFI_MASK;
1055         if (video_info->ycbcr_coeff)
1056                 reg |= IN_YC_COEFFI_ITU709;
1057         else
1058                 reg |= IN_YC_COEFFI_ITU601;
1059         writel(reg, &dp_regs->video_ctl3);
1060 }
1061
1062 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
1063                                 struct exynos_dp_priv *priv)
1064 {
1065         unsigned int reg;
1066         unsigned int bist_type = 0;
1067         struct edp_video_info video_info = priv->video_info;
1068
1069         /* For master mode, you don't need to set the video format */
1070         if (video_info.master_mode == 0) {
1071                 writel(TOTAL_LINE_CFG_L(priv->disp_info.v_total),
1072                        &dp_regs->total_ln_cfg_l);
1073                 writel(TOTAL_LINE_CFG_H(priv->disp_info.v_total),
1074                        &dp_regs->total_ln_cfg_h);
1075                 writel(ACTIVE_LINE_CFG_L(priv->disp_info.v_res),
1076                        &dp_regs->active_ln_cfg_l);
1077                 writel(ACTIVE_LINE_CFG_H(priv->disp_info.v_res),
1078                        &dp_regs->active_ln_cfg_h);
1079                 writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg);
1080                 writel(priv->disp_info.v_back_porch, &dp_regs->vbp_cfg);
1081                 writel(priv->disp_info.v_front_porch, &dp_regs->vfp_cfg);
1082
1083                 writel(TOTAL_PIXEL_CFG_L(priv->disp_info.h_total),
1084                        &dp_regs->total_pix_cfg_l);
1085                 writel(TOTAL_PIXEL_CFG_H(priv->disp_info.h_total),
1086                        &dp_regs->total_pix_cfg_h);
1087                 writel(ACTIVE_PIXEL_CFG_L(priv->disp_info.h_res),
1088                        &dp_regs->active_pix_cfg_l);
1089                 writel(ACTIVE_PIXEL_CFG_H(priv->disp_info.h_res),
1090                        &dp_regs->active_pix_cfg_h);
1091                 writel(H_F_PORCH_CFG_L(priv->disp_info.h_front_porch),
1092                        &dp_regs->hfp_cfg_l);
1093                 writel(H_F_PORCH_CFG_H(priv->disp_info.h_front_porch),
1094                        &dp_regs->hfp_cfg_h);
1095                 writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width),
1096                        &dp_regs->hsw_cfg_l);
1097                 writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width),
1098                        &dp_regs->hsw_cfg_h);
1099                 writel(H_B_PORCH_CFG_L(priv->disp_info.h_back_porch),
1100                        &dp_regs->hbp_cfg_l);
1101                 writel(H_B_PORCH_CFG_H(priv->disp_info.h_back_porch),
1102                        &dp_regs->hbp_cfg_h);
1103
1104                 /*
1105                  * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
1106                  * HSYNC_P_CFG[0] properly
1107                  */
1108                 reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
1109                         video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
1110                         video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1111                 writel(reg, &dp_regs->video_ctl10);
1112         }
1113
1114         /* BIST color bar width set--set to each bar is 32 pixel width */
1115         switch (video_info.bist_pattern) {
1116         case COLORBAR_32:
1117                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1118                           BIST_TYPE_COLOR_BAR;
1119                 break;
1120         case COLORBAR_64:
1121                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1122                           BIST_TYPE_COLOR_BAR;
1123                 break;
1124         case WHITE_GRAY_BALCKBAR_32:
1125                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1126                           BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1127                 break;
1128         case WHITE_GRAY_BALCKBAR_64:
1129                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1130                           BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1131                 break;
1132         case MOBILE_WHITEBAR_32:
1133                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1134                           BIST_TYPE_MOBILE_WHITE_BAR;
1135                 break;
1136         case MOBILE_WHITEBAR_64:
1137                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1138                           BIST_TYPE_MOBILE_WHITE_BAR;
1139                 break;
1140         default:
1141                 return -1;
1142         }
1143
1144         reg = bist_type;
1145         writel(reg, &dp_regs->video_ctl4);
1146
1147         return 0;
1148 }
1149
1150 unsigned int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp *dp_regs)
1151 {
1152         unsigned int reg;
1153
1154         /* Update Video stream clk detect status */
1155         reg = readl(&dp_regs->sys_ctl1);
1156         writel(reg, &dp_regs->sys_ctl1);
1157
1158         reg = readl(&dp_regs->sys_ctl1);
1159
1160         if (!(reg & DET_STA)) {
1161                 debug("DP Input stream clock not detected.\n");
1162                 return -EIO;
1163         }
1164
1165         return EXYNOS_DP_SUCCESS;
1166 }
1167
1168 void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
1169                                unsigned int m_value, unsigned int n_value)
1170 {
1171         unsigned int reg;
1172
1173         if (type == REGISTER_M) {
1174                 reg = readl(&dp_regs->sys_ctl4);
1175                 reg |= FIX_M_VID;
1176                 writel(reg, &dp_regs->sys_ctl4);
1177                 reg = M_VID0_CFG(m_value);
1178                 writel(reg, &dp_regs->m_vid0);
1179                 reg = M_VID1_CFG(m_value);
1180                 writel(reg, &dp_regs->m_vid1);
1181                 reg = M_VID2_CFG(m_value);
1182                 writel(reg, &dp_regs->m_vid2);
1183
1184                 reg = N_VID0_CFG(n_value);
1185                 writel(reg, &dp_regs->n_vid0);
1186                 reg = N_VID1_CFG(n_value);
1187                 writel(reg, &dp_regs->n_vid1);
1188                 reg = N_VID2_CFG(n_value);
1189                 writel(reg, &dp_regs->n_vid2);
1190         } else  {
1191                 reg = readl(&dp_regs->sys_ctl4);
1192                 reg &= ~FIX_M_VID;
1193                 writel(reg, &dp_regs->sys_ctl4);
1194         }
1195 }
1196
1197 void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
1198                                      unsigned int type)
1199 {
1200         unsigned int reg;
1201
1202         reg = readl(&dp_regs->video_ctl10);
1203         reg &= ~FORMAT_SEL;
1204
1205         if (type != VIDEO_TIMING_FROM_CAPTURE)
1206                 reg |= FORMAT_SEL;
1207
1208         writel(reg, &dp_regs->video_ctl10);
1209 }
1210
1211 void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
1212                                    unsigned int enable)
1213 {
1214         unsigned int reg;
1215
1216         reg = readl(&dp_regs->soc_general_ctl);
1217         if (enable) {
1218                 reg &= ~VIDEO_MODE_MASK;
1219                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1220         } else {
1221                 reg &= ~VIDEO_MODE_MASK;
1222                 reg |= VIDEO_MODE_SLAVE_MODE;
1223         }
1224
1225         writel(reg, &dp_regs->soc_general_ctl);
1226 }
1227
1228 void exynos_dp_start_video(struct exynos_dp *dp_regs)
1229 {
1230         unsigned int reg;
1231
1232         /* Enable Video input and disable Mute */
1233         reg = readl(&dp_regs->video_ctl1);
1234         reg |= VIDEO_EN;
1235         writel(reg, &dp_regs->video_ctl1);
1236 }
1237
1238 unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs)
1239 {
1240         unsigned int reg;
1241
1242         /* Update STRM_VALID */
1243         reg = readl(&dp_regs->sys_ctl3);
1244         writel(reg, &dp_regs->sys_ctl3);
1245
1246         reg = readl(&dp_regs->sys_ctl3);
1247         if (!(reg & STRM_VALID))
1248                 return -EIO;
1249
1250         return EXYNOS_DP_SUCCESS;
1251 }