drivers/video/exynos/exynos_dp_lowlevel.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Samsung Electronics
   4  *
   5  * Author: Donghwa Lee <dh09.lee@samsung.com>
   6  */
   7
   8 #include <config.h>
   9 #include <common.h>
  10 #include <log.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <asm/arch/cpu.h>
  14 #include <asm/arch/dp_info.h>
  15 #include <asm/arch/dp.h>
  16 #include <fdtdec.h>
  17 #include <linux/libfdt.h>
  18 #include "exynos_dp_lowlevel.h"
  19
  20 /* Declare global data pointer */
  21 static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
  22                                          unsigned int enable)
  23 {
  24         unsigned int reg;
  25
  26         reg = readl(&dp_regs->video_ctl1);
  27         reg &= ~VIDEO_EN_MASK;
  28
  29         /* enable video input */
  30         if (enable)
  31                 reg |= VIDEO_EN_MASK;
  32
  33         writel(reg, &dp_regs->video_ctl1);
  34
  35         return;
  36 }
  37
  38 void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, unsigned int enable)
  39 {
  40         /* enable video bist */
  41         unsigned int reg;
  42
  43         reg = readl(&dp_regs->video_ctl4);
  44         reg &= ~VIDEO_BIST_MASK;
  45
  46         /* enable video bist */
  47         if (enable)
  48                 reg |= VIDEO_BIST_MASK;
  49
  50         writel(reg, &dp_regs->video_ctl4);
  51
  52         return;
  53 }
  54
  55 void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, unsigned int enable)
  56 {
  57         unsigned int reg;
  58
  59         reg = readl(&dp_regs->video_ctl1);
  60         reg &= ~(VIDEO_MUTE_MASK);
  61         if (enable)
  62                 reg |= VIDEO_MUTE_MASK;
  63
  64         writel(reg, &dp_regs->video_ctl1);
  65
  66         return;
  67 }
  68
  69
  70 static void exynos_dp_init_analog_param(struct exynos_dp *dp_regs)
  71 {
  72         unsigned int reg;
  73
  74         /*
  75          * Set termination
  76          * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
  77          * 24M Phy clock, TX digital logic power is 100:1.0625V
  78          */
  79         reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
  80                 SWING_A_30PER_G_NORMAL;
  81         writel(reg, &dp_regs->analog_ctl1);
  82
  83         reg = SEL_24M | TX_DVDD_BIT_1_0625V;
  84         writel(reg, &dp_regs->analog_ctl2);
  85
  86         /*
  87          * Set power source for internal clk driver to 1.0625v.
  88          * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
  89          * Set VCO range of PLL +- 0uA
  90          */
  91         reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
  92         writel(reg, &dp_regs->analog_ctl3);
  93
  94         /*
  95          * Set AUX TX terminal resistor to 102 ohm
  96          * Set AUX channel amplitude control
  97          */
  98         reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
  99         writel(reg, &dp_regs->pll_filter_ctl1);
 100
 101         /*
 102          * PLL loop filter bandwidth
 103          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 104          * PLL digital power select: 1.2500V
 105          */
 106         reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
 107
 108         writel(reg, &dp_regs->amp_tuning_ctl);
 109
 110         /*
 111          * PLL loop filter bandwidth
 112          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 113          * PLL digital power select: 1.1250V
 114          */
 115         reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
 116         writel(reg, &dp_regs->pll_ctl);
 117 }
 118
 119 static void exynos_dp_init_interrupt(struct exynos_dp *dp_regs)
 120 {
 121         /* Set interrupt registers to initial states */
 122
 123         /*
 124          * Disable interrupt
 125          * INT pin assertion polarity. It must be configured
 126          * correctly according to ICU setting.
 127          * 1 = assert high, 0 = assert low
 128          */
 129         writel(INT_POL, &dp_regs->int_ctl);
 130
 131         /* Clear pending registers */
 132         writel(0xff, &dp_regs->common_int_sta1);
 133         writel(0xff, &dp_regs->common_int_sta2);
 134         writel(0xff, &dp_regs->common_int_sta3);
 135         writel(0xff, &dp_regs->common_int_sta4);
 136         writel(0xff, &dp_regs->int_sta);
 137
 138         /* 0:mask,1: unmask */
 139         writel(0x00, &dp_regs->int_sta_mask1);
 140         writel(0x00, &dp_regs->int_sta_mask2);
 141         writel(0x00, &dp_regs->int_sta_mask3);
 142         writel(0x00, &dp_regs->int_sta_mask4);
 143         writel(0x00, &dp_regs->int_sta_mask);
 144 }
 145
 146 void exynos_dp_reset(struct exynos_dp *dp_regs)
 147 {
 148         unsigned int reg_func_1;
 149
 150         /* dp tx sw reset */
 151         writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
 152
 153         exynos_dp_enable_video_input(dp_regs, DP_DISABLE);
 154         exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
 155         exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
 156
 157         /* software reset */
 158         reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 159                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 160                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 161
 162         writel(reg_func_1, &dp_regs->func_en1);
 163         writel(reg_func_1, &dp_regs->func_en2);
 164
 165         mdelay(1);
 166
 167         exynos_dp_init_analog_param(dp_regs);
 168         exynos_dp_init_interrupt(dp_regs);
 169
 170         return;
 171 }
 172
 173 void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable)
 174 {
 175         unsigned int reg;
 176
 177         reg = readl(&dp_regs->func_en1);
 178         reg &= ~(SW_FUNC_EN_N);
 179
 180         if (!enable)
 181                 reg |= SW_FUNC_EN_N;
 182
 183         writel(reg, &dp_regs->func_en1);
 184
 185         return;
 186 }
 187
 188 unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
 189                                              unsigned int block, u32 enable)
 190 {
 191         unsigned int reg;
 192
 193         reg = readl(&dp_regs->phy_pd);
 194         switch (block) {
 195         case AUX_BLOCK:
 196                 reg &= ~(AUX_PD);
 197                 if (enable)
 198                         reg |= AUX_PD;
 199                 break;
 200         case CH0_BLOCK:
 201                 reg &= ~(CH0_PD);
 202                 if (enable)
 203                         reg |= CH0_PD;
 204                 break;
 205         case CH1_BLOCK:
 206                 reg &= ~(CH1_PD);
 207                 if (enable)
 208                         reg |= CH1_PD;
 209                 break;
 210         case CH2_BLOCK:
 211                 reg &= ~(CH2_PD);
 212                 if (enable)
 213                         reg |= CH2_PD;
 214                 break;
 215         case CH3_BLOCK:
 216                 reg &= ~(CH3_PD);
 217                 if (enable)
 218                         reg |= CH3_PD;
 219                 break;
 220         case ANALOG_TOTAL:
 221                 reg &= ~PHY_PD;
 222                 if (enable)
 223                         reg |= PHY_PD;
 224                 break;
 225         case POWER_ALL:
 226                 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
 227                         CH3_PD);
 228                 if (enable)
 229                         reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
 230                                 CH2_PD | CH3_PD);
 231                 break;
 232         default:
 233                 printf("DP undefined block number : %d\n",  block);
 234                 return -1;
 235         }
 236
 237         writel(reg, &dp_regs->phy_pd);
 238
 239         return 0;
 240 }
 241
 242 unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs)
 243 {
 244         unsigned int reg;
 245
 246         reg = readl(&dp_regs->debug_ctl);
 247
 248         if (reg & PLL_LOCK)
 249                 return PLL_LOCKED;
 250         else
 251                 return PLL_UNLOCKED;
 252 }
 253
 254 static void exynos_dp_set_pll_power(struct exynos_dp *dp_regs,
 255                                     unsigned int enable)
 256 {
 257         unsigned int reg;
 258
 259         reg = readl(&dp_regs->pll_ctl);
 260         reg &= ~(DP_PLL_PD);
 261
 262         if (!enable)
 263                 reg |= DP_PLL_PD;
 264
 265         writel(reg, &dp_regs->pll_ctl);
 266 }
 267
 268 int exynos_dp_init_analog_func(struct exynos_dp *dp_regs)
 269 {
 270         int ret = EXYNOS_DP_SUCCESS;
 271         unsigned int retry_cnt = 10;
 272         unsigned int reg;
 273
 274         /* Power On All Analog block */
 275         exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, DP_DISABLE);
 276
 277         reg = PLL_LOCK_CHG;
 278         writel(reg, &dp_regs->common_int_sta1);
 279
 280         reg = readl(&dp_regs->debug_ctl);
 281         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 282         writel(reg, &dp_regs->debug_ctl);
 283
 284         /* Assert DP PLL Reset */
 285         reg = readl(&dp_regs->pll_ctl);
 286         reg |= DP_PLL_RESET;
 287         writel(reg, &dp_regs->pll_ctl);
 288
 289         mdelay(1);
 290
 291         /* Deassert DP PLL Reset */
 292         reg = readl(&dp_regs->pll_ctl);
 293         reg &= ~(DP_PLL_RESET);
 294         writel(reg, &dp_regs->pll_ctl);
 295
 296         exynos_dp_set_pll_power(dp_regs, DP_ENABLE);
 297
 298         while (exynos_dp_get_pll_lock_status(dp_regs) == PLL_UNLOCKED) {
 299                 mdelay(1);
 300                 retry_cnt--;
 301                 if (retry_cnt == 0) {
 302                         printf("DP dp's pll lock failed : retry : %d\n",
 303                                         retry_cnt);
 304                         return -EINVAL;
 305                 }
 306         }
 307
 308         debug("dp's pll lock success(%d)\n", retry_cnt);
 309
 310         /* Enable Serdes FIFO function and Link symbol clock domain module */
 311         reg = readl(&dp_regs->func_en2);
 312         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 313                 | AUX_FUNC_EN_N);
 314         writel(reg, &dp_regs->func_en2);
 315
 316         return ret;
 317 }
 318
 319 void exynos_dp_init_hpd(struct exynos_dp *dp_regs)
 320 {
 321         unsigned int reg;
 322
 323         /* Clear interrupts related to Hot Plug Detect */
 324         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 325         writel(reg, &dp_regs->common_int_sta4);
 326
 327         reg = INT_HPD;
 328         writel(reg, &dp_regs->int_sta);
 329
 330         reg = readl(&dp_regs->sys_ctl3);
 331         reg &= ~(F_HPD | HPD_CTRL);
 332         writel(reg, &dp_regs->sys_ctl3);
 333
 334         return;
 335 }
 336
 337 static inline void exynos_dp_reset_aux(struct exynos_dp *dp_regs)
 338 {
 339         unsigned int reg;
 340
 341         /* Disable AUX channel module */
 342         reg = readl(&dp_regs->func_en2);
 343         reg |= AUX_FUNC_EN_N;
 344         writel(reg, &dp_regs->func_en2);
 345
 346         return;
 347 }
 348
 349 void exynos_dp_init_aux(struct exynos_dp *dp_regs)
 350 {
 351         unsigned int reg;
 352
 353         /* Clear interrupts related to AUX channel */
 354         reg = RPLY_RECEIV | AUX_ERR;
 355         writel(reg, &dp_regs->int_sta);
 356
 357         exynos_dp_reset_aux(dp_regs);
 358
 359         /* Disable AUX transaction H/W retry */
 360         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
 361                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 362         writel(reg, &dp_regs->aux_hw_retry_ctl);
 363
 364         /* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
 365         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 366         writel(reg, &dp_regs->aux_ch_defer_ctl);
 367
 368         /* Enable AUX channel module */
 369         reg = readl(&dp_regs->func_en2);
 370         reg &= ~AUX_FUNC_EN_N;
 371         writel(reg, &dp_regs->func_en2);
 372
 373         return;
 374 }
 375
 376 void exynos_dp_config_interrupt(struct exynos_dp *dp_regs)
 377 {
 378         unsigned int reg;
 379
 380         /* 0: mask, 1: unmask */
 381         reg = COMMON_INT_MASK_1;
 382         writel(reg, &dp_regs->common_int_mask1);
 383
 384         reg = COMMON_INT_MASK_2;
 385         writel(reg, &dp_regs->common_int_mask2);
 386
 387         reg = COMMON_INT_MASK_3;
 388         writel(reg, &dp_regs->common_int_mask3);
 389
 390         reg = COMMON_INT_MASK_4;
 391         writel(reg, &dp_regs->common_int_mask4);
 392
 393         reg = INT_STA_MASK;
 394         writel(reg, &dp_regs->int_sta_mask);
 395
 396         return;
 397 }
 398
 399 unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs)
 400 {
 401         unsigned int reg;
 402
 403         reg = readl(&dp_regs->sys_ctl3);
 404         if (reg & HPD_STATUS)
 405                 return 0;
 406
 407         return -1;
 408 }
 409
 410 unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs)
 411 {
 412         int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
 413
 414         mdelay(2);
 415
 416         while (exynos_dp_get_plug_in_status(dp_regs) != 0) {
 417                 if (timeout_loop == 0)
 418                         return -EINVAL;
 419                 mdelay(10);
 420                 timeout_loop--;
 421         }
 422
 423         return EXYNOS_DP_SUCCESS;
 424 }
 425
 426 unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs)
 427 {
 428         unsigned int reg;
 429         unsigned int ret = 0;
 430         unsigned int retry_cnt;
 431
 432         /* Enable AUX CH operation */
 433         reg = readl(&dp_regs->aux_ch_ctl2);
 434         reg |= AUX_EN;
 435         writel(reg, &dp_regs->aux_ch_ctl2);
 436
 437         retry_cnt = 10;
 438         while (retry_cnt) {
 439                 reg = readl(&dp_regs->int_sta);
 440                 if (!(reg & RPLY_RECEIV)) {
 441                         if (retry_cnt == 0) {
 442                                 printf("DP Reply Timeout!!\n");
 443                                 ret = -EAGAIN;
 444                                 return ret;
 445                         }
 446                         mdelay(1);
 447                         retry_cnt--;
 448                 } else
 449                         break;
 450         }
 451
 452         /* Clear interrupt source for AUX CH command reply */
 453         writel(reg, &dp_regs->int_sta);
 454
 455         /* Clear interrupt source for AUX CH access error */
 456         reg = readl(&dp_regs->int_sta);
 457         if (reg & AUX_ERR) {
 458                 printf("DP Aux Access Error\n");
 459                 writel(AUX_ERR, &dp_regs->int_sta);
 460                 ret = -EAGAIN;
 461                 return ret;
 462         }
 463
 464         /* Check AUX CH error access status */
 465         reg = readl(&dp_regs->aux_ch_sta);
 466         if ((reg & AUX_STATUS_MASK) != 0) {
 467                 debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
 468                 ret = -EAGAIN;
 469                 return ret;
 470         }
 471
 472         return EXYNOS_DP_SUCCESS;
 473 }
 474
 475 unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
 476                                           unsigned int reg_addr,
 477                                           unsigned char data)
 478 {
 479         unsigned int reg, ret;
 480
 481         /* Clear AUX CH data buffer */
 482         reg = BUF_CLR;
 483         writel(reg, &dp_regs->buffer_data_ctl);
 484
 485         /* Select DPCD device address */
 486         reg = AUX_ADDR_7_0(reg_addr);
 487         writel(reg, &dp_regs->aux_addr_7_0);
 488         reg = AUX_ADDR_15_8(reg_addr);
 489         writel(reg, &dp_regs->aux_addr_15_8);
 490         reg = AUX_ADDR_19_16(reg_addr);
 491         writel(reg, &dp_regs->aux_addr_19_16);
 492
 493         /* Write data buffer */
 494         reg = (unsigned int)data;
 495         writel(reg, &dp_regs->buf_data0);
 496
 497         /*
 498          * Set DisplayPort transaction and write 1 byte
 499          * If bit 3 is 1, DisplayPort transaction.
 500          * If Bit 3 is 0, I2C transaction.
 501          */
 502         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 503         writel(reg, &dp_regs->aux_ch_ctl1);
 504
 505         /* Start AUX transaction */
 506         ret = exynos_dp_start_aux_transaction(dp_regs);
 507         if (ret != EXYNOS_DP_SUCCESS) {
 508                 printf("DP Aux transaction failed\n");
 509                 return ret;
 510         }
 511
 512         return ret;
 513 }
 514
 515 unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
 516                                            unsigned int reg_addr,
 517                                            unsigned char *data)
 518 {
 519         unsigned int reg;
 520         int retval;
 521
 522         /* Clear AUX CH data buffer */
 523         reg = BUF_CLR;
 524         writel(reg, &dp_regs->buffer_data_ctl);
 525
 526         /* Select DPCD device address */
 527         reg = AUX_ADDR_7_0(reg_addr);
 528         writel(reg, &dp_regs->aux_addr_7_0);
 529         reg = AUX_ADDR_15_8(reg_addr);
 530         writel(reg, &dp_regs->aux_addr_15_8);
 531         reg = AUX_ADDR_19_16(reg_addr);
 532         writel(reg, &dp_regs->aux_addr_19_16);
 533
 534         /*
 535          * Set DisplayPort transaction and read 1 byte
 536          * If bit 3 is 1, DisplayPort transaction.
 537          * If Bit 3 is 0, I2C transaction.
 538          */
 539         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 540         writel(reg, &dp_regs->aux_ch_ctl1);
 541
 542         /* Start AUX transaction */
 543         retval = exynos_dp_start_aux_transaction(dp_regs);
 544         if (!retval)
 545                 debug("DP Aux Transaction fail!\n");
 546
 547         /* Read data buffer */
 548         reg = readl(&dp_regs->buf_data0);
 549         *data = (unsigned char)(reg & 0xff);
 550
 551         return retval;
 552 }
 553
 554 unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
 555                                            unsigned int reg_addr,
 556                                            unsigned int count,
 557                                            unsigned char data[])
 558 {
 559         unsigned int reg;
 560         unsigned int start_offset;
 561         unsigned int cur_data_count;
 562         unsigned int cur_data_idx;
 563         unsigned int retry_cnt;
 564         unsigned int ret = 0;
 565
 566         /* Clear AUX CH data buffer */
 567         reg = BUF_CLR;
 568         writel(reg, &dp_regs->buffer_data_ctl);
 569
 570         start_offset = 0;
 571         while (start_offset < count) {
 572                 /* Buffer size of AUX CH is 16 * 4bytes */
 573                 if ((count - start_offset) > 16)
 574                         cur_data_count = 16;
 575                 else
 576                         cur_data_count = count - start_offset;
 577
 578                 retry_cnt = 5;
 579                 while (retry_cnt) {
 580                         /* Select DPCD device address */
 581                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 582                         writel(reg, &dp_regs->aux_addr_7_0);
 583                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 584                         writel(reg, &dp_regs->aux_addr_15_8);
 585                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 586                         writel(reg, &dp_regs->aux_addr_19_16);
 587
 588                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 589                                         cur_data_idx++) {
 590                                 reg = data[start_offset + cur_data_idx];
 591                                 writel(reg, (unsigned int)&dp_regs->buf_data0 +
 592                                                 (4 * cur_data_idx));
 593                         }
 594                         /*
 595                         * Set DisplayPort transaction and write
 596                         * If bit 3 is 1, DisplayPort transaction.
 597                         * If Bit 3 is 0, I2C transaction.
 598                         */
 599                         reg = AUX_LENGTH(cur_data_count) |
 600                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 601                         writel(reg, &dp_regs->aux_ch_ctl1);
 602
 603                         /* Start AUX transaction */
 604                         ret = exynos_dp_start_aux_transaction(dp_regs);
 605                         if (ret != EXYNOS_DP_SUCCESS) {
 606                                 if (retry_cnt == 0) {
 607                                         printf("DP Aux Transaction failed\n");
 608                                         return ret;
 609                                 }
 610                                 retry_cnt--;
 611                         } else
 612                                 break;
 613                 }
 614                 start_offset += cur_data_count;
 615         }
 616
 617         return ret;
 618 }
 619
 620 unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
 621                                             unsigned int reg_addr,
 622                                             unsigned int count,
 623                                             unsigned char data[])
 624 {
 625         unsigned int reg;
 626         unsigned int start_offset;
 627         unsigned int cur_data_count;
 628         unsigned int cur_data_idx;
 629         unsigned int retry_cnt;
 630         unsigned int ret = 0;
 631
 632         /* Clear AUX CH data buffer */
 633         reg = BUF_CLR;
 634         writel(reg, &dp_regs->buffer_data_ctl);
 635
 636         start_offset = 0;
 637         while (start_offset < count) {
 638                 /* Buffer size of AUX CH is 16 * 4bytes */
 639                 if ((count - start_offset) > 16)
 640                         cur_data_count = 16;
 641                 else
 642                         cur_data_count = count - start_offset;
 643
 644                 retry_cnt = 5;
 645                 while (retry_cnt) {
 646                         /* Select DPCD device address */
 647                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 648                         writel(reg, &dp_regs->aux_addr_7_0);
 649                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 650                         writel(reg, &dp_regs->aux_addr_15_8);
 651                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 652                         writel(reg, &dp_regs->aux_addr_19_16);
 653                         /*
 654                          * Set DisplayPort transaction and read
 655                          * If bit 3 is 1, DisplayPort transaction.
 656                          * If Bit 3 is 0, I2C transaction.
 657                          */
 658                         reg = AUX_LENGTH(cur_data_count) |
 659                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 660                         writel(reg, &dp_regs->aux_ch_ctl1);
 661
 662                         /* Start AUX transaction */
 663                         ret = exynos_dp_start_aux_transaction(dp_regs);
 664                         if (ret != EXYNOS_DP_SUCCESS) {
 665                                 if (retry_cnt == 0) {
 666                                         printf("DP Aux Transaction failed\n");
 667                                         return ret;
 668                                 }
 669                                 retry_cnt--;
 670                         } else
 671                                 break;
 672                 }
 673
 674                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 675                                 cur_data_idx++) {
 676                         reg = readl((unsigned int)&dp_regs->buf_data0 +
 677                                         4 * cur_data_idx);
 678                         data[start_offset + cur_data_idx] = (unsigned char)reg;
 679                 }
 680
 681                 start_offset += cur_data_count;
 682         }
 683
 684         return ret;
 685 }
 686
 687 int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
 688                                 unsigned int device_addr, unsigned int reg_addr)
 689 {
 690         unsigned int reg;
 691         int retval;
 692
 693         /* Set EDID device address */
 694         reg = device_addr;
 695         writel(reg, &dp_regs->aux_addr_7_0);
 696         writel(0x0, &dp_regs->aux_addr_15_8);
 697         writel(0x0, &dp_regs->aux_addr_19_16);
 698
 699         /* Set offset from base address of EDID device */
 700         writel(reg_addr, &dp_regs->buf_data0);
 701
 702         /*
 703          * Set I2C transaction and write address
 704          * If bit 3 is 1, DisplayPort transaction.
 705          * If Bit 3 is 0, I2C transaction.
 706          */
 707         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 708                 AUX_TX_COMM_WRITE;
 709         writel(reg, &dp_regs->aux_ch_ctl1);
 710
 711         /* Start AUX transaction */
 712         retval = exynos_dp_start_aux_transaction(dp_regs);
 713         if (retval != 0)
 714                 printf("%s: DP Aux Transaction fail!\n", __func__);
 715
 716         return retval;
 717 }
 718
 719 int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
 720                                  unsigned int device_addr,
 721                                  unsigned int reg_addr, unsigned int *data)
 722 {
 723         unsigned int reg;
 724         int i;
 725         int retval;
 726
 727         for (i = 0; i < 10; i++) {
 728                 /* Clear AUX CH data buffer */
 729                 reg = BUF_CLR;
 730                 writel(reg, &dp_regs->buffer_data_ctl);
 731
 732                 /* Select EDID device */
 733                 retval = exynos_dp_select_i2c_device(dp_regs, device_addr,
 734                                                      reg_addr);
 735                 if (retval != 0) {
 736                         printf("DP Select EDID device fail. retry !\n");
 737                         continue;
 738                 }
 739
 740                 /*
 741                  * Set I2C transaction and read data
 742                  * If bit 3 is 1, DisplayPort transaction.
 743                  * If Bit 3 is 0, I2C transaction.
 744                  */
 745                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 746                         AUX_TX_COMM_READ;
 747                 writel(reg, &dp_regs->aux_ch_ctl1);
 748
 749                 /* Start AUX transaction */
 750                 retval = exynos_dp_start_aux_transaction(dp_regs);
 751                 if (retval != EXYNOS_DP_SUCCESS)
 752                         printf("%s: DP Aux Transaction fail!\n", __func__);
 753         }
 754
 755         /* Read data */
 756         if (retval == 0)
 757                 *data = readl(&dp_regs->buf_data0);
 758
 759         return retval;
 760 }
 761
 762 int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
 763                                   unsigned int device_addr,
 764                                   unsigned int reg_addr, unsigned int count,
 765                                   unsigned char edid[])
 766 {
 767         unsigned int reg;
 768         unsigned int i, j;
 769         unsigned int cur_data_idx;
 770         unsigned int defer = 0;
 771         int retval = 0;
 772
 773         for (i = 0; i < count; i += 16) { /* use 16 burst */
 774                 for (j = 0; j < 100; j++) {
 775                         /* Clear AUX CH data buffer */
 776                         reg = BUF_CLR;
 777                         writel(reg, &dp_regs->buffer_data_ctl);
 778
 779                         /* Set normal AUX CH command */
 780                         reg = readl(&dp_regs->aux_ch_ctl2);
 781                         reg &= ~ADDR_ONLY;
 782                         writel(reg, &dp_regs->aux_ch_ctl2);
 783
 784                         /*
 785                          * If Rx sends defer, Tx sends only reads
 786                          * request without sending addres
 787                          */
 788                         if (!defer)
 789                                 retval = exynos_dp_select_i2c_device(
 790                                         dp_regs, device_addr, reg_addr + i);
 791                         else
 792                                 defer = 0;
 793
 794                         if (retval == EXYNOS_DP_SUCCESS) {
 795                                 /*
 796                                  * Set I2C transaction and write data
 797                                  * If bit 3 is 1, DisplayPort transaction.
 798                                  * If Bit 3 is 0, I2C transaction.
 799                                  */
 800                                 reg = AUX_LENGTH(16) |
 801                                         AUX_TX_COMM_I2C_TRANSACTION |
 802                                         AUX_TX_COMM_READ;
 803                                 writel(reg, &dp_regs->aux_ch_ctl1);
 804
 805                                 /* Start AUX transaction */
 806                                 retval = exynos_dp_start_aux_transaction(
 807                                                         dp_regs);
 808                                 if (retval == 0)
 809                                         break;
 810                                 else
 811                                         printf("DP Aux Transaction fail!\n");
 812                         }
 813                         /* Check if Rx sends defer */
 814                         reg = readl(&dp_regs->aux_rx_comm);
 815                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 816                                 reg == AUX_RX_COMM_I2C_DEFER) {
 817                                 printf("DP Defer: %d\n", reg);
 818                                 defer = 1;
 819                         }
 820                 }
 821
 822                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 823                         reg = readl((unsigned int)&dp_regs->buf_data0
 824                                                  + 4 * cur_data_idx);
 825                         edid[i + cur_data_idx] = (unsigned char)reg;
 826                 }
 827         }
 828
 829         return retval;
 830 }
 831
 832 void exynos_dp_reset_macro(struct exynos_dp *dp_regs)
 833 {
 834         unsigned int reg;
 835
 836         reg = readl(&dp_regs->phy_test);
 837         reg |= MACRO_RST;
 838         writel(reg, &dp_regs->phy_test);
 839
 840         /* 10 us is the minimum Macro reset time. */
 841         mdelay(1);
 842
 843         reg &= ~MACRO_RST;
 844         writel(reg, &dp_regs->phy_test);
 845 }
 846
 847 void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
 848                                   unsigned char bwtype)
 849 {
 850         unsigned int reg;
 851
 852         reg = (unsigned int)bwtype;
 853
 854          /* Set bandwidth to 2.7G or 1.62G */
 855         if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
 856                 writel(reg, &dp_regs->link_bw_set);
 857 }
 858
 859 unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs)
 860 {
 861         unsigned char ret;
 862         unsigned int reg;
 863
 864         reg = readl(&dp_regs->link_bw_set);
 865         ret = (unsigned char)reg;
 866
 867         return ret;
 868 }
 869
 870 void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count)
 871 {
 872         unsigned int reg;
 873
 874         reg = (unsigned int)count;
 875
 876         if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
 877                         (count == DP_LANE_CNT_4))
 878                 writel(reg, &dp_regs->lane_count_set);
 879 }
 880
 881 unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs)
 882 {
 883         return readl(&dp_regs->lane_count_set);
 884 }
 885
 886 unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
 887                                                unsigned char lanecnt)
 888 {
 889         unsigned int reg_list[DP_LANE_CNT_4] = {
 890                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 891                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 892                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 893                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 894         };
 895
 896         return readl(reg_list[lanecnt]);
 897 }
 898
 899 void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
 900                                       unsigned char request_val,
 901                                       unsigned char lanecnt)
 902 {
 903         unsigned int reg_list[DP_LANE_CNT_4] = {
 904                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 905                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 906                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 907                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 908         };
 909
 910         writel(request_val, reg_list[lanecnt]);
 911 }
 912
 913 void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
 914                                      unsigned int level, unsigned char lanecnt)
 915 {
 916         unsigned char i;
 917         unsigned int reg;
 918         unsigned int reg_list[DP_LANE_CNT_4] = {
 919                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 920                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 921                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 922                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 923         };
 924         unsigned int reg_shift[DP_LANE_CNT_4] = {
 925                 PRE_EMPHASIS_SET_0_SHIFT,
 926                 PRE_EMPHASIS_SET_1_SHIFT,
 927                 PRE_EMPHASIS_SET_2_SHIFT,
 928                 PRE_EMPHASIS_SET_3_SHIFT
 929         };
 930
 931         for (i = 0; i < lanecnt; i++) {
 932                 reg = level << reg_shift[i];
 933                 writel(reg, reg_list[i]);
 934         }
 935 }
 936
 937 void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
 938                                     unsigned int pattern)
 939 {
 940         unsigned int reg = 0;
 941
 942         switch (pattern) {
 943         case PRBS7:
 944                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 945                 break;
 946         case D10_2:
 947                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 948                 break;
 949         case TRAINING_PTN1:
 950                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 951                 break;
 952         case TRAINING_PTN2:
 953                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 954                 break;
 955         case DP_NONE:
 956                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
 957                         SW_TRAINING_PATTERN_SET_NORMAL;
 958                 break;
 959         default:
 960                 break;
 961         }
 962
 963         writel(reg, &dp_regs->training_ptn_set);
 964 }
 965
 966 void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
 967                                     unsigned char enable)
 968 {
 969         unsigned int reg;
 970
 971         reg = readl(&dp_regs->sys_ctl4);
 972         reg &= ~ENHANCED;
 973
 974         if (enable)
 975                 reg |= ENHANCED;
 976
 977         writel(reg, &dp_regs->sys_ctl4);
 978 }
 979
 980 void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, unsigned int enable)
 981 {
 982         unsigned int reg;
 983
 984         reg = readl(&dp_regs->training_ptn_set);
 985         reg &= ~(SCRAMBLING_DISABLE);
 986
 987         if (!enable)
 988                 reg |= SCRAMBLING_DISABLE;
 989
 990         writel(reg, &dp_regs->training_ptn_set);
 991 }
 992
 993 int exynos_dp_init_video(struct exynos_dp *dp_regs)
 994 {
 995         unsigned int reg;
 996
 997         /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
 998         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
 999         writel(reg, &dp_regs->common_int_sta1);
1000
1001         /* I_STRM__CLK detect : DE_CTL : Auto detect */
1002         reg &= ~DET_CTRL;
1003         writel(reg, &dp_regs->sys_ctl1);
1004
1005         return 0;
1006 }
1007
1008 void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
1009                                        struct edp_video_info *video_info)
1010 {
1011         unsigned int reg;
1012
1013         /* Video Slave mode setting */
1014         reg = readl(&dp_regs->func_en1);
1015         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1016         reg |= MASTER_VID_FUNC_EN_N;
1017         writel(reg, &dp_regs->func_en1);
1018
1019         /* Configure Interlaced for slave mode video */
1020         reg = readl(&dp_regs->video_ctl10);
1021         reg &= ~INTERACE_SCAN_CFG;
1022         reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
1023         writel(reg, &dp_regs->video_ctl10);
1024
1025         /* Configure V sync polarity for slave mode video */
1026         reg = readl(&dp_regs->video_ctl10);
1027         reg &= ~VSYNC_POLARITY_CFG;
1028         reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
1029         writel(reg, &dp_regs->video_ctl10);
1030
1031         /* Configure H sync polarity for slave mode video */
1032         reg = readl(&dp_regs->video_ctl10);
1033         reg &= ~HSYNC_POLARITY_CFG;
1034         reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1035         writel(reg, &dp_regs->video_ctl10);
1036
1037         /* Set video mode to slave mode */
1038         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1039         writel(reg, &dp_regs->soc_general_ctl);
1040 }
1041
1042 void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
1043                                       struct edp_video_info *video_info)
1044 {
1045         unsigned int reg;
1046
1047         /* Configure the input color depth, color space, dynamic range */
1048         reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1049                 (video_info->color_depth << IN_BPC_SHIFT) |
1050                 (video_info->color_space << IN_COLOR_F_SHIFT);
1051         writel(reg, &dp_regs->video_ctl2);
1052
1053         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1054         reg = readl(&dp_regs->video_ctl3);
1055         reg &= ~IN_YC_COEFFI_MASK;
1056         if (video_info->ycbcr_coeff)
1057                 reg |= IN_YC_COEFFI_ITU709;
1058         else
1059                 reg |= IN_YC_COEFFI_ITU601;
1060         writel(reg, &dp_regs->video_ctl3);
1061 }
1062
1063 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
1064                                 struct exynos_dp_priv *priv)
1065 {
1066         unsigned int reg;
1067         unsigned int bist_type = 0;
1068         struct edp_video_info video_info = priv->video_info;
1069
1070         /* For master mode, you don't need to set the video format */
1071         if (video_info.master_mode == 0) {
1072                 writel(TOTAL_LINE_CFG_L(priv->disp_info.v_total),
1073                        &dp_regs->total_ln_cfg_l);
1074                 writel(TOTAL_LINE_CFG_H(priv->disp_info.v_total),
1075                        &dp_regs->total_ln_cfg_h);
1076                 writel(ACTIVE_LINE_CFG_L(priv->disp_info.v_res),
1077                        &dp_regs->active_ln_cfg_l);
1078                 writel(ACTIVE_LINE_CFG_H(priv->disp_info.v_res),
1079                        &dp_regs->active_ln_cfg_h);
1080                 writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg);
1081                 writel(priv->disp_info.v_back_porch, &dp_regs->vbp_cfg);
1082                 writel(priv->disp_info.v_front_porch, &dp_regs->vfp_cfg);
1083
1084                 writel(TOTAL_PIXEL_CFG_L(priv->disp_info.h_total),
1085                        &dp_regs->total_pix_cfg_l);
1086                 writel(TOTAL_PIXEL_CFG_H(priv->disp_info.h_total),
1087                        &dp_regs->total_pix_cfg_h);
1088                 writel(ACTIVE_PIXEL_CFG_L(priv->disp_info.h_res),
1089                        &dp_regs->active_pix_cfg_l);
1090                 writel(ACTIVE_PIXEL_CFG_H(priv->disp_info.h_res),
1091                        &dp_regs->active_pix_cfg_h);
1092                 writel(H_F_PORCH_CFG_L(priv->disp_info.h_front_porch),
1093                        &dp_regs->hfp_cfg_l);
1094                 writel(H_F_PORCH_CFG_H(priv->disp_info.h_front_porch),
1095                        &dp_regs->hfp_cfg_h);
1096                 writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width),
1097                        &dp_regs->hsw_cfg_l);
1098                 writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width),
1099                        &dp_regs->hsw_cfg_h);
1100                 writel(H_B_PORCH_CFG_L(priv->disp_info.h_back_porch),
1101                        &dp_regs->hbp_cfg_l);
1102                 writel(H_B_PORCH_CFG_H(priv->disp_info.h_back_porch),
1103                        &dp_regs->hbp_cfg_h);
1104
1105                 /*
1106                  * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
1107                  * HSYNC_P_CFG[0] properly
1108                  */
1109                 reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
1110                         video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
1111                         video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1112                 writel(reg, &dp_regs->video_ctl10);
1113         }
1114
1115         /* BIST color bar width set--set to each bar is 32 pixel width */
1116         switch (video_info.bist_pattern) {
1117         case COLORBAR_32:
1118                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1119                           BIST_TYPE_COLOR_BAR;
1120                 break;
1121         case COLORBAR_64:
1122                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1123                           BIST_TYPE_COLOR_BAR;
1124                 break;
1125         case WHITE_GRAY_BALCKBAR_32:
1126                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1127                           BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1128                 break;
1129         case WHITE_GRAY_BALCKBAR_64:
1130                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1131                           BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1132                 break;
1133         case MOBILE_WHITEBAR_32:
1134                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1135                           BIST_TYPE_MOBILE_WHITE_BAR;
1136                 break;
1137         case MOBILE_WHITEBAR_64:
1138                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1139                           BIST_TYPE_MOBILE_WHITE_BAR;
1140                 break;
1141         default:
1142                 return -1;
1143         }
1144
1145         reg = bist_type;
1146         writel(reg, &dp_regs->video_ctl4);
1147
1148         return 0;
1149 }
1150
1151 unsigned int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp *dp_regs)
1152 {
1153         unsigned int reg;
1154
1155         /* Update Video stream clk detect status */
1156         reg = readl(&dp_regs->sys_ctl1);
1157         writel(reg, &dp_regs->sys_ctl1);
1158
1159         reg = readl(&dp_regs->sys_ctl1);
1160
1161         if (!(reg & DET_STA)) {
1162                 debug("DP Input stream clock not detected.\n");
1163                 return -EIO;
1164         }
1165
1166         return EXYNOS_DP_SUCCESS;
1167 }
1168
1169 void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
1170                                unsigned int m_value, unsigned int n_value)
1171 {
1172         unsigned int reg;
1173
1174         if (type == REGISTER_M) {
1175                 reg = readl(&dp_regs->sys_ctl4);
1176                 reg |= FIX_M_VID;
1177                 writel(reg, &dp_regs->sys_ctl4);
1178                 reg = M_VID0_CFG(m_value);
1179                 writel(reg, &dp_regs->m_vid0);
1180                 reg = M_VID1_CFG(m_value);
1181                 writel(reg, &dp_regs->m_vid1);
1182                 reg = M_VID2_CFG(m_value);
1183                 writel(reg, &dp_regs->m_vid2);
1184
1185                 reg = N_VID0_CFG(n_value);
1186                 writel(reg, &dp_regs->n_vid0);
1187                 reg = N_VID1_CFG(n_value);
1188                 writel(reg, &dp_regs->n_vid1);
1189                 reg = N_VID2_CFG(n_value);
1190                 writel(reg, &dp_regs->n_vid2);
1191         } else  {
1192                 reg = readl(&dp_regs->sys_ctl4);
1193                 reg &= ~FIX_M_VID;
1194                 writel(reg, &dp_regs->sys_ctl4);
1195         }
1196 }
1197
1198 void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
1199                                      unsigned int type)
1200 {
1201         unsigned int reg;
1202
1203         reg = readl(&dp_regs->video_ctl10);
1204         reg &= ~FORMAT_SEL;
1205
1206         if (type != VIDEO_TIMING_FROM_CAPTURE)
1207                 reg |= FORMAT_SEL;
1208
1209         writel(reg, &dp_regs->video_ctl10);
1210 }
1211
1212 void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
1213                                    unsigned int enable)
1214 {
1215         unsigned int reg;
1216
1217         reg = readl(&dp_regs->soc_general_ctl);
1218         if (enable) {
1219                 reg &= ~VIDEO_MODE_MASK;
1220                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1221         } else {
1222                 reg &= ~VIDEO_MODE_MASK;
1223                 reg |= VIDEO_MODE_SLAVE_MODE;
1224         }
1225
1226         writel(reg, &dp_regs->soc_general_ctl);
1227 }
1228
1229 void exynos_dp_start_video(struct exynos_dp *dp_regs)
1230 {
1231         unsigned int reg;
1232
1233         /* Enable Video input and disable Mute */
1234         reg = readl(&dp_regs->video_ctl1);
1235         reg |= VIDEO_EN;
1236         writel(reg, &dp_regs->video_ctl1);
1237 }
1238
1239 unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs)
1240 {
1241         unsigned int reg;
1242
1243         /* Update STRM_VALID */
1244         reg = readl(&dp_regs->sys_ctl3);
1245         writel(reg, &dp_regs->sys_ctl3);
1246
1247         reg = readl(&dp_regs->sys_ctl3);
1248         if (!(reg & STRM_VALID))
1249                 return -EIO;
1250
1251         return EXYNOS_DP_SUCCESS;
1252 }