drivers/video/dw_mipi_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
   4  * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
   5  * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
   6  *            Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
   7  *
   8  * This generic Synopsys DesignWare MIPI DSI host driver is inspired from
   9  * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
  10  */
  11
  12 #include <common.h>
  13 #include <clk.h>
  14 #include <dsi_host.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <panel.h>
  18 #include <video.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/gpio.h>
  21 #include <dm/device-internal.h>
  22 #include <dm/device_compat.h>
  23 #include <linux/iopoll.h>
  24 #include <video_bridge.h>
  25
  26 #define HWVER_131                       0x31333100      /* IP version 1.31 */
  27
  28 #define DSI_VERSION                     0x00
  29 #define VERSION                         GENMASK(31, 8)
  30
  31 #define DSI_PWR_UP                      0x04
  32 #define RESET                           0
  33 #define POWERUP                         BIT(0)
  34
  35 #define DSI_CLKMGR_CFG                  0x08
  36 #define TO_CLK_DIVISION(div)            (((div) & 0xff) << 8)
  37 #define TX_ESC_CLK_DIVISION(div)        ((div) & 0xff)
  38
  39 #define DSI_DPI_VCID                    0x0c
  40 #define DPI_VCID(vcid)                  ((vcid) & 0x3)
  41
  42 #define DSI_DPI_COLOR_CODING            0x10
  43 #define LOOSELY18_EN                    BIT(8)
  44 #define DPI_COLOR_CODING_16BIT_1        0x0
  45 #define DPI_COLOR_CODING_16BIT_2        0x1
  46 #define DPI_COLOR_CODING_16BIT_3        0x2
  47 #define DPI_COLOR_CODING_18BIT_1        0x3
  48 #define DPI_COLOR_CODING_18BIT_2        0x4
  49 #define DPI_COLOR_CODING_24BIT          0x5
  50
  51 #define DSI_DPI_CFG_POL                 0x14
  52 #define COLORM_ACTIVE_LOW               BIT(4)
  53 #define SHUTD_ACTIVE_LOW                BIT(3)
  54 #define HSYNC_ACTIVE_LOW                BIT(2)
  55 #define VSYNC_ACTIVE_LOW                BIT(1)
  56 #define DATAEN_ACTIVE_LOW               BIT(0)
  57
  58 #define DSI_DPI_LP_CMD_TIM              0x18
  59 #define OUTVACT_LPCMD_TIME(p)           (((p) & 0xff) << 16)
  60 #define INVACT_LPCMD_TIME(p)            ((p) & 0xff)
  61
  62 #define DSI_DBI_VCID                    0x1c
  63 #define DSI_DBI_CFG                     0x20
  64 #define DSI_DBI_PARTITIONING_EN         0x24
  65 #define DSI_DBI_CMDSIZE                 0x28
  66
  67 #define DSI_PCKHDL_CFG                  0x2c
  68 #define CRC_RX_EN                       BIT(4)
  69 #define ECC_RX_EN                       BIT(3)
  70 #define BTA_EN                          BIT(2)
  71 #define EOTP_RX_EN                      BIT(1)
  72 #define EOTP_TX_EN                      BIT(0)
  73
  74 #define DSI_GEN_VCID                    0x30
  75
  76 #define DSI_MODE_CFG                    0x34
  77 #define ENABLE_VIDEO_MODE               0
  78 #define ENABLE_CMD_MODE                 BIT(0)
  79
  80 #define DSI_VID_MODE_CFG                0x38
  81 #define ENABLE_LOW_POWER                (0x3f << 8)
  82 #define ENABLE_LOW_POWER_MASK           (0x3f << 8)
  83 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES     0x0
  84 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS     0x1
  85 #define VID_MODE_TYPE_BURST                     0x2
  86 #define VID_MODE_TYPE_MASK                      0x3
  87
  88 #define DSI_VID_PKT_SIZE                0x3c
  89 #define VID_PKT_SIZE(p)                 ((p) & 0x3fff)
  90
  91 #define DSI_VID_NUM_CHUNKS              0x40
  92 #define VID_NUM_CHUNKS(c)               ((c) & 0x1fff)
  93
  94 #define DSI_VID_NULL_SIZE               0x44
  95 #define VID_NULL_SIZE(b)                ((b) & 0x1fff)
  96
  97 #define DSI_VID_HSA_TIME                0x48
  98 #define DSI_VID_HBP_TIME                0x4c
  99 #define DSI_VID_HLINE_TIME              0x50
 100 #define DSI_VID_VSA_LINES               0x54
 101 #define DSI_VID_VBP_LINES               0x58
 102 #define DSI_VID_VFP_LINES               0x5c
 103 #define DSI_VID_VACTIVE_LINES           0x60
 104 #define DSI_EDPI_CMD_SIZE               0x64
 105
 106 #define DSI_CMD_MODE_CFG                0x68
 107 #define MAX_RD_PKT_SIZE_LP              BIT(24)
 108 #define DCS_LW_TX_LP                    BIT(19)
 109 #define DCS_SR_0P_TX_LP                 BIT(18)
 110 #define DCS_SW_1P_TX_LP                 BIT(17)
 111 #define DCS_SW_0P_TX_LP                 BIT(16)
 112 #define GEN_LW_TX_LP                    BIT(14)
 113 #define GEN_SR_2P_TX_LP                 BIT(13)
 114 #define GEN_SR_1P_TX_LP                 BIT(12)
 115 #define GEN_SR_0P_TX_LP                 BIT(11)
 116 #define GEN_SW_2P_TX_LP                 BIT(10)
 117 #define GEN_SW_1P_TX_LP                 BIT(9)
 118 #define GEN_SW_0P_TX_LP                 BIT(8)
 119 #define ACK_RQST_EN                     BIT(1)
 120 #define TEAR_FX_EN                      BIT(0)
 121
 122 #define CMD_MODE_ALL_LP                 (MAX_RD_PKT_SIZE_LP | \
 123                                          DCS_LW_TX_LP | \
 124                                          DCS_SR_0P_TX_LP | \
 125                                          DCS_SW_1P_TX_LP | \
 126                                          DCS_SW_0P_TX_LP | \
 127                                          GEN_LW_TX_LP | \
 128                                          GEN_SR_2P_TX_LP | \
 129                                          GEN_SR_1P_TX_LP | \
 130                                          GEN_SR_0P_TX_LP | \
 131                                          GEN_SW_2P_TX_LP | \
 132                                          GEN_SW_1P_TX_LP | \
 133                                          GEN_SW_0P_TX_LP)
 134
 135 #define DSI_GEN_HDR                     0x6c
 136 #define DSI_GEN_PLD_DATA                0x70
 137
 138 #define DSI_CMD_PKT_STATUS              0x74
 139 #define GEN_RD_CMD_BUSY                 BIT(6)
 140 #define GEN_PLD_R_FULL                  BIT(5)
 141 #define GEN_PLD_R_EMPTY                 BIT(4)
 142 #define GEN_PLD_W_FULL                  BIT(3)
 143 #define GEN_PLD_W_EMPTY                 BIT(2)
 144 #define GEN_CMD_FULL                    BIT(1)
 145 #define GEN_CMD_EMPTY                   BIT(0)
 146
 147 #define DSI_TO_CNT_CFG                  0x78
 148 #define HSTX_TO_CNT(p)                  (((p) & 0xffff) << 16)
 149 #define LPRX_TO_CNT(p)                  ((p) & 0xffff)
 150
 151 #define DSI_HS_RD_TO_CNT                0x7c
 152 #define DSI_LP_RD_TO_CNT                0x80
 153 #define DSI_HS_WR_TO_CNT                0x84
 154 #define DSI_LP_WR_TO_CNT                0x88
 155 #define DSI_BTA_TO_CNT                  0x8c
 156
 157 #define DSI_LPCLK_CTRL                  0x94
 158 #define AUTO_CLKLANE_CTRL               BIT(1)
 159 #define PHY_TXREQUESTCLKHS              BIT(0)
 160
 161 #define DSI_PHY_TMR_LPCLK_CFG           0x98
 162 #define PHY_CLKHS2LP_TIME(lbcc)         (((lbcc) & 0x3ff) << 16)
 163 #define PHY_CLKLP2HS_TIME(lbcc)         ((lbcc) & 0x3ff)
 164
 165 #define DSI_PHY_TMR_CFG                 0x9c
 166 #define PHY_HS2LP_TIME(lbcc)            (((lbcc) & 0xff) << 24)
 167 #define PHY_LP2HS_TIME(lbcc)            (((lbcc) & 0xff) << 16)
 168 #define MAX_RD_TIME(lbcc)               ((lbcc) & 0x7fff)
 169 #define PHY_HS2LP_TIME_V131(lbcc)       (((lbcc) & 0x3ff) << 16)
 170 #define PHY_LP2HS_TIME_V131(lbcc)       ((lbcc) & 0x3ff)
 171
 172 #define DSI_PHY_RSTZ                    0xa0
 173 #define PHY_DISFORCEPLL                 0
 174 #define PHY_ENFORCEPLL                  BIT(3)
 175 #define PHY_DISABLECLK                  0
 176 #define PHY_ENABLECLK                   BIT(2)
 177 #define PHY_RSTZ                        0
 178 #define PHY_UNRSTZ                      BIT(1)
 179 #define PHY_SHUTDOWNZ                   0
 180 #define PHY_UNSHUTDOWNZ                 BIT(0)
 181
 182 #define DSI_PHY_IF_CFG                  0xa4
 183 #define PHY_STOP_WAIT_TIME(cycle)       (((cycle) & 0xff) << 8)
 184 #define N_LANES(n)                      (((n) - 1) & 0x3)
 185
 186 #define DSI_PHY_ULPS_CTRL               0xa8
 187 #define DSI_PHY_TX_TRIGGERS             0xac
 188
 189 #define DSI_PHY_STATUS                  0xb0
 190 #define PHY_STOP_STATE_CLK_LANE         BIT(2)
 191 #define PHY_LOCK                        BIT(0)
 192
 193 #define DSI_PHY_TST_CTRL0               0xb4
 194 #define PHY_TESTCLK                     BIT(1)
 195 #define PHY_UNTESTCLK                   0
 196 #define PHY_TESTCLR                     BIT(0)
 197 #define PHY_UNTESTCLR                   0
 198
 199 #define DSI_PHY_TST_CTRL1               0xb8
 200 #define PHY_TESTEN                      BIT(16)
 201 #define PHY_UNTESTEN                    0
 202 #define PHY_TESTDOUT(n)                 (((n) & 0xff) << 8)
 203 #define PHY_TESTDIN(n)                  ((n) & 0xff)
 204
 205 #define DSI_INT_ST0                     0xbc
 206 #define DSI_INT_ST1                     0xc0
 207 #define DSI_INT_MSK0                    0xc4
 208 #define DSI_INT_MSK1                    0xc8
 209
 210 #define DSI_PHY_TMR_RD_CFG              0xf4
 211 #define MAX_RD_TIME_V131(lbcc)          ((lbcc) & 0x7fff)
 212
 213 #define PHY_STATUS_TIMEOUT_US           10000
 214 #define CMD_PKT_STATUS_TIMEOUT_US       20000
 215
 216 #define MSEC_PER_SEC                    1000
 217
 218 struct dw_mipi_dsi {
 219         struct mipi_dsi_host dsi_host;
 220         struct mipi_dsi_device *device;
 221         void __iomem *base;
 222         unsigned int lane_mbps; /* per lane */
 223         u32 channel;
 224         unsigned int max_data_lanes;
 225         const struct mipi_dsi_phy_ops *phy_ops;
 226 };
 227
 228 static int dsi_mode_vrefresh(struct display_timing *timings)
 229 {
 230         int refresh = 0;
 231         unsigned int calc_val;
 232         u32 htotal = timings->hactive.typ + timings->hfront_porch.typ +
 233                      timings->hback_porch.typ + timings->hsync_len.typ;
 234         u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ +
 235                      timings->vback_porch.typ + timings->vsync_len.typ;
 236
 237         if (htotal > 0 && vtotal > 0) {
 238                 calc_val = timings->pixelclock.typ;
 239                 calc_val /= htotal;
 240                 refresh = (calc_val + vtotal / 2) / vtotal;
 241         }
 242
 243         return refresh;
 244 }
 245
 246 /*
 247  * The controller should generate 2 frames before
 248  * preparing the peripheral.
 249  */
 250 static void dw_mipi_dsi_wait_for_two_frames(struct display_timing *timings)
 251 {
 252         int refresh, two_frames;
 253
 254         refresh = dsi_mode_vrefresh(timings);
 255         two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
 256         mdelay(two_frames);
 257 }
 258
 259 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
 260 {
 261         return container_of(host, struct dw_mipi_dsi, dsi_host);
 262 }
 263
 264 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
 265 {
 266         writel(val, dsi->base + reg);
 267 }
 268
 269 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
 270 {
 271         return readl(dsi->base + reg);
 272 }
 273
 274 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
 275                                    struct mipi_dsi_device *device)
 276 {
 277         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 278
 279         if (device->lanes > dsi->max_data_lanes) {
 280                 dev_err(device->dev,
 281                         "the number of data lanes(%u) is too many\n",
 282                         device->lanes);
 283                 return -EINVAL;
 284         }
 285
 286         dsi->channel = device->channel;
 287
 288         return 0;
 289 }
 290
 291 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 292                                    const struct mipi_dsi_msg *msg)
 293 {
 294         bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
 295         u32 val = 0;
 296
 297         if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
 298                 val |= ACK_RQST_EN;
 299         if (lpm)
 300                 val |= CMD_MODE_ALL_LP;
 301
 302         dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
 303         dsi_write(dsi, DSI_CMD_MODE_CFG, val);
 304 }
 305
 306 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
 307 {
 308         int ret;
 309         u32 val, mask;
 310
 311         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 312                                  val, !(val & GEN_CMD_FULL),
 313                                  CMD_PKT_STATUS_TIMEOUT_US);
 314         if (ret) {
 315                 dev_err(dsi->dev, "failed to get available command FIFO\n");
 316                 return ret;
 317         }
 318
 319         dsi_write(dsi, DSI_GEN_HDR, hdr_val);
 320
 321         mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
 322         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 323                                  val, (val & mask) == mask,
 324                                  CMD_PKT_STATUS_TIMEOUT_US);
 325         if (ret) {
 326                 dev_err(dsi->dev, "failed to write command FIFO\n");
 327                 return ret;
 328         }
 329
 330         return 0;
 331 }
 332
 333 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
 334                              const struct mipi_dsi_packet *packet)
 335 {
 336         const u8 *tx_buf = packet->payload;
 337         int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
 338         __le32 word;
 339         u32 val;
 340
 341         while (len) {
 342                 if (len < pld_data_bytes) {
 343                         word = 0;
 344                         memcpy(&word, tx_buf, len);
 345                         dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 346                         len = 0;
 347                 } else {
 348                         memcpy(&word, tx_buf, pld_data_bytes);
 349                         dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
 350                         tx_buf += pld_data_bytes;
 351                         len -= pld_data_bytes;
 352                 }
 353
 354                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 355                                          val, !(val & GEN_PLD_W_FULL),
 356                                          CMD_PKT_STATUS_TIMEOUT_US);
 357                 if (ret) {
 358                         dev_err(dsi->dev,
 359                                 "failed to get available write payload FIFO\n");
 360                         return ret;
 361                 }
 362         }
 363
 364         word = 0;
 365         memcpy(&word, packet->header, sizeof(packet->header));
 366         return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
 367 }
 368
 369 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
 370                             const struct mipi_dsi_msg *msg)
 371 {
 372         int i, j, ret, len = msg->rx_len;
 373         u8 *buf = msg->rx_buf;
 374         u32 val;
 375
 376         /* Wait end of the read operation */
 377         ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 378                                  val, !(val & GEN_RD_CMD_BUSY),
 379                                  CMD_PKT_STATUS_TIMEOUT_US);
 380         if (ret) {
 381                 dev_err(dsi->dev, "Timeout during read operation\n");
 382                 return ret;
 383         }
 384
 385         for (i = 0; i < len; i += 4) {
 386                 /* Read fifo must not be empty before all bytes are read */
 387                 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
 388                                          val, !(val & GEN_PLD_R_EMPTY),
 389                                          CMD_PKT_STATUS_TIMEOUT_US);
 390                 if (ret) {
 391                         dev_err(dsi->dev, "Read payload FIFO is empty\n");
 392                         return ret;
 393                 }
 394
 395                 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
 396                 for (j = 0; j < 4 && j + i < len; j++)
 397                         buf[i + j] = val >> (8 * j);
 398         }
 399
 400         return ret;
 401 }
 402
 403 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
 404                                          const struct mipi_dsi_msg *msg)
 405 {
 406         struct dw_mipi_dsi *dsi = host_to_dsi(host);
 407         struct mipi_dsi_packet packet;
 408         int ret, nb_bytes;
 409
 410         ret = mipi_dsi_create_packet(&packet, msg);
 411         if (ret) {
 412                 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
 413                 return ret;
 414         }
 415
 416         dw_mipi_message_config(dsi, msg);
 417
 418         ret = dw_mipi_dsi_write(dsi, &packet);
 419         if (ret)
 420                 return ret;
 421
 422         if (msg->rx_buf && msg->rx_len) {
 423                 ret = dw_mipi_dsi_read(dsi, msg);
 424                 if (ret)
 425                         return ret;
 426                 nb_bytes = msg->rx_len;
 427         } else {
 428                 nb_bytes = packet.size;
 429         }
 430
 431         return nb_bytes;
 432 }
 433
 434 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
 435         .attach = dw_mipi_dsi_host_attach,
 436         .transfer = dw_mipi_dsi_host_transfer,
 437 };
 438
 439 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 440 {
 441         struct mipi_dsi_device *device = dsi->device;
 442         u32 val;
 443
 444         /*
 445          * TODO dw drv improvements
 446          * enabling low power is panel-dependent, we should use the
 447          * panel configuration here...
 448          */
 449         val = ENABLE_LOW_POWER;
 450
 451         if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 452                 val |= VID_MODE_TYPE_BURST;
 453         else if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 454                 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
 455         else
 456                 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
 457
 458         dsi_write(dsi, DSI_VID_MODE_CFG, val);
 459 }
 460
 461 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 462                                  unsigned long mode_flags)
 463 {
 464         const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
 465
 466         dsi_write(dsi, DSI_PWR_UP, RESET);
 467
 468         if (mode_flags & MIPI_DSI_MODE_VIDEO) {
 469                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
 470                 dw_mipi_dsi_video_mode_config(dsi);
 471                 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
 472         } else {
 473                 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 474         }
 475
 476         if (phy_ops->post_set_mode)
 477                 phy_ops->post_set_mode(dsi->device, mode_flags);
 478
 479         dsi_write(dsi, DSI_PWR_UP, POWERUP);
 480 }
 481
 482 static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
 483 {
 484         /*
 485          * The maximum permitted escape clock is 20MHz and it is derived from
 486          * lanebyteclk, which is running at "lane_mbps / 8".  Thus we want:
 487          *
 488          *     (lane_mbps >> 3) / esc_clk_division < 20
 489          * which is:
 490          *     (lane_mbps >> 3) / 20 > esc_clk_division
 491          */
 492         u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
 493
 494         dsi_write(dsi, DSI_PWR_UP, RESET);
 495
 496         /*
 497          * TODO dw drv improvements
 498          * timeout clock division should be computed with the
 499          * high speed transmission counter timeout and byte lane...
 500          */
 501         dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
 502                   TX_ESC_CLK_DIVISION(esc_clk_division));
 503 }
 504
 505 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 506                                    struct display_timing *timings)
 507 {
 508         struct mipi_dsi_device *device = dsi->device;
 509         u32 val = 0, color = 0;
 510
 511         switch (device->format) {
 512         case MIPI_DSI_FMT_RGB888:
 513                 color = DPI_COLOR_CODING_24BIT;
 514                 break;
 515         case MIPI_DSI_FMT_RGB666:
 516                 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
 517                 break;
 518         case MIPI_DSI_FMT_RGB666_PACKED:
 519                 color = DPI_COLOR_CODING_18BIT_1;
 520                 break;
 521         case MIPI_DSI_FMT_RGB565:
 522                 color = DPI_COLOR_CODING_16BIT_1;
 523                 break;
 524         }
 525
 526         if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
 527                 val |= VSYNC_ACTIVE_LOW;
 528         if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
 529                 val |= HSYNC_ACTIVE_LOW;
 530
 531         dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
 532         dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
 533         dsi_write(dsi, DSI_DPI_CFG_POL, val);
 534         /*
 535          * TODO dw drv improvements
 536          * largest packet sizes during hfp or during vsa/vpb/vfp
 537          * should be computed according to byte lane, lane number and only
 538          * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
 539          */
 540         dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
 541                   | INVACT_LPCMD_TIME(4));
 542 }
 543
 544 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
 545 {
 546         dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
 547 }
 548
 549 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
 550                                             struct display_timing *timings)
 551 {
 552         /*
 553          * TODO dw drv improvements
 554          * only burst mode is supported here. For non-burst video modes,
 555          * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
 556          * DSI_VNPCR.NPSIZE... especially because this driver supports
 557          * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
 558          */
 559         dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ));
 560 }
 561
 562 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
 563 {
 564         const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
 565
 566         /*
 567          * TODO dw drv improvements
 568          * compute high speed transmission counter timeout according
 569          * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
 570          */
 571         dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
 572         /*
 573          * TODO dw drv improvements
 574          * the Bus-Turn-Around Timeout Counter should be computed
 575          * according to byte lane...
 576          */
 577         dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
 578         dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
 579
 580         if (phy_ops->post_set_mode)
 581                 phy_ops->post_set_mode(dsi->device, 0);
 582 }
 583
 584 /* Get lane byte clock cycles. */
 585 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
 586                                            struct display_timing *timings,
 587                                            u32 hcomponent)
 588 {
 589         u32 frac, lbcc;
 590
 591         lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
 592
 593         frac = lbcc % (timings->pixelclock.typ / 1000);
 594         lbcc = lbcc / (timings->pixelclock.typ / 1000);
 595         if (frac)
 596                 lbcc++;
 597
 598         return lbcc;
 599 }
 600
 601 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 602                                           struct display_timing *timings)
 603 {
 604         u32 htotal, hsa, hbp, lbcc;
 605
 606         htotal = timings->hactive.typ + timings->hfront_porch.typ +
 607                  timings->hback_porch.typ + timings->hsync_len.typ;
 608
 609         hsa = timings->hback_porch.typ;
 610         hbp = timings->hsync_len.typ;
 611
 612         /*
 613          * TODO dw drv improvements
 614          * computations below may be improved...
 615          */
 616         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal);
 617         dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
 618
 619         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa);
 620         dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
 621
 622         lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp);
 623         dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
 624 }
 625
 626 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 627                                                struct display_timing *timings)
 628 {
 629         u32 vactive, vsa, vfp, vbp;
 630
 631         vactive = timings->vactive.typ;
 632         vsa =  timings->vback_porch.typ;
 633         vfp =  timings->vfront_porch.typ;
 634         vbp = timings->vsync_len.typ;
 635
 636         dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 637         dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
 638         dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
 639         dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
 640 }
 641
 642 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
 643 {
 644         u32 hw_version;
 645
 646         /*
 647          * TODO dw drv improvements
 648          * data & clock lane timers should be computed according to panel
 649          * blankings and to the automatic clock lane control mode...
 650          * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
 651          * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
 652          */
 653
 654         hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
 655
 656         if (hw_version >= HWVER_131) {
 657                 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
 658                           PHY_LP2HS_TIME_V131(0x40));
 659                 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
 660         } else {
 661                 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
 662                           PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
 663         }
 664
 665         dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
 666                   | PHY_CLKLP2HS_TIME(0x40));
 667 }
 668
 669 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
 670 {
 671         struct mipi_dsi_device *device = dsi->device;
 672
 673         /*
 674          * TODO dw drv improvements
 675          * stop wait time should be the maximum between host dsi
 676          * and panel stop wait times
 677          */
 678         dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
 679                   N_LANES(device->lanes));
 680 }
 681
 682 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
 683 {
 684         /* Clear PHY state */
 685         dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
 686                   | PHY_RSTZ | PHY_SHUTDOWNZ);
 687         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 688         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
 689         dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
 690 }
 691
 692 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
 693 {
 694         u32 val;
 695         int ret;
 696
 697         dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
 698                   PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 699
 700         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
 701                                  val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
 702         if (ret)
 703                 dev_warn(dsi->dev, "failed to wait phy lock state\n");
 704
 705         ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
 706                                  val, val & PHY_STOP_STATE_CLK_LANE,
 707                                  PHY_STATUS_TIMEOUT_US);
 708         if (ret)
 709                 dev_warn(dsi->dev, "failed to wait phy clk lane stop state\n");
 710 }
 711
 712 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
 713 {
 714         dsi_read(dsi, DSI_INT_ST0);
 715         dsi_read(dsi, DSI_INT_ST1);
 716         dsi_write(dsi, DSI_INT_MSK0, 0);
 717         dsi_write(dsi, DSI_INT_MSK1, 0);
 718 }
 719
 720 static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi,
 721                                    struct display_timing *timings)
 722 {
 723         const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
 724         struct mipi_dsi_device *device = dsi->device;
 725         int ret;
 726
 727         ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
 728                                      device->format, &dsi->lane_mbps);
 729         if (ret)
 730                 dev_warn(dsi->dev, "Phy get_lane_mbps() failed\n");
 731
 732         dw_mipi_dsi_init_pll(dsi);
 733         dw_mipi_dsi_dpi_config(dsi, timings);
 734         dw_mipi_dsi_packet_handler_config(dsi);
 735         dw_mipi_dsi_video_mode_config(dsi);
 736         dw_mipi_dsi_video_packet_config(dsi, timings);
 737         dw_mipi_dsi_command_mode_config(dsi);
 738         dw_mipi_dsi_line_timer_config(dsi, timings);
 739         dw_mipi_dsi_vertical_timing_config(dsi, timings);
 740
 741         dw_mipi_dsi_dphy_init(dsi);
 742         dw_mipi_dsi_dphy_timing_config(dsi);
 743         dw_mipi_dsi_dphy_interface_config(dsi);
 744
 745         dw_mipi_dsi_clear_err(dsi);
 746
 747         ret = phy_ops->init(dsi->device);
 748         if (ret)
 749                 dev_warn(dsi->dev, "Phy init() failed\n");
 750
 751         dw_mipi_dsi_dphy_enable(dsi);
 752
 753         dw_mipi_dsi_wait_for_two_frames(timings);
 754
 755         /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
 756         dw_mipi_dsi_set_mode(dsi, 0);
 757 }
 758
 759 static int dw_mipi_dsi_init(struct udevice *dev,
 760                             struct mipi_dsi_device *device,
 761                             struct display_timing *timings,
 762                             unsigned int max_data_lanes,
 763                             const struct mipi_dsi_phy_ops *phy_ops)
 764 {
 765         struct dw_mipi_dsi *dsi = dev_get_priv(dev);
 766         struct clk clk;
 767         int ret;
 768
 769         if (!phy_ops->init || !phy_ops->get_lane_mbps) {
 770                 dev_err(device->dev, "Phy not properly configured\n");
 771                 return -ENODEV;
 772         }
 773
 774         dsi->phy_ops = phy_ops;
 775         dsi->max_data_lanes = max_data_lanes;
 776         dsi->device = device;
 777         dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
 778         device->host = &dsi->dsi_host;
 779
 780         dsi->base = (void *)dev_read_addr(device->dev);
 781         if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
 782                 dev_err(device->dev, "dsi dt register address error\n");
 783                 return -EINVAL;
 784         }
 785
 786         ret = clk_get_by_name(device->dev, "px_clk", &clk);
 787         if (ret) {
 788                 dev_err(device->dev, "peripheral clock get error %d\n", ret);
 789                 return ret;
 790         }
 791
 792         /*  get the pixel clock set by the clock framework */
 793         timings->pixelclock.typ = clk_get_rate(&clk);
 794
 795         dw_mipi_dsi_bridge_set(dsi, timings);
 796
 797         return 0;
 798 }
 799
 800 static int dw_mipi_dsi_enable(struct udevice *dev)
 801 {
 802         struct dw_mipi_dsi *dsi = dev_get_priv(dev);
 803
 804         /* Switch to video mode for panel-bridge enable & panel enable */
 805         dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
 806
 807         return 0;
 808 }
 809
 810 struct dsi_host_ops dw_mipi_dsi_ops = {
 811         .init = dw_mipi_dsi_init,
 812         .enable = dw_mipi_dsi_enable,
 813 };
 814
 815 static int dw_mipi_dsi_probe(struct udevice *dev)
 816 {
 817         return 0;
 818 }
 819
 820 U_BOOT_DRIVER(dw_mipi_dsi) = {
 821         .name                   = "dw_mipi_dsi",
 822         .id                     = UCLASS_DSI_HOST,
 823         .probe                  = dw_mipi_dsi_probe,
 824         .ops                    = &dw_mipi_dsi_ops,
 825         .priv_auto_alloc_size   = sizeof(struct dw_mipi_dsi),
 826 };
 827
 828 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
 829 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
 830 MODULE_AUTHOR("Yannick Fertré <yannick.fertre@st.com>");
 831 MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
 832 MODULE_LICENSE("GPL");
 833 MODULE_ALIAS("platform:dw-mipi-dsi");