drivers/video/da8xx-fb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Porting to u-boot:
   4  *
   5  * (C) Copyright 2011
   6  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   7  *
   8  * Copyright (C) 2008-2009 MontaVista Software Inc.
   9  * Copyright (C) 2008-2009 Texas Instruments Inc
  10  *
  11  * Based on the LCD driver for TI Avalanche processors written by
  12  * Ajay Singh and Shalom Hai.
  13  */
  14
  15 #include <common.h>
  16 #include <log.h>
  17 #include <malloc.h>
  18 #include <memalign.h>
  19 #include <video_fb.h>
  20 #include <linux/list.h>
  21 #include <linux/fb.h>
  22
  23 #include <linux/errno.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/hardware.h>
  26
  27 #include "videomodes.h"
  28 #include "da8xx-fb.h"
  29
  30 #if !defined(DA8XX_LCD_CNTL_BASE)
  31 #define DA8XX_LCD_CNTL_BASE     DAVINCI_LCD_CNTL_BASE
  32 #endif
  33
  34 #define DRIVER_NAME "da8xx_lcdc"
  35
  36 #define LCD_VERSION_1   1
  37 #define LCD_VERSION_2   2
  38
  39 /* LCD Status Register */
  40 #define LCD_END_OF_FRAME1               (1 << 9)
  41 #define LCD_END_OF_FRAME0               (1 << 8)
  42 #define LCD_PL_LOAD_DONE                (1 << 6)
  43 #define LCD_FIFO_UNDERFLOW              (1 << 5)
  44 #define LCD_SYNC_LOST                   (1 << 2)
  45
  46 /* LCD DMA Control Register */
  47 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
  48 #define LCD_DMA_BURST_1                 0x0
  49 #define LCD_DMA_BURST_2                 0x1
  50 #define LCD_DMA_BURST_4                 0x2
  51 #define LCD_DMA_BURST_8                 0x3
  52 #define LCD_DMA_BURST_16                0x4
  53 #define LCD_V1_END_OF_FRAME_INT_ENA     (1 << 2)
  54 #define LCD_V2_END_OF_FRAME0_INT_ENA    (1 << 8)
  55 #define LCD_V2_END_OF_FRAME1_INT_ENA    (1 << 9)
  56 #define LCD_DUAL_FRAME_BUFFER_ENABLE    (1 << 0)
  57
  58 #define LCD_V2_TFT_24BPP_MODE           (1 << 25)
  59 #define LCD_V2_TFT_24BPP_UNPACK         (1 << 26)
  60
  61 /* LCD Control Register */
  62 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
  63 #define LCD_RASTER_MODE                 0x01
  64
  65 /* LCD Raster Control Register */
  66 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
  67 #define PALETTE_AND_DATA                0x00
  68 #define PALETTE_ONLY                    0x01
  69 #define DATA_ONLY                       0x02
  70
  71 #define LCD_MONO_8BIT_MODE              (1 << 9)
  72 #define LCD_RASTER_ORDER                (1 << 8)
  73 #define LCD_TFT_MODE                    (1 << 7)
  74 #define LCD_V1_UNDERFLOW_INT_ENA        (1 << 6)
  75 #define LCD_V2_UNDERFLOW_INT_ENA        (1 << 5)
  76 #define LCD_V1_PL_INT_ENA               (1 << 4)
  77 #define LCD_V2_PL_INT_ENA               (1 << 6)
  78 #define LCD_MONOCHROME_MODE             (1 << 1)
  79 #define LCD_RASTER_ENABLE               (1 << 0)
  80 #define LCD_TFT_ALT_ENABLE              (1 << 23)
  81 #define LCD_STN_565_ENABLE              (1 << 24)
  82 #define LCD_V2_DMA_CLK_EN               (1 << 2)
  83 #define LCD_V2_LIDD_CLK_EN              (1 << 1)
  84 #define LCD_V2_CORE_CLK_EN              (1 << 0)
  85 #define LCD_V2_LPP_B10                  26
  86 #define LCD_V2_TFT_24BPP_MODE           (1 << 25)
  87 #define LCD_V2_TFT_24BPP_UNPACK         (1 << 26)
  88
  89 /* LCD Raster Timing 2 Register */
  90 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  91 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
  92 #define LCD_SYNC_CTRL                           (1 << 25)
  93 #define LCD_SYNC_EDGE                           (1 << 24)
  94 #define LCD_INVERT_PIXEL_CLOCK                  (1 << 22)
  95 #define LCD_INVERT_LINE_CLOCK                   (1 << 21)
  96 #define LCD_INVERT_FRAME_CLOCK                  (1 << 20)
  97
  98 /* Clock registers available only on Version 2 */
  99 #define  LCD_CLK_MAIN_RESET                     (1 << 3)
 100 /* LCD Block */
 101 struct da8xx_lcd_regs {
 102         u32     revid;
 103         u32     ctrl;
 104         u32     stat;
 105         u32     lidd_ctrl;
 106         u32     lidd_cs0_conf;
 107         u32     lidd_cs0_addr;
 108         u32     lidd_cs0_data;
 109         u32     lidd_cs1_conf;
 110         u32     lidd_cs1_addr;
 111         u32     lidd_cs1_data;
 112         u32     raster_ctrl;
 113         u32     raster_timing_0;
 114         u32     raster_timing_1;
 115         u32     raster_timing_2;
 116         u32     raster_subpanel;
 117         u32     reserved;
 118         u32     dma_ctrl;
 119         u32     dma_frm_buf_base_addr_0;
 120         u32     dma_frm_buf_ceiling_addr_0;
 121         u32     dma_frm_buf_base_addr_1;
 122         u32     dma_frm_buf_ceiling_addr_1;
 123         u32     resv1;
 124         u32     raw_stat;
 125         u32     masked_stat;
 126         u32     int_ena_set;
 127         u32     int_ena_clr;
 128         u32     end_of_int_ind;
 129         /* Clock registers available only on Version 2 */
 130         u32     clk_ena;
 131         u32     clk_reset;
 132 };
 133
 134 #define LCD_NUM_BUFFERS 1
 135
 136 #define WSI_TIMEOUT     50
 137 #define PALETTE_SIZE    256
 138 #define LEFT_MARGIN     64
 139 #define RIGHT_MARGIN    64
 140 #define UPPER_MARGIN    32
 141 #define LOWER_MARGIN    32
 142 #define WAIT_FOR_FRAME_DONE     true
 143 #define NO_WAIT_FOR_FRAME_DONE  false
 144
 145 #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
 146
 147 static struct da8xx_lcd_regs *da8xx_fb_reg_base;
 148
 149 DECLARE_GLOBAL_DATA_PTR;
 150
 151 /* graphics setup */
 152 static GraphicDevice gpanel;
 153 static const struct da8xx_panel *lcd_panel;
 154 static struct fb_info *da8xx_fb_info;
 155 static int bits_x_pixel;
 156 static unsigned int lcd_revision;
 157 const struct lcd_ctrl_config *da8xx_lcd_cfg;
 158
 159 static inline unsigned int lcdc_read(u32 *addr)
 160 {
 161         return (unsigned int)readl(addr);
 162 }
 163
 164 static inline void lcdc_write(unsigned int val, u32 *addr)
 165 {
 166         writel(val, addr);
 167 }
 168
 169 struct da8xx_fb_par {
 170         u32                      p_palette_base;
 171         unsigned char *v_palette_base;
 172         dma_addr_t              vram_phys;
 173         unsigned long           vram_size;
 174         void                    *vram_virt;
 175         unsigned int            dma_start;
 176         unsigned int            dma_end;
 177         struct clk *lcdc_clk;
 178         int irq;
 179         unsigned short pseudo_palette[16];
 180         unsigned int palette_sz;
 181         unsigned int pxl_clk;
 182         int blank;
 183         int                     vsync_flag;
 184         int                     vsync_timeout;
 185 };
 186
 187
 188 /* Variable Screen Information */
 189 static struct fb_var_screeninfo da8xx_fb_var = {
 190         .xoffset = 0,
 191         .yoffset = 0,
 192         .transp = {0, 0, 0},
 193         .nonstd = 0,
 194         .activate = 0,
 195         .height = -1,
 196         .width = -1,
 197         .pixclock = 46666,      /* 46us - AUO display */
 198         .accel_flags = 0,
 199         .left_margin = LEFT_MARGIN,
 200         .right_margin = RIGHT_MARGIN,
 201         .upper_margin = UPPER_MARGIN,
 202         .lower_margin = LOWER_MARGIN,
 203         .sync = 0,
 204         .vmode = FB_VMODE_NONINTERLACED
 205 };
 206
 207 static struct fb_fix_screeninfo da8xx_fb_fix = {
 208         .id = "DA8xx FB Drv",
 209         .type = FB_TYPE_PACKED_PIXELS,
 210         .type_aux = 0,
 211         .visual = FB_VISUAL_PSEUDOCOLOR,
 212         .xpanstep = 0,
 213         .ypanstep = 1,
 214         .ywrapstep = 0,
 215         .accel = FB_ACCEL_NONE
 216 };
 217
 218 /* Enable the Raster Engine of the LCD Controller */
 219 static inline void lcd_enable_raster(void)
 220 {
 221         u32 reg;
 222
 223         /* Put LCDC in reset for several cycles */
 224         if (lcd_revision == LCD_VERSION_2)
 225                 lcdc_write(LCD_CLK_MAIN_RESET,
 226                            &da8xx_fb_reg_base->clk_reset);
 227
 228         udelay(1000);
 229         /* Bring LCDC out of reset */
 230         if (lcd_revision == LCD_VERSION_2)
 231                 lcdc_write(0,
 232                            &da8xx_fb_reg_base->clk_reset);
 233
 234         udelay(1000);
 235
 236         reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
 237         if (!(reg & LCD_RASTER_ENABLE))
 238                 lcdc_write(reg | LCD_RASTER_ENABLE,
 239                         &da8xx_fb_reg_base->raster_ctrl);
 240 }
 241
 242 /* Disable the Raster Engine of the LCD Controller */
 243 static inline void lcd_disable_raster(bool wait_for_frame_done)
 244 {
 245         u32 reg;
 246         u32 loop_cnt = 0;
 247         u32 stat;
 248         u32 i = 0;
 249
 250         if (wait_for_frame_done)
 251                 loop_cnt = 5000;
 252
 253         reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
 254         if (reg & LCD_RASTER_ENABLE)
 255                 lcdc_write(reg & ~LCD_RASTER_ENABLE,
 256                         &da8xx_fb_reg_base->raster_ctrl);
 257
 258         /* Wait for the current frame to complete */
 259         do {
 260                 if (lcd_revision == LCD_VERSION_1)
 261                         stat = lcdc_read(&da8xx_fb_reg_base->stat);
 262                 else
 263                         stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
 264
 265                 mdelay(1);
 266         } while (!(stat & 0x01) && (i++ < loop_cnt));
 267
 268         if (lcd_revision == LCD_VERSION_1)
 269                 lcdc_write(stat, &da8xx_fb_reg_base->stat);
 270         else
 271                 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
 272
 273         if ((loop_cnt != 0) && (i >= loop_cnt)) {
 274                 printf("LCD Controller timed out\n");
 275                 return;
 276         }
 277 }
 278
 279 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
 280 {
 281         u32 start;
 282         u32 end;
 283         u32 reg_ras;
 284         u32 reg_dma;
 285         u32 reg_int;
 286
 287         /* init reg to clear PLM (loading mode) fields */
 288         reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
 289         reg_ras &= ~(3 << 20);
 290
 291         reg_dma  = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
 292
 293         if (load_mode == LOAD_DATA) {
 294                 start    = par->dma_start;
 295                 end      = par->dma_end;
 296
 297                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
 298                 if (lcd_revision == LCD_VERSION_1) {
 299                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
 300                 } else {
 301                         reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
 302                                 LCD_V2_END_OF_FRAME0_INT_ENA |
 303                                 LCD_V2_END_OF_FRAME1_INT_ENA |
 304                                 LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
 305                         lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
 306                 }
 307
 308 #if (LCD_NUM_BUFFERS == 2)
 309                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
 310                 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 311                 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 312                 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
 313                 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 314 #else
 315                 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
 316                 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 317                 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 318                 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
 319                 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 320 #endif
 321
 322         } else if (load_mode == LOAD_PALETTE) {
 323                 start    = par->p_palette_base;
 324                 end      = start + par->palette_sz - 1;
 325
 326                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
 327                 if (lcd_revision == LCD_VERSION_1) {
 328                         reg_ras |= LCD_V1_PL_INT_ENA;
 329                 } else {
 330                         reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
 331                                 LCD_V2_PL_INT_ENA;
 332                         lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
 333                 }
 334
 335                 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 336                 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 337         }
 338
 339         lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
 340         lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
 341
 342         /*
 343          * The Raster enable bit must be set after all other control fields are
 344          * set.
 345          */
 346         lcd_enable_raster();
 347 }
 348
 349 /* Configure the Burst Size of DMA */
 350 static int lcd_cfg_dma(int burst_size)
 351 {
 352         u32 reg;
 353
 354         reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
 355         switch (burst_size) {
 356         case 1:
 357                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
 358                 break;
 359         case 2:
 360                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
 361                 break;
 362         case 4:
 363                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
 364                 break;
 365         case 8:
 366                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
 367                 break;
 368         case 16:
 369                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 370                 break;
 371         default:
 372                 return -EINVAL;
 373         }
 374         lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
 375
 376         return 0;
 377 }
 378
 379 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
 380 {
 381         u32 reg;
 382
 383         /* Set the AC Bias Period and Number of Transitions per Interrupt */
 384         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
 385         reg |= LCD_AC_BIAS_FREQUENCY(period) |
 386                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
 387         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
 388 }
 389
 390 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 391                 int front_porch)
 392 {
 393         u32 reg;
 394
 395         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
 396         reg |= ((back_porch & 0xff) << 24)
 397             | ((front_porch & 0xff) << 16)
 398             | ((pulse_width & 0x3f) << 10);
 399         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
 400 }
 401
 402 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 403                 int front_porch)
 404 {
 405         u32 reg;
 406
 407         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
 408         reg |= ((back_porch & 0xff) << 24)
 409             | ((front_porch & 0xff) << 16)
 410             | ((pulse_width & 0x3f) << 10);
 411         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
 412 }
 413
 414 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
 415 {
 416         u32 reg;
 417         u32 reg_int;
 418
 419         reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
 420                                                 LCD_MONO_8BIT_MODE |
 421                                                 LCD_MONOCHROME_MODE);
 422
 423         switch (cfg->p_disp_panel->panel_shade) {
 424         case MONOCHROME:
 425                 reg |= LCD_MONOCHROME_MODE;
 426                 if (cfg->mono_8bit_mode)
 427                         reg |= LCD_MONO_8BIT_MODE;
 428                 break;
 429         case COLOR_ACTIVE:
 430                 reg |= LCD_TFT_MODE;
 431                 if (cfg->tft_alt_mode)
 432                         reg |= LCD_TFT_ALT_ENABLE;
 433                 break;
 434
 435         case COLOR_PASSIVE:
 436                 if (cfg->stn_565_mode)
 437                         reg |= LCD_STN_565_ENABLE;
 438                 break;
 439
 440         default:
 441                 return -EINVAL;
 442         }
 443
 444         /* enable additional interrupts here */
 445         if (lcd_revision == LCD_VERSION_1) {
 446                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
 447         } else {
 448                 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
 449                         LCD_V2_UNDERFLOW_INT_ENA;
 450                 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
 451         }
 452
 453         lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
 454
 455         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
 456
 457         if (cfg->sync_ctrl)
 458                 reg |= LCD_SYNC_CTRL;
 459         else
 460                 reg &= ~LCD_SYNC_CTRL;
 461
 462         if (cfg->sync_edge)
 463                 reg |= LCD_SYNC_EDGE;
 464         else
 465                 reg &= ~LCD_SYNC_EDGE;
 466
 467         if (cfg->invert_line_clock)
 468                 reg |= LCD_INVERT_LINE_CLOCK;
 469         else
 470                 reg &= ~LCD_INVERT_LINE_CLOCK;
 471
 472         if (cfg->invert_frm_clock)
 473                 reg |= LCD_INVERT_FRAME_CLOCK;
 474         else
 475                 reg &= ~LCD_INVERT_FRAME_CLOCK;
 476
 477         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
 478
 479         return 0;
 480 }
 481
 482 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
 483                 u32 bpp, u32 raster_order)
 484 {
 485         u32 reg;
 486
 487         /* Set the Panel Width */
 488         /* Pixels per line = (PPL + 1)*16 */
 489         if (lcd_revision == LCD_VERSION_1) {
 490                 /*
 491                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
 492                  * pixels
 493                  */
 494                 width &= 0x3f0;
 495         } else {
 496                 /*
 497                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
 498                  * pixels.
 499                  */
 500                 width &= 0x7f0;
 501         }
 502         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
 503         reg &= 0xfffffc00;
 504         if (lcd_revision == LCD_VERSION_1) {
 505                 reg |= ((width >> 4) - 1) << 4;
 506         } else {
 507                 width = (width >> 4) - 1;
 508                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
 509         }
 510         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
 511
 512         /* Set the Panel Height */
 513         /* Set bits 9:0 of Lines Per Pixel */
 514         reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
 515         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
 516         lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
 517
 518         /* Set bit 10 of Lines Per Pixel */
 519         if (lcd_revision == LCD_VERSION_2) {
 520                 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
 521                 reg |= ((height - 1) & 0x400) << 16;
 522                 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
 523         }
 524
 525         /* Set the Raster Order of the Frame Buffer */
 526         reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
 527         if (raster_order)
 528                 reg |= LCD_RASTER_ORDER;
 529
 530         if (bpp == 24)
 531                 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
 532         else if (bpp == 32)
 533                 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
 534                                 | LCD_V2_TFT_24BPP_UNPACK);
 535
 536         lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
 537
 538         switch (bpp) {
 539         case 1:
 540         case 2:
 541         case 4:
 542         case 16:
 543         case 24:
 544         case 32:
 545                 par->palette_sz = 16 * 2;
 546                 break;
 547
 548         case 8:
 549                 par->palette_sz = 256 * 2;
 550                 break;
 551
 552         default:
 553                 return -EINVAL;
 554         }
 555
 556         return 0;
 557 }
 558
 559 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 560                               unsigned blue, unsigned transp,
 561                               struct fb_info *info)
 562 {
 563         struct da8xx_fb_par *par = info->par;
 564         unsigned short *palette = (unsigned short *) par->v_palette_base;
 565         u_short pal;
 566         int update_hw = 0;
 567
 568         if (regno > 255)
 569                 return 1;
 570
 571         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
 572                 return 1;
 573
 574         if (info->var.bits_per_pixel == 8) {
 575                 red >>= 4;
 576                 green >>= 8;
 577                 blue >>= 12;
 578
 579                 pal = (red & 0x0f00);
 580                 pal |= (green & 0x00f0);
 581                 pal |= (blue & 0x000f);
 582
 583                 if (palette[regno] != pal) {
 584                         update_hw = 1;
 585                         palette[regno] = pal;
 586                 }
 587         } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
 588                 red >>= (16 - info->var.red.length);
 589                 red <<= info->var.red.offset;
 590
 591                 green >>= (16 - info->var.green.length);
 592                 green <<= info->var.green.offset;
 593
 594                 blue >>= (16 - info->var.blue.length);
 595                 blue <<= info->var.blue.offset;
 596
 597                 par->pseudo_palette[regno] = red | green | blue;
 598
 599                 if (palette[0] != 0x4000) {
 600                         update_hw = 1;
 601                         palette[0] = 0x4000;
 602                 }
 603         } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
 604                    ((info->var.bits_per_pixel == 24) && regno < 24)) {
 605                 red >>= (24 - info->var.red.length);
 606                 red <<= info->var.red.offset;
 607
 608                 green >>= (24 - info->var.green.length);
 609                 green <<= info->var.green.offset;
 610
 611                 blue >>= (24 - info->var.blue.length);
 612                 blue <<= info->var.blue.offset;
 613
 614                 par->pseudo_palette[regno] = red | green | blue;
 615
 616                 if (palette[0] != 0x4000) {
 617                         update_hw = 1;
 618                         palette[0] = 0x4000;
 619                 }
 620         }
 621
 622         /* Update the palette in the h/w as needed. */
 623         if (update_hw)
 624                 lcd_blit(LOAD_PALETTE, par);
 625
 626         return 0;
 627 }
 628
 629 static void lcd_reset(struct da8xx_fb_par *par)
 630 {
 631         /* Disable the Raster if previously Enabled */
 632         lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
 633
 634         /* DMA has to be disabled */
 635         lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
 636         lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
 637
 638         if (lcd_revision == LCD_VERSION_2) {
 639                 lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
 640                 /* Write 1 to reset */
 641                 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
 642                 lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
 643         }
 644 }
 645
 646 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
 647 {
 648         unsigned int lcd_clk, div;
 649
 650         /* Get clock from sysclk2 */
 651         lcd_clk = clk_get(2);
 652
 653         div = lcd_clk / par->pxl_clk;
 654         debug("LCD Clock: %d Divider: %d PixClk: %d\n",
 655               lcd_clk, div, par->pxl_clk);
 656
 657         /* Configure the LCD clock divisor. */
 658         lcdc_write(LCD_CLK_DIVISOR(div) |
 659                         (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
 660
 661         if (lcd_revision == LCD_VERSION_2)
 662                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
 663                                 LCD_V2_CORE_CLK_EN,
 664                                 &da8xx_fb_reg_base->clk_ena);
 665 }
 666
 667 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
 668                 const struct da8xx_panel *panel)
 669 {
 670         u32 bpp;
 671         int ret = 0;
 672
 673         lcd_reset(par);
 674
 675         /* Calculate the divider */
 676         lcd_calc_clk_divider(par);
 677
 678         if (panel->invert_pxl_clk)
 679                 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
 680                         LCD_INVERT_PIXEL_CLOCK),
 681                          &da8xx_fb_reg_base->raster_timing_2);
 682         else
 683                 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
 684                         ~LCD_INVERT_PIXEL_CLOCK),
 685                         &da8xx_fb_reg_base->raster_timing_2);
 686
 687         /* Configure the DMA burst size. */
 688         ret = lcd_cfg_dma(cfg->dma_burst_sz);
 689         if (ret < 0)
 690                 return ret;
 691
 692         /* Configure the AC bias properties. */
 693         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
 694
 695         /* Configure the vertical and horizontal sync properties. */
 696         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
 697         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
 698
 699         /* Configure for display */
 700         ret = lcd_cfg_display(cfg);
 701         if (ret < 0)
 702                 return ret;
 703
 704         if ((QVGA != cfg->p_disp_panel->panel_type) &&
 705             (WVGA != cfg->p_disp_panel->panel_type))
 706                 return -EINVAL;
 707
 708         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
 709             cfg->bpp >= cfg->p_disp_panel->min_bpp)
 710                 bpp = cfg->bpp;
 711         else
 712                 bpp = cfg->p_disp_panel->max_bpp;
 713         if (bpp == 12)
 714                 bpp = 16;
 715         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
 716                                 (unsigned int)panel->height, bpp,
 717                                 cfg->raster_order);
 718         if (ret < 0)
 719                 return ret;
 720
 721         /* Configure FDD */
 722         lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
 723                        (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
 724
 725         return 0;
 726 }
 727
 728 static void lcdc_dma_start(void)
 729 {
 730         struct da8xx_fb_par *par = da8xx_fb_info->par;
 731         lcdc_write(par->dma_start,
 732                 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 733         lcdc_write(par->dma_end,
 734                 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 735         lcdc_write(0,
 736                 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
 737         lcdc_write(0,
 738                 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
 739 }
 740
 741 static u32 lcdc_irq_handler_rev01(void)
 742 {
 743         struct da8xx_fb_par *par = da8xx_fb_info->par;
 744         u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
 745         u32 reg_ras;
 746
 747         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 748                 debug("LCD_SYNC_LOST\n");
 749                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
 750                 lcdc_write(stat, &da8xx_fb_reg_base->stat);
 751                 lcd_enable_raster();
 752                 return LCD_SYNC_LOST;
 753         } else if (stat & LCD_PL_LOAD_DONE) {
 754                 debug("LCD_PL_LOAD_DONE\n");
 755                 /*
 756                  * Must disable raster before changing state of any control bit.
 757                  * And also must be disabled before clearing the PL loading
 758                  * interrupt via the following write to the status register. If
 759                  * this is done after then one gets multiple PL done interrupts.
 760                  */
 761                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
 762
 763                 lcdc_write(stat, &da8xx_fb_reg_base->stat);
 764
 765                 /* Disable PL completion interrupt */
 766                 reg_ras  = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
 767                 reg_ras &= ~LCD_V1_PL_INT_ENA;
 768                 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
 769
 770                 /* Setup and start data loading mode */
 771                 lcd_blit(LOAD_DATA, par);
 772                 return LCD_PL_LOAD_DONE;
 773         } else {
 774                 lcdc_write(stat, &da8xx_fb_reg_base->stat);
 775
 776                 if (stat & LCD_END_OF_FRAME0)
 777                         debug("LCD_END_OF_FRAME0\n");
 778
 779                 lcdc_write(par->dma_start,
 780                         &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 781                 lcdc_write(par->dma_end,
 782                         &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 783                 par->vsync_flag = 1;
 784                 return LCD_END_OF_FRAME0;
 785         }
 786         return stat;
 787 }
 788
 789 static u32 lcdc_irq_handler_rev02(void)
 790 {
 791         struct da8xx_fb_par *par = da8xx_fb_info->par;
 792         u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
 793         u32 reg_int;
 794
 795         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 796                 debug("LCD_SYNC_LOST\n");
 797                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
 798                 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
 799                 lcd_enable_raster();
 800                 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
 801                 return LCD_SYNC_LOST;
 802         } else if (stat & LCD_PL_LOAD_DONE) {
 803                 debug("LCD_PL_LOAD_DONE\n");
 804                 /*
 805                  * Must disable raster before changing state of any control bit.
 806                  * And also must be disabled before clearing the PL loading
 807                  * interrupt via the following write to the status register. If
 808                  * this is done after then one gets multiple PL done interrupts.
 809                  */
 810                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
 811
 812                 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
 813
 814                 /* Disable PL completion interrupt */
 815                 reg_int  = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
 816                         (LCD_V2_PL_INT_ENA);
 817                 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
 818
 819                 /* Setup and start data loading mode */
 820                 lcd_blit(LOAD_DATA, par);
 821                 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
 822                 return LCD_PL_LOAD_DONE;
 823         } else {
 824                 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
 825
 826                 if (stat & LCD_END_OF_FRAME0)
 827                         debug("LCD_END_OF_FRAME0\n");
 828
 829                 lcdc_write(par->dma_start,
 830                            &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
 831                 lcdc_write(par->dma_end,
 832                            &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
 833                 par->vsync_flag = 1;
 834                 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
 835                 return LCD_END_OF_FRAME0;
 836         }
 837         lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
 838         return stat;
 839 }
 840
 841 static u32 lcdc_irq_handler(void)
 842 {
 843         if (lcd_revision == LCD_VERSION_1)
 844                 return lcdc_irq_handler_rev01();
 845         else
 846                 return lcdc_irq_handler_rev02();
 847 }
 848
 849 static u32 wait_for_event(u32 event)
 850 {
 851         u32 timeout = 50000;
 852         u32 ret;
 853
 854         do {
 855                 ret = lcdc_irq_handler();
 856                 udelay(1000);
 857                 --timeout;
 858         } while (!(ret & event) && timeout);
 859
 860         if (!(ret & event)) {
 861                 printf("%s: event %d not hit\n", __func__, event);
 862                 return -1;
 863         }
 864
 865         return 0;
 866
 867 }
 868
 869 void *video_hw_init(void)
 870 {
 871         struct da8xx_fb_par *par;
 872         u32 size;
 873         u32 rev;
 874         char *p;
 875
 876         if (!lcd_panel) {
 877                 printf("Display not initialized\n");
 878                 return NULL;
 879         }
 880         gpanel.winSizeX = lcd_panel->width;
 881         gpanel.winSizeY = lcd_panel->height;
 882         gpanel.plnSizeX = lcd_panel->width;
 883         gpanel.plnSizeY = lcd_panel->height;
 884
 885         switch (bits_x_pixel) {
 886         case 32:
 887                 gpanel.gdfBytesPP = 4;
 888                 gpanel.gdfIndex = GDF_32BIT_X888RGB;
 889                 break;
 890         case 24:
 891                 gpanel.gdfBytesPP = 4;
 892                 gpanel.gdfIndex = GDF_32BIT_X888RGB;
 893                 break;
 894         case 16:
 895                 gpanel.gdfBytesPP = 2;
 896                 gpanel.gdfIndex = GDF_16BIT_565RGB;
 897                 break;
 898         default:
 899                 gpanel.gdfBytesPP = 1;
 900                 gpanel.gdfIndex = GDF__8BIT_INDEX;
 901                 break;
 902         }
 903
 904         da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
 905
 906         /* Determine LCD IP Version */
 907         rev = lcdc_read(&da8xx_fb_reg_base->revid);
 908         switch (rev) {
 909         case 0x4C100102:
 910                 lcd_revision = LCD_VERSION_1;
 911                 break;
 912         case 0x4F200800:
 913         case 0x4F201000:
 914                 lcd_revision = LCD_VERSION_2;
 915                 break;
 916         default:
 917                 printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
 918                        rev);
 919                 lcd_revision = LCD_VERSION_1;
 920                 break;
 921         }
 922
 923         debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
 924               gpanel.winSizeX,
 925               gpanel.winSizeY,
 926               da8xx_lcd_cfg->bpp);
 927
 928         size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
 929         da8xx_fb_info = malloc_cache_aligned(size);
 930         debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
 931
 932         if (!da8xx_fb_info) {
 933                 printf("Memory allocation failed for fb_info\n");
 934                 return NULL;
 935         }
 936         memset(da8xx_fb_info, 0, size);
 937         p = (char *)da8xx_fb_info;
 938         da8xx_fb_info->par = p +  sizeof(struct fb_info);
 939         debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
 940
 941         par = da8xx_fb_info->par;
 942         par->pxl_clk = lcd_panel->pxl_clk;
 943
 944         if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
 945                 printf("lcd_init failed\n");
 946                 goto err_release_fb;
 947         }
 948
 949         /* allocate frame buffer */
 950         par->vram_size = lcd_panel->width * lcd_panel->height *
 951                         da8xx_lcd_cfg->bpp;
 952         par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
 953
 954         par->vram_virt = malloc_cache_aligned(par->vram_size);
 955
 956         par->vram_phys = (dma_addr_t) par->vram_virt;
 957         debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
 958                 (unsigned int)par->vram_size,
 959                 (unsigned int)par->vram_virt);
 960         if (!par->vram_virt) {
 961                 printf("GLCD: malloc for frame buffer failed\n");
 962                 goto err_release_fb;
 963         }
 964         gd->fb_base = (int)par->vram_virt;
 965
 966         gpanel.frameAdrs = (unsigned int)par->vram_virt;
 967         da8xx_fb_info->screen_base = (char *) par->vram_virt;
 968         da8xx_fb_fix.smem_start = gpanel.frameAdrs;
 969         da8xx_fb_fix.smem_len = par->vram_size;
 970         da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
 971
 972         par->dma_start = par->vram_phys;
 973         par->dma_end   = par->dma_start + lcd_panel->height *
 974                 da8xx_fb_fix.line_length - 1;
 975
 976         /* allocate palette buffer */
 977         par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE);
 978         if (!par->v_palette_base) {
 979                 printf("GLCD: malloc for palette buffer failed\n");
 980                 goto err_release_fb_mem;
 981         }
 982         memset(par->v_palette_base, 0, PALETTE_SIZE);
 983         par->p_palette_base = (unsigned int)par->v_palette_base;
 984
 985         /* Initialize par */
 986         da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
 987
 988         da8xx_fb_var.xres = lcd_panel->width;
 989         da8xx_fb_var.xres_virtual = lcd_panel->width;
 990
 991         da8xx_fb_var.yres         = lcd_panel->height;
 992         da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
 993
 994         da8xx_fb_var.grayscale =
 995             da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
 996         da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
 997
 998         da8xx_fb_var.hsync_len = lcd_panel->hsw;
 999         da8xx_fb_var.vsync_len = lcd_panel->vsw;
1000
1001         /* Initialize fbinfo */
1002         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1003         da8xx_fb_info->fix = da8xx_fb_fix;
1004         da8xx_fb_info->var = da8xx_fb_var;
1005         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1006         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1007                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1008
1009         /* Clear interrupt */
1010         memset((void *)par->vram_virt, 0, par->vram_size);
1011         lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
1012         if (lcd_revision == LCD_VERSION_1)
1013                 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
1014         else
1015                 lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
1016         debug("Palette at 0x%x size %d\n", par->p_palette_base,
1017                 par->palette_sz);
1018         lcdc_dma_start();
1019
1020         /* Load a default palette */
1021         fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
1022
1023         /* Check that the palette is loaded */
1024         wait_for_event(LCD_PL_LOAD_DONE);
1025
1026         /* Wait until DMA is working */
1027         wait_for_event(LCD_END_OF_FRAME0);
1028
1029         return (void *)&gpanel;
1030
1031 err_release_fb_mem:
1032         free(par->vram_virt);
1033
1034 err_release_fb:
1035         free(da8xx_fb_info);
1036
1037         return NULL;
1038 }
1039
1040 void da8xx_video_init(const struct da8xx_panel *panel,
1041                       const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
1042 {
1043         lcd_panel = panel;
1044         da8xx_lcd_cfg = lcd_cfg;
1045         bits_x_pixel = bits_pixel;
1046 }