drivers/video/broadwell_igd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * From coreboot src/soc/intel/broadwell/igd.c
   4  *
   5  * Copyright (C) 2016 Google, Inc
   6  */
   7
   8 #include <common.h>
   9 #include <bios_emul.h>
  10 #include <bootstage.h>
  11 #include <dm.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <vbe.h>
  15 #include <video.h>
  16 #include <asm/cpu.h>
  17 #include <asm/intel_regs.h>
  18 #include <asm/io.h>
  19 #include <asm/mtrr.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/iomap.h>
  22 #include <asm/arch/pch.h>
  23 #include <linux/delay.h>
  24 #include "i915_reg.h"
  25
  26 struct broadwell_igd_priv {
  27         u8 *regs;
  28 };
  29
  30 struct broadwell_igd_plat {
  31         u32 dp_hotplug[3];
  32
  33         int port_select;
  34         int power_up_delay;
  35         int power_backlight_on_delay;
  36         int power_down_delay;
  37         int power_backlight_off_delay;
  38         int power_cycle_delay;
  39         int cpu_backlight;
  40         int pch_backlight;
  41         int cdclk;
  42         int pre_graphics_delay;
  43 };
  44
  45 #define GT_RETRY                1000
  46 #define GT_CDCLK_337            0
  47 #define GT_CDCLK_450            1
  48 #define GT_CDCLK_540            2
  49 #define GT_CDCLK_675            3
  50
  51 u32 board_map_oprom_vendev(u32 vendev)
  52 {
  53         return SA_IGD_OPROM_VENDEV;
  54 }
  55
  56 static int poll32(u8 *addr, uint mask, uint value)
  57 {
  58         ulong start;
  59
  60         start = get_timer(0);
  61         debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
  62         while ((readl(addr) & mask) != value) {
  63                 if (get_timer(start) > GT_RETRY) {
  64                         debug("poll32: timeout: %x\n", readl(addr));
  65                         return -ETIMEDOUT;
  66                 }
  67         }
  68
  69         return 0;
  70 }
  71
  72 static int haswell_early_init(struct udevice *dev)
  73 {
  74         struct broadwell_igd_priv *priv = dev_get_priv(dev);
  75         u8 *regs = priv->regs;
  76         int ret;
  77
  78         /* Enable Force Wake */
  79         writel(0x00000020, regs + 0xa180);
  80         writel(0x00010001, regs + 0xa188);
  81         ret = poll32(regs + 0x130044, 1, 1);
  82         if (ret)
  83                 goto err;
  84
  85         /* Enable Counters */
  86         setbits_le32(regs + 0xa248, 0x00000016);
  87
  88         /* GFXPAUSE settings */
  89         writel(0x00070020, regs + 0xa000);
  90
  91         /* ECO Settings */
  92         clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
  93
  94         /* Enable DOP Clock Gating */
  95         writel(0x000003fd, regs + 0x9424);
  96
  97         /* Enable Unit Level Clock Gating */
  98         writel(0x00000080, regs + 0x9400);
  99         writel(0x40401000, regs + 0x9404);
 100         writel(0x00000000, regs + 0x9408);
 101         writel(0x02000001, regs + 0x940c);
 102
 103         /*
 104          * RC6 Settings
 105          */
 106
 107         /* Wake Rate Limits */
 108         setbits_le32(regs + 0xa090, 0x00000000);
 109         setbits_le32(regs + 0xa098, 0x03e80000);
 110         setbits_le32(regs + 0xa09c, 0x00280000);
 111         setbits_le32(regs + 0xa0a8, 0x0001e848);
 112         setbits_le32(regs + 0xa0ac, 0x00000019);
 113
 114         /* Render/Video/Blitter Idle Max Count */
 115         writel(0x0000000a, regs + 0x02054);
 116         writel(0x0000000a, regs + 0x12054);
 117         writel(0x0000000a, regs + 0x22054);
 118         writel(0x0000000a, regs + 0x1a054);
 119
 120         /* RC Sleep / RCx Thresholds */
 121         setbits_le32(regs + 0xa0b0, 0x00000000);
 122         setbits_le32(regs + 0xa0b4, 0x000003e8);
 123         setbits_le32(regs + 0xa0b8, 0x0000c350);
 124
 125         /* RP Settings */
 126         setbits_le32(regs + 0xa010, 0x000f4240);
 127         setbits_le32(regs + 0xa014, 0x12060000);
 128         setbits_le32(regs + 0xa02c, 0x0000e808);
 129         setbits_le32(regs + 0xa030, 0x0003bd08);
 130         setbits_le32(regs + 0xa068, 0x000101d0);
 131         setbits_le32(regs + 0xa06c, 0x00055730);
 132         setbits_le32(regs + 0xa070, 0x0000000a);
 133
 134         /* RP Control */
 135         writel(0x00000b92, regs + 0xa024);
 136
 137         /* HW RC6 Control */
 138         writel(0x88040000, regs + 0xa090);
 139
 140         /* Video Frequency Request */
 141         writel(0x08000000, regs + 0xa00c);
 142
 143         /* Set RC6 VIDs */
 144         ret = poll32(regs + 0x138124, (1 << 31), 0);
 145         if (ret)
 146                 goto err;
 147         writel(0, regs + 0x138128);
 148         writel(0x80000004, regs + 0x138124);
 149         ret = poll32(regs + 0x138124, (1 << 31), 0);
 150         if (ret)
 151                 goto err;
 152
 153         /* Enable PM Interrupts */
 154         writel(0x03000076, regs + 0x4402c);
 155
 156         /* Enable RC6 in idle */
 157         writel(0x00040000, regs + 0xa094);
 158
 159         return 0;
 160 err:
 161         debug("%s: ret=%d\n", __func__, ret);
 162         return ret;
 163 };
 164
 165 static int haswell_late_init(struct udevice *dev)
 166 {
 167         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 168         u8 *regs = priv->regs;
 169         int ret;
 170
 171         /* Lock settings */
 172         setbits_le32(regs + 0x0a248, (1 << 31));
 173         setbits_le32(regs + 0x0a004, (1 << 4));
 174         setbits_le32(regs + 0x0a080, (1 << 2));
 175         setbits_le32(regs + 0x0a180, (1 << 31));
 176
 177         /* Disable Force Wake */
 178         writel(0x00010000, regs + 0xa188);
 179         ret = poll32(regs + 0x130044, 1, 0);
 180         if (ret)
 181                 goto err;
 182         writel(0x00000001, regs + 0xa188);
 183
 184         /* Enable power well for DP and Audio */
 185         setbits_le32(regs + 0x45400, (1 << 31));
 186         ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
 187         if (ret)
 188                 goto err;
 189
 190         return 0;
 191 err:
 192         debug("%s: ret=%d\n", __func__, ret);
 193         return ret;
 194 };
 195
 196 static int broadwell_early_init(struct udevice *dev)
 197 {
 198         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 199         u8 *regs = priv->regs;
 200         int ret;
 201
 202         /* Enable Force Wake */
 203         writel(0x00010001, regs + 0xa188);
 204         ret = poll32(regs + 0x130044, 1, 1);
 205         if (ret)
 206                 goto err;
 207
 208         /* Enable push bus metric control and shift */
 209         writel(0x00000004, regs + 0xa248);
 210         writel(0x000000ff, regs + 0xa250);
 211         writel(0x00000010, regs + 0xa25c);
 212
 213         /* GFXPAUSE settings (set based on stepping) */
 214
 215         /* ECO Settings */
 216         writel(0x45200000, regs + 0xa180);
 217
 218         /* Enable DOP Clock Gating */
 219         writel(0x000000fd, regs + 0x9424);
 220
 221         /* Enable Unit Level Clock Gating */
 222         writel(0x00000000, regs + 0x9400);
 223         writel(0x40401000, regs + 0x9404);
 224         writel(0x00000000, regs + 0x9408);
 225         writel(0x02000001, regs + 0x940c);
 226         writel(0x0000000a, regs + 0x1a054);
 227
 228         /* Video Frequency Request */
 229         writel(0x08000000, regs + 0xa00c);
 230
 231         writel(0x00000009, regs + 0x138158);
 232         writel(0x0000000d, regs + 0x13815c);
 233
 234         /*
 235          * RC6 Settings
 236          */
 237
 238         /* Wake Rate Limits */
 239         clrsetbits_le32(regs + 0x0a090, ~0, 0);
 240         setbits_le32(regs + 0x0a098, 0x03e80000);
 241         setbits_le32(regs + 0x0a09c, 0x00280000);
 242         setbits_le32(regs + 0x0a0a8, 0x0001e848);
 243         setbits_le32(regs + 0x0a0ac, 0x00000019);
 244
 245         /* Render/Video/Blitter Idle Max Count */
 246         writel(0x0000000a, regs + 0x02054);
 247         writel(0x0000000a, regs + 0x12054);
 248         writel(0x0000000a, regs + 0x22054);
 249
 250         /* RC Sleep / RCx Thresholds */
 251         setbits_le32(regs + 0x0a0b0, 0x00000000);
 252         setbits_le32(regs + 0x0a0b8, 0x00000271);
 253
 254         /* RP Settings */
 255         setbits_le32(regs + 0x0a010, 0x000f4240);
 256         setbits_le32(regs + 0x0a014, 0x12060000);
 257         setbits_le32(regs + 0x0a02c, 0x0000e808);
 258         setbits_le32(regs + 0x0a030, 0x0003bd08);
 259         setbits_le32(regs + 0x0a068, 0x000101d0);
 260         setbits_le32(regs + 0x0a06c, 0x00055730);
 261         setbits_le32(regs + 0x0a070, 0x0000000a);
 262         setbits_le32(regs + 0x0a168, 0x00000006);
 263
 264         /* RP Control */
 265         writel(0x00000b92, regs + 0xa024);
 266
 267         /* HW RC6 Control */
 268         writel(0x90040000, regs + 0xa090);
 269
 270         /* Set RC6 VIDs */
 271         ret = poll32(regs + 0x138124, (1 << 31), 0);
 272         if (ret)
 273                 goto err;
 274         writel(0, regs + 0x138128);
 275         writel(0x80000004, regs + 0x138124);
 276         ret = poll32(regs + 0x138124, (1 << 31), 0);
 277         if (ret)
 278                 goto err;
 279
 280         /* Enable PM Interrupts */
 281         writel(0x03000076, regs + 0x4402c);
 282
 283         /* Enable RC6 in idle */
 284         writel(0x00040000, regs + 0xa094);
 285
 286         return 0;
 287 err:
 288         debug("%s: ret=%d\n", __func__, ret);
 289         return ret;
 290 }
 291
 292 static int broadwell_late_init(struct udevice *dev)
 293 {
 294         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 295         u8 *regs = priv->regs;
 296         int ret;
 297
 298         /* Lock settings */
 299         setbits_le32(regs + 0x0a248, 1 << 31);
 300         setbits_le32(regs + 0x0a000, 1 << 18);
 301         setbits_le32(regs + 0x0a180, 1 << 31);
 302
 303         /* Disable Force Wake */
 304         writel(0x00010000, regs + 0xa188);
 305         ret = poll32(regs + 0x130044, 1, 0);
 306         if (ret)
 307                 goto err;
 308
 309         /* Enable power well for DP and Audio */
 310         setbits_le32(regs + 0x45400, 1 << 31);
 311         ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
 312         if (ret)
 313                 goto err;
 314
 315         return 0;
 316 err:
 317         debug("%s: ret=%d\n", __func__, ret);
 318         return ret;
 319 };
 320
 321
 322 static unsigned long gtt_read(struct broadwell_igd_priv *priv,
 323                               unsigned long reg)
 324 {
 325         return readl(priv->regs + reg);
 326 }
 327
 328 static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
 329                       unsigned long data)
 330 {
 331         writel(data, priv->regs + reg);
 332 }
 333
 334 static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
 335                                   u32 bic, u32 or)
 336 {
 337         clrsetbits_le32(priv->regs + reg, bic, or);
 338 }
 339
 340 static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
 341                     u32 value)
 342 {
 343         unsigned try = GT_RETRY;
 344         u32 data;
 345
 346         while (try--) {
 347                 data = gtt_read(priv, reg);
 348                 if ((data & mask) == value)
 349                         return 0;
 350                 udelay(10);
 351         }
 352
 353         debug("GT init timeout\n");
 354         return -ETIMEDOUT;
 355 }
 356
 357 static void igd_setup_panel(struct udevice *dev)
 358 {
 359         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 360         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 361         u32 reg32;
 362
 363         /* Setup Digital Port Hotplug */
 364         reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
 365         reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
 366         reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
 367         gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
 368
 369         /* Setup Panel Power On Delays */
 370         reg32 = (plat->port_select & 0x3) << 30;
 371         reg32 |= (plat->power_up_delay & 0x1fff) << 16;
 372         reg32 |= (plat->power_backlight_on_delay & 0x1fff);
 373         gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
 374
 375         /* Setup Panel Power Off Delays */
 376         reg32 = (plat->power_down_delay & 0x1fff) << 16;
 377         reg32 |= (plat->power_backlight_off_delay & 0x1fff);
 378         gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
 379
 380         /* Setup Panel Power Cycle Delay */
 381         if (plat->power_cycle_delay) {
 382                 reg32 = gtt_read(priv, PCH_PP_DIVISOR);
 383                 reg32 &= ~0xff;
 384                 reg32 |= plat->power_cycle_delay & 0xff;
 385                 gtt_write(priv, PCH_PP_DIVISOR, reg32);
 386         }
 387
 388         /* Enable Backlight if needed */
 389         if (plat->cpu_backlight) {
 390                 gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
 391                 gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
 392         }
 393         if (plat->pch_backlight) {
 394                 gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
 395                 gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
 396         }
 397 }
 398
 399 static int igd_cdclk_init_haswell(struct udevice *dev)
 400 {
 401         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 402         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 403         int cdclk = plat->cdclk;
 404         u16 devid;
 405         int gpu_is_ulx = 0;
 406         u32 dpdiv, lpcll;
 407         int ret;
 408
 409         dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
 410
 411         /* Check for ULX GT1 or GT2 */
 412         if (devid == 0x0a0e || devid == 0x0a1e)
 413                 gpu_is_ulx = 1;
 414
 415         /* 675MHz is not supported on haswell */
 416         if (cdclk == GT_CDCLK_675)
 417                 cdclk = GT_CDCLK_337;
 418
 419         /* If CD clock is fixed or ULT then set to 450MHz */
 420         if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
 421                 cdclk = GT_CDCLK_450;
 422
 423         /* 540MHz is not supported on ULX */
 424         if (gpu_is_ulx && cdclk == GT_CDCLK_540)
 425                 cdclk = GT_CDCLK_337;
 426
 427         /* 337.5MHz is not supported on non-ULT/ULX */
 428         if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
 429                 cdclk = GT_CDCLK_450;
 430
 431         /* Set variables based on CD Clock setting */
 432         switch (cdclk) {
 433         case GT_CDCLK_337:
 434                 dpdiv = 169;
 435                 lpcll = (1 << 26);
 436                 break;
 437         case GT_CDCLK_450:
 438                 dpdiv = 225;
 439                 lpcll = 0;
 440                 break;
 441         case GT_CDCLK_540:
 442                 dpdiv = 270;
 443                 lpcll = (1 << 26);
 444                 break;
 445         default:
 446                 ret = -EDOM;
 447                 goto err;
 448         }
 449
 450         /* Set LPCLL_CTL CD Clock Frequency Select */
 451         gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
 452
 453         /* ULX: Inform power controller of selected frequency */
 454         if (gpu_is_ulx) {
 455                 if (cdclk == GT_CDCLK_450)
 456                         gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
 457                 else
 458                         gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
 459                 gtt_write(priv, 0x13812c, 0x00000000);
 460                 gtt_write(priv, 0x138124, 0x80000017);
 461         }
 462
 463         /* Set CPU DP AUX 2X bit clock dividers */
 464         gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
 465         gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
 466
 467         return 0;
 468 err:
 469         debug("%s: ret=%d\n", __func__, ret);
 470         return ret;
 471 }
 472
 473 static int igd_cdclk_init_broadwell(struct udevice *dev)
 474 {
 475         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 476         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 477         int cdclk = plat->cdclk;
 478         u32 dpdiv, lpcll, pwctl, cdset;
 479         int ret;
 480
 481         /* Inform power controller of upcoming frequency change */
 482         gtt_write(priv, 0x138128, 0);
 483         gtt_write(priv, 0x13812c, 0);
 484         gtt_write(priv, 0x138124, 0x80000018);
 485
 486         /* Poll GT driver mailbox for run/busy clear */
 487         if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
 488                 cdclk = GT_CDCLK_450;
 489
 490         if (gtt_read(priv, 0x42014) & 0x1000000) {
 491                 /* If CD clock is fixed then set to 450MHz */
 492                 cdclk = GT_CDCLK_450;
 493         } else {
 494                 /* Program CD clock to highest supported freq */
 495                 if (cpu_is_ult())
 496                         cdclk = GT_CDCLK_540;
 497                 else
 498                         cdclk = GT_CDCLK_675;
 499         }
 500
 501         /* CD clock frequency 675MHz not supported on ULT */
 502         if (cpu_is_ult() && cdclk == GT_CDCLK_675)
 503                 cdclk = GT_CDCLK_540;
 504
 505         /* Set variables based on CD Clock setting */
 506         switch (cdclk) {
 507         case GT_CDCLK_337:
 508                 cdset = 337;
 509                 lpcll = (1 << 27);
 510                 pwctl = 2;
 511                 dpdiv = 169;
 512                 break;
 513         case GT_CDCLK_450:
 514                 cdset = 449;
 515                 lpcll = 0;
 516                 pwctl = 0;
 517                 dpdiv = 225;
 518                 break;
 519         case GT_CDCLK_540:
 520                 cdset = 539;
 521                 lpcll = (1 << 26);
 522                 pwctl = 1;
 523                 dpdiv = 270;
 524                 break;
 525         case GT_CDCLK_675:
 526                 cdset = 674;
 527                 lpcll = (1 << 26) | (1 << 27);
 528                 pwctl = 3;
 529                 dpdiv = 338;
 530                 break;
 531         default:
 532                 ret = -EDOM;
 533                 goto err;
 534         }
 535         debug("%s: frequency = %d\n", __func__, cdclk);
 536
 537         /* Set LPCLL_CTL CD Clock Frequency Select */
 538         gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
 539
 540         /* Inform power controller of selected frequency */
 541         gtt_write(priv, 0x138128, pwctl);
 542         gtt_write(priv, 0x13812c, 0);
 543         gtt_write(priv, 0x138124, 0x80000017);
 544
 545         /* Program CD Clock Frequency */
 546         gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
 547
 548         /* Set CPU DP AUX 2X bit clock dividers */
 549         gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
 550         gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
 551
 552         return 0;
 553 err:
 554         debug("%s: ret=%d\n", __func__, ret);
 555         return ret;
 556 }
 557
 558 u8 systemagent_revision(struct udevice *bus)
 559 {
 560         ulong val;
 561
 562         pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
 563                             PCI_SIZE_32);
 564
 565         return val;
 566 }
 567
 568 static int igd_pre_init(struct udevice *dev, bool is_broadwell)
 569 {
 570         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 571         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 572         u32 rp1_gfx_freq;
 573         int ret;
 574
 575         mdelay(plat->pre_graphics_delay);
 576
 577         /* Early init steps */
 578         if (is_broadwell) {
 579                 ret = broadwell_early_init(dev);
 580                 if (ret)
 581                         goto err;
 582
 583                 /* Set GFXPAUSE based on stepping */
 584                 if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
 585                     systemagent_revision(pci_get_controller(dev)) <= 9) {
 586                         gtt_write(priv, 0xa000, 0x300ff);
 587                 } else {
 588                         gtt_write(priv, 0xa000, 0x30020);
 589                 }
 590         } else {
 591                 ret = haswell_early_init(dev);
 592                 if (ret)
 593                         goto err;
 594         }
 595
 596         /* Set RP1 graphics frequency */
 597         rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
 598         gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
 599
 600         /* Post VBIOS panel setup */
 601         igd_setup_panel(dev);
 602
 603         return 0;
 604 err:
 605         debug("%s: ret=%d\n", __func__, ret);
 606         return ret;
 607 }
 608
 609 static int igd_post_init(struct udevice *dev, bool is_broadwell)
 610 {
 611         int ret;
 612
 613         /* Late init steps */
 614         if (is_broadwell) {
 615                 ret = igd_cdclk_init_broadwell(dev);
 616                 if (ret)
 617                         return ret;
 618                 ret = broadwell_late_init(dev);
 619                 if (ret)
 620                         return ret;
 621         } else {
 622                 igd_cdclk_init_haswell(dev);
 623                 ret = haswell_late_init(dev);
 624                 if (ret)
 625                         return ret;
 626         }
 627
 628         return 0;
 629 }
 630
 631 static int broadwell_igd_int15_handler(void)
 632 {
 633         int res = 0;
 634
 635         debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
 636
 637         switch (M.x86.R_AX) {
 638         case 0x5f35:
 639                 /*
 640                  * Boot Display Device Hook:
 641                  *  bit 0 = CRT
 642                  *  bit 1 = TV (eDP)
 643                  *  bit 2 = EFP
 644                  *  bit 3 = LFP
 645                  *  bit 4 = CRT2
 646                  *  bit 5 = TV2 (eDP)
 647                  *  bit 6 = EFP2
 648                  *  bit 7 = LFP2
 649                  */
 650                 M.x86.R_AX = 0x005f;
 651                 M.x86.R_CX = 0x0000; /* Use video bios default */
 652                 res = 1;
 653                 break;
 654         default:
 655                 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
 656                 break;
 657         }
 658
 659         return res;
 660 }
 661
 662 static int broadwell_igd_probe(struct udevice *dev)
 663 {
 664         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 665         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 666         bool is_broadwell;
 667         int ret;
 668
 669         if (!ll_boot_init()) {
 670                 /*
 671                  * If we are running from EFI or coreboot, this driver can't
 672                  * work.
 673                  */
 674                 printf("Not available (previous bootloader prevents it)\n");
 675                 return -EPERM;
 676         }
 677         is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
 678         bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
 679         debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
 680         ret = igd_pre_init(dev, is_broadwell);
 681         if (!ret) {
 682                 ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
 683                 if (ret)
 684                         debug("failed to run video BIOS: %d\n", ret);
 685         }
 686         if (!ret)
 687                 ret = igd_post_init(dev, is_broadwell);
 688         bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
 689         if (ret)
 690                 return ret;
 691
 692         /* Use write-combining for the graphics memory, 256MB */
 693         ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20);
 694         if (!ret)
 695                 ret = mtrr_commit(true);
 696         if (ret && ret != -ENOSYS) {
 697                 printf("Failed to add MTRR: Display will be slow (err %d)\n",
 698                        ret);
 699         }
 700
 701         debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
 702               plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
 703
 704         return 0;
 705 }
 706
 707 static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
 708 {
 709         struct broadwell_igd_plat *plat = dev_get_platdata(dev);
 710         struct broadwell_igd_priv *priv = dev_get_priv(dev);
 711         int node = dev_of_offset(dev);
 712         const void *blob = gd->fdt_blob;
 713
 714         if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
 715                                  plat->dp_hotplug,
 716                                  ARRAY_SIZE(plat->dp_hotplug)))
 717                 return -EINVAL;
 718         plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
 719         plat->power_cycle_delay = fdtdec_get_int(blob, node,
 720                         "intel,power-cycle-delay", 0);
 721         plat->power_up_delay = fdtdec_get_int(blob, node,
 722                         "intel,power-up-delay", 0);
 723         plat->power_down_delay = fdtdec_get_int(blob, node,
 724                         "intel,power-down-delay", 0);
 725         plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
 726                         "intel,power-backlight-on-delay", 0);
 727         plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
 728                         "intel,power-backlight-off-delay", 0);
 729         plat->cpu_backlight = fdtdec_get_int(blob, node,
 730                         "intel,cpu-backlight", 0);
 731         plat->pch_backlight = fdtdec_get_int(blob, node,
 732                         "intel,pch-backlight", 0);
 733         plat->pre_graphics_delay = fdtdec_get_int(blob, node,
 734                         "intel,pre-graphics-delay", 0);
 735         priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
 736         debug("%s: regs at %p\n", __func__, priv->regs);
 737         debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
 738               plat->dp_hotplug[2]);
 739         debug("port_select = %d\n", plat->port_select);
 740         debug("power_up_delay = %d\n", plat->power_up_delay);
 741         debug("power_backlight_on_delay = %d\n",
 742               plat->power_backlight_on_delay);
 743         debug("power_down_delay = %d\n", plat->power_down_delay);
 744         debug("power_backlight_off_delay = %d\n",
 745               plat->power_backlight_off_delay);
 746         debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
 747         debug("cpu_backlight = %x\n", plat->cpu_backlight);
 748         debug("pch_backlight = %x\n", plat->pch_backlight);
 749         debug("cdclk = %d\n", plat->cdclk);
 750         debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
 751
 752         return 0;
 753 }
 754
 755 static const struct video_ops broadwell_igd_ops = {
 756 };
 757
 758 static const struct udevice_id broadwell_igd_ids[] = {
 759         { .compatible = "intel,broadwell-igd" },
 760         { }
 761 };
 762
 763 U_BOOT_DRIVER(broadwell_igd) = {
 764         .name   = "broadwell_igd",
 765         .id     = UCLASS_VIDEO,
 766         .of_match = broadwell_igd_ids,
 767         .ops    = &broadwell_igd_ops,
 768         .ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
 769         .probe  = broadwell_igd_probe,
 770         .priv_auto_alloc_size   = sizeof(struct broadwell_igd_priv),
 771         .platdata_auto_alloc_size       = sizeof(struct broadwell_igd_plat),
 772 };