drivers/video/atmel_lcdfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for AT91/AT32 LCD Controller
   4  *
   5  * Copyright (C) 2007 Atmel Corporation
   6  */
   7
   8 #include <common.h>
   9 #include <atmel_lcd.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <log.h>
  13 #include <part.h>
  14 #include <video.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/gpio.h>
  17 #include <asm/arch/clk.h>
  18 #include <lcd.h>
  19 #include <bmp_layout.h>
  20 #include <atmel_lcdc.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #ifdef CONFIG_DM_VIDEO
  25 enum {
  26         /* Maximum LCD size we support */
  27         LCD_MAX_WIDTH           = 1366,
  28         LCD_MAX_HEIGHT          = 768,
  29         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
  30 };
  31 #endif
  32
  33 struct atmel_fb_priv {
  34         struct display_timing timing;
  35 };
  36
  37 /* configurable parameters */
  38 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  39 #define ATMEL_LCDC_DMA_BURST_LEN        8
  40 #ifndef ATMEL_LCDC_GUARD_TIME
  41 #define ATMEL_LCDC_GUARD_TIME           1
  42 #endif
  43
  44 #if defined(CONFIG_AT91SAM9263)
  45 #define ATMEL_LCDC_FIFO_SIZE            2048
  46 #else
  47 #define ATMEL_LCDC_FIFO_SIZE            512
  48 #endif
  49
  50 #define lcdc_readl(mmio, reg)           __raw_readl((mmio)+(reg))
  51 #define lcdc_writel(mmio, reg, val)     __raw_writel((val), (mmio)+(reg))
  52
  53 #ifndef CONFIG_DM_VIDEO
  54 ushort *configuration_get_cmap(void)
  55 {
  56         return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  57 }
  58
  59 #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  60 void fb_put_word(uchar **fb, uchar **from)
  61 {
  62         *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  63         *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  64         *from += 2;
  65 }
  66 #endif
  67
  68 #ifdef CONFIG_LCD_LOGO
  69 #include <bmp_logo.h>
  70 void lcd_logo_set_cmap(void)
  71 {
  72         int i;
  73         uint lut_entry;
  74         ushort colreg;
  75         uint *cmap = (uint *)configuration_get_cmap();
  76
  77         for (i = 0; i < BMP_LOGO_COLORS; ++i) {
  78                 colreg = bmp_logo_palette[i];
  79 #ifdef CONFIG_ATMEL_LCD_BGR555
  80                 lut_entry = ((colreg & 0x000F) << 11) |
  81                                 ((colreg & 0x00F0) <<  2) |
  82                                 ((colreg & 0x0F00) >>  7);
  83 #else
  84                 lut_entry = ((colreg & 0x000F) << 1) |
  85                                 ((colreg & 0x00F0) << 3) |
  86                                 ((colreg & 0x0F00) << 4);
  87 #endif
  88                 *(cmap + BMP_LOGO_OFFSET) = lut_entry;
  89                 cmap++;
  90         }
  91 }
  92 #endif
  93
  94 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  95 {
  96 #if defined(CONFIG_ATMEL_LCD_BGR555)
  97         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  98                     (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  99 #else
 100         lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
 101                     (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
 102 #endif
 103 }
 104
 105 void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
 106 {
 107         int i;
 108
 109         for (i = 0; i < colors; ++i) {
 110                 struct bmp_color_table_entry cte = bmp->color_table[i];
 111                 lcd_setcolreg(i, cte.red, cte.green, cte.blue);
 112         }
 113 }
 114 #endif
 115
 116 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
 117                           bool tft, bool cont_pol_low, ulong lcdbase)
 118 {
 119         unsigned long value;
 120         void *reg = (void *)addr;
 121
 122         /* Turn off the LCD controller and the DMA controller */
 123         lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 124                     ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
 125
 126         /* Wait for the LCDC core to become idle */
 127         while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
 128                 udelay(10);
 129
 130         lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
 131
 132         /* Reset LCDC DMA */
 133         lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
 134
 135         /* ...set frame size and burst length = 8 words (?) */
 136         value = (timing->hactive.typ * timing->vactive.typ *
 137                  (1 << bpix)) / 32;
 138         value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
 139         lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
 140
 141         /* Set pixel clock */
 142         value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
 143         if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
 144                 value++;
 145         value = (value / 2) - 1;
 146
 147         if (!value) {
 148                 lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
 149         } else
 150                 lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
 151                             value << ATMEL_LCDC_CLKVAL_OFFSET);
 152
 153         /* Initialize control register 2 */
 154         value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
 155         if (tft)
 156                 value |= ATMEL_LCDC_DISTYPE_TFT;
 157
 158         if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
 159                 value |= ATMEL_LCDC_INVLINE_INVERTED;
 160         if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
 161                 value |= ATMEL_LCDC_INVFRAME_INVERTED;
 162         value |= bpix << 5;
 163         lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
 164
 165         /* Vertical timing */
 166         value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
 167         value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
 168         value |= timing->vfront_porch.typ;
 169         /* Magic! (Datasheet says "Bit 31 must be written to 1") */
 170         value |= 1U << 31;
 171         lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
 172
 173         /* Horizontal timing */
 174         value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
 175         value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
 176         value |= (timing->hback_porch.typ - 1);
 177         lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
 178
 179         /* Display size */
 180         value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
 181         value |= timing->vactive.typ - 1;
 182         lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
 183
 184         /* FIFO Threshold: Use formula from data sheet */
 185         value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
 186         lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
 187
 188         /* Toggle LCD_MODE every frame */
 189         lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
 190
 191         /* Disable all interrupts */
 192         lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
 193
 194         /* Set contrast */
 195         value = ATMEL_LCDC_PS_DIV8 |
 196                 ATMEL_LCDC_ENA_PWMENABLE;
 197         if (!cont_pol_low)
 198                 value |= ATMEL_LCDC_POL_POSITIVE;
 199         lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
 200         lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
 201
 202         /* Set framebuffer DMA base address and pixel offset */
 203         lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
 204
 205         lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
 206         lcdc_writel(reg, ATMEL_LCDC_PWRCON,
 207                     (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
 208 }
 209
 210 #ifndef CONFIG_DM_VIDEO
 211 void lcd_ctrl_init(void *lcdbase)
 212 {
 213         struct display_timing timing;
 214
 215         timing.flags = 0;
 216         if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
 217                 timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
 218         if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
 219                 timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
 220         timing.pixelclock.typ = panel_info.vl_clk;
 221
 222         timing.hactive.typ = panel_info.vl_col;
 223         timing.hfront_porch.typ = panel_info.vl_right_margin;
 224         timing.hback_porch.typ = panel_info.vl_left_margin;
 225         timing.hsync_len.typ = panel_info.vl_hsync_len;
 226
 227         timing.vactive.typ = panel_info.vl_row;
 228         timing.vfront_porch.typ = panel_info.vl_clk;
 229         timing.vback_porch.typ = panel_info.vl_clk;
 230         timing.vsync_len.typ = panel_info.vl_clk;
 231
 232         atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
 233                       panel_info.vl_tft, panel_info.vl_cont_pol_low,
 234                       (ulong)lcdbase);
 235 }
 236
 237 ulong calc_fbsize(void)
 238 {
 239         return ((panel_info.vl_col * panel_info.vl_row *
 240                 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
 241 }
 242 #endif
 243
 244 #ifdef CONFIG_DM_VIDEO
 245 static int atmel_fb_lcd_probe(struct udevice *dev)
 246 {
 247         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 248         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 249         struct atmel_fb_priv *priv = dev_get_priv(dev);
 250         struct display_timing *timing = &priv->timing;
 251
 252         /*
 253          * For now some values are hard-coded. We could use the device tree
 254          * bindings in simple-framebuffer.txt to specify the format/bpp and
 255          * some Atmel-specific binding for tft and cont_pol_low.
 256          */
 257         atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
 258                       uc_plat->base);
 259         uc_priv->xsize = timing->hactive.typ;
 260         uc_priv->ysize = timing->vactive.typ;
 261         uc_priv->bpix = VIDEO_BPP16;
 262         video_set_flush_dcache(dev, true);
 263         debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
 264               uc_plat->size, uc_priv->xsize, uc_priv->ysize);
 265
 266         return 0;
 267 }
 268
 269 static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
 270 {
 271         struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
 272         struct atmel_fb_priv *priv = dev_get_priv(dev);
 273         struct display_timing *timing = &priv->timing;
 274         const void *blob = gd->fdt_blob;
 275
 276         if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
 277                                          plat->timing_index, timing)) {
 278                 debug("%s: Failed to decode display timing\n", __func__);
 279                 return -EINVAL;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static int atmel_fb_lcd_bind(struct udevice *dev)
 286 {
 287         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 288
 289         uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 290                         (1 << VIDEO_BPP16) / 8;
 291         debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
 292
 293         return 0;
 294 }
 295
 296 static const struct udevice_id atmel_fb_lcd_ids[] = {
 297         { .compatible = "atmel,at91sam9g45-lcdc" },
 298         { }
 299 };
 300
 301 U_BOOT_DRIVER(atmel_fb) = {
 302         .name   = "atmel_fb",
 303         .id     = UCLASS_VIDEO,
 304         .of_match = atmel_fb_lcd_ids,
 305         .bind   = atmel_fb_lcd_bind,
 306         .ofdata_to_platdata     = atmel_fb_ofdata_to_platdata,
 307         .probe  = atmel_fb_lcd_probe,
 308         .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
 309         .priv_auto_alloc_size   = sizeof(struct atmel_fb_priv),
 310 };
 311 #endif