drivers/video/atmel_hlcdfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for AT91/AT32 MULTI LAYER LCD Controller
   4  *
   5  * Copyright (C) 2012 Atmel Corporation
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <malloc.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/gpio.h>
  13 #include <asm/arch/clk.h>
  14 #include <clk.h>
  15 #include <dm.h>
  16 #include <fdtdec.h>
  17 #include <lcd.h>
  18 #include <video.h>
  19 #include <wait_bit.h>
  20 #include <atmel_hlcdc.h>
  21
  22 #if defined(CONFIG_LCD_LOGO)
  23 #include <bmp_logo.h>
  24 #endif
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #ifndef CONFIG_DM_VIDEO
  29
  30 /* configurable parameters */
  31 #define ATMEL_LCDC_CVAL_DEFAULT         0xc8
  32 #define ATMEL_LCDC_DMA_BURST_LEN        8
  33 #ifndef ATMEL_LCDC_GUARD_TIME
  34 #define ATMEL_LCDC_GUARD_TIME           1
  35 #endif
  36
  37 #define ATMEL_LCDC_FIFO_SIZE            512
  38
  39 /*
  40  * the CLUT register map as following
  41  * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  42  */
  43 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  44 {
  45         writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
  46                ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
  47                | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
  48                | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
  49 }
  50
  51 ushort *configuration_get_cmap(void)
  52 {
  53 #if defined(CONFIG_LCD_LOGO)
  54         return bmp_logo_palette;
  55 #else
  56         return NULL;
  57 #endif
  58 }
  59
  60 void lcd_ctrl_init(void *lcdbase)
  61 {
  62         unsigned long value;
  63         struct lcd_dma_desc *desc;
  64         struct atmel_hlcd_regs *regs;
  65         int ret;
  66
  67         if (!has_lcdc())
  68                 return;     /* No lcdc */
  69
  70         regs = (struct atmel_hlcd_regs *)panel_info.mmio;
  71
  72         /* Disable DISP signal */
  73         writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  74         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  75                                 false, 1000, false);
  76         if (ret)
  77                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  78         /* Disable synchronization */
  79         writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  80         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  81                                 false, 1000, false);
  82         if (ret)
  83                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  84         /* Disable pixel clock */
  85         writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  86         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  87                                 false, 1000, false);
  88         if (ret)
  89                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  90         /* Disable PWM */
  91         writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  92         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  93                                 false, 1000, false);
  94         if (ret)
  95                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
  96
  97         /* Set pixel clock */
  98         value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  99         if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
 100                 value++;
 101
 102         if (value < 1) {
 103                 /* Using system clock as pixel clock */
 104                 writel(LCDC_LCDCFG0_CLKDIV(0)
 105                         | LCDC_LCDCFG0_CGDISHCR
 106                         | LCDC_LCDCFG0_CGDISHEO
 107                         | LCDC_LCDCFG0_CGDISOVR1
 108                         | LCDC_LCDCFG0_CGDISBASE
 109                         | panel_info.vl_clk_pol
 110                         | LCDC_LCDCFG0_CLKSEL,
 111                         &regs->lcdc_lcdcfg0);
 112
 113         } else {
 114                 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
 115                         | LCDC_LCDCFG0_CGDISHCR
 116                         | LCDC_LCDCFG0_CGDISHEO
 117                         | LCDC_LCDCFG0_CGDISOVR1
 118                         | LCDC_LCDCFG0_CGDISBASE
 119                         | panel_info.vl_clk_pol,
 120                         &regs->lcdc_lcdcfg0);
 121         }
 122
 123         /* Initialize control register 5 */
 124         value = 0;
 125
 126         value |= panel_info.vl_sync;
 127
 128 #ifndef LCD_OUTPUT_BPP
 129         /* Output is 24bpp */
 130         value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 131 #else
 132         switch (LCD_OUTPUT_BPP) {
 133         case 12:
 134                 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
 135                 break;
 136         case 16:
 137                 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
 138                 break;
 139         case 18:
 140                 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
 141                 break;
 142         case 24:
 143                 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 144                 break;
 145         default:
 146                 BUG();
 147                 break;
 148         }
 149 #endif
 150
 151         value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
 152         value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
 153         writel(value, &regs->lcdc_lcdcfg5);
 154
 155         /* Vertical & Horizontal Timing */
 156         value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
 157         value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
 158         writel(value, &regs->lcdc_lcdcfg1);
 159
 160         value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
 161         value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
 162         writel(value, &regs->lcdc_lcdcfg2);
 163
 164         value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
 165         value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
 166         writel(value, &regs->lcdc_lcdcfg3);
 167
 168         /* Display size */
 169         value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
 170         value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
 171         writel(value, &regs->lcdc_lcdcfg4);
 172
 173         writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
 174                &regs->lcdc_basecfg0);
 175
 176         switch (NBITS(panel_info.vl_bpix)) {
 177         case 16:
 178                 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
 179                        &regs->lcdc_basecfg1);
 180                 break;
 181         case 32:
 182                 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
 183                        &regs->lcdc_basecfg1);
 184                 break;
 185         default:
 186                 BUG();
 187                 break;
 188         }
 189
 190         writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
 191         writel(0, &regs->lcdc_basecfg3);
 192         writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
 193
 194         /* Disable all interrupts */
 195         writel(~0UL, &regs->lcdc_lcdidr);
 196         writel(~0UL, &regs->lcdc_baseidr);
 197
 198         /* Setup the DMA descriptor, this descriptor will loop to itself */
 199         desc = (struct lcd_dma_desc *)(lcdbase - 16);
 200
 201         desc->address = (u32)lcdbase;
 202         /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
 203         desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
 204                         | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
 205         desc->next = (u32)desc;
 206
 207         /* Flush the DMA descriptor if we enabled dcache */
 208         flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
 209
 210         writel(desc->address, &regs->lcdc_baseaddr);
 211         writel(desc->control, &regs->lcdc_basectrl);
 212         writel(desc->next, &regs->lcdc_basenext);
 213         writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
 214                &regs->lcdc_basecher);
 215
 216         /* Enable LCD */
 217         value = readl(&regs->lcdc_lcden);
 218         writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
 219         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
 220                                 true, 1000, false);
 221         if (ret)
 222                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 223         value = readl(&regs->lcdc_lcden);
 224         writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
 225         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
 226                                 true, 1000, false);
 227         if (ret)
 228                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 229         value = readl(&regs->lcdc_lcden);
 230         writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
 231         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
 232                                 true, 1000, false);
 233         if (ret)
 234                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 235         value = readl(&regs->lcdc_lcden);
 236         writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
 237         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
 238                                 true, 1000, false);
 239         if (ret)
 240                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 241
 242         /* Enable flushing if we enabled dcache */
 243         lcd_set_flush_dcache(1);
 244 }
 245
 246 #else
 247
 248 enum {
 249         LCD_MAX_WIDTH           = 1024,
 250         LCD_MAX_HEIGHT          = 768,
 251         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
 252 };
 253
 254 struct atmel_hlcdc_priv {
 255         struct atmel_hlcd_regs *regs;
 256         struct display_timing timing;
 257         unsigned int vl_bpix;
 258         unsigned int output_mode;
 259         unsigned int guard_time;
 260         ulong clk_rate;
 261 };
 262
 263 static int at91_hlcdc_enable_clk(struct udevice *dev)
 264 {
 265         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 266         struct clk clk;
 267         ulong clk_rate;
 268         int ret;
 269
 270         ret = clk_get_by_index(dev, 0, &clk);
 271         if (ret)
 272                 return -EINVAL;
 273
 274         ret = clk_enable(&clk);
 275         if (ret)
 276                 return ret;
 277
 278         clk_rate = clk_get_rate(&clk);
 279         if (!clk_rate) {
 280                 clk_disable(&clk);
 281                 return -ENODEV;
 282         }
 283
 284         priv->clk_rate = clk_rate;
 285
 286         clk_free(&clk);
 287
 288         return 0;
 289 }
 290
 291 static void atmel_hlcdc_init(struct udevice *dev)
 292 {
 293         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 294         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 295         struct atmel_hlcd_regs *regs = priv->regs;
 296         struct display_timing *timing = &priv->timing;
 297         struct lcd_dma_desc *desc;
 298         unsigned long value, vl_clk_pol;
 299         int ret;
 300
 301         /* Disable DISP signal */
 302         writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
 303         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
 304                                 false, 1000, false);
 305         if (ret)
 306                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 307         /* Disable synchronization */
 308         writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
 309         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
 310                                 false, 1000, false);
 311         if (ret)
 312                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 313         /* Disable pixel clock */
 314         writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
 315         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
 316                                 false, 1000, false);
 317         if (ret)
 318                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 319         /* Disable PWM */
 320         writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
 321         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
 322                                 false, 1000, false);
 323         if (ret)
 324                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 325
 326         /* Set pixel clock */
 327         value = priv->clk_rate / timing->pixelclock.typ;
 328         if (priv->clk_rate % timing->pixelclock.typ)
 329                 value++;
 330
 331         vl_clk_pol = 0;
 332         if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 333                 vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
 334
 335         if (value < 1) {
 336                 /* Using system clock as pixel clock */
 337                 writel(LCDC_LCDCFG0_CLKDIV(0)
 338                         | LCDC_LCDCFG0_CGDISHCR
 339                         | LCDC_LCDCFG0_CGDISHEO
 340                         | LCDC_LCDCFG0_CGDISOVR1
 341                         | LCDC_LCDCFG0_CGDISBASE
 342                         | vl_clk_pol
 343                         | LCDC_LCDCFG0_CLKSEL,
 344                         &regs->lcdc_lcdcfg0);
 345
 346         } else {
 347                 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
 348                         | LCDC_LCDCFG0_CGDISHCR
 349                         | LCDC_LCDCFG0_CGDISHEO
 350                         | LCDC_LCDCFG0_CGDISOVR1
 351                         | LCDC_LCDCFG0_CGDISBASE
 352                         | vl_clk_pol,
 353                         &regs->lcdc_lcdcfg0);
 354         }
 355
 356         /* Initialize control register 5 */
 357         value = 0;
 358
 359         if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
 360                 value |= LCDC_LCDCFG5_HSPOL;
 361         if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
 362                 value |= LCDC_LCDCFG5_VSPOL;
 363
 364         switch (priv->output_mode) {
 365         case 12:
 366                 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
 367                 break;
 368         case 16:
 369                 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
 370                 break;
 371         case 18:
 372                 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
 373                 break;
 374         case 24:
 375                 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
 376                 break;
 377         default:
 378                 BUG();
 379                 break;
 380         }
 381
 382         value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
 383         value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
 384         writel(value, &regs->lcdc_lcdcfg5);
 385
 386         /* Vertical & Horizontal Timing */
 387         value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
 388         value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
 389         writel(value, &regs->lcdc_lcdcfg1);
 390
 391         value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
 392         value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
 393         writel(value, &regs->lcdc_lcdcfg2);
 394
 395         value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
 396         value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
 397         writel(value, &regs->lcdc_lcdcfg3);
 398
 399         /* Display size */
 400         value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
 401         value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
 402         writel(value, &regs->lcdc_lcdcfg4);
 403
 404         writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
 405                &regs->lcdc_basecfg0);
 406
 407         switch (VNBITS(priv->vl_bpix)) {
 408         case 16:
 409                 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
 410                        &regs->lcdc_basecfg1);
 411                 break;
 412         case 32:
 413                 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
 414                        &regs->lcdc_basecfg1);
 415                 break;
 416         default:
 417                 BUG();
 418                 break;
 419         }
 420
 421         writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
 422         writel(0, &regs->lcdc_basecfg3);
 423         writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
 424
 425         /* Disable all interrupts */
 426         writel(~0UL, &regs->lcdc_lcdidr);
 427         writel(~0UL, &regs->lcdc_baseidr);
 428
 429         /* Setup the DMA descriptor, this descriptor will loop to itself */
 430         desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
 431         if (!desc)
 432                 return;
 433
 434         desc->address = (u32)uc_plat->base;
 435
 436         /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
 437         desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
 438                         | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
 439         desc->next = (u32)desc;
 440
 441         /* Flush the DMA descriptor if we enabled dcache */
 442         flush_dcache_range((u32)desc,
 443                            ALIGN(((u32)desc + sizeof(*desc)),
 444                            CONFIG_SYS_CACHELINE_SIZE));
 445
 446         writel(desc->address, &regs->lcdc_baseaddr);
 447         writel(desc->control, &regs->lcdc_basectrl);
 448         writel(desc->next, &regs->lcdc_basenext);
 449         writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
 450                &regs->lcdc_basecher);
 451
 452         /* Enable LCD */
 453         value = readl(&regs->lcdc_lcden);
 454         writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
 455         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
 456                                 true, 1000, false);
 457         if (ret)
 458                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 459         value = readl(&regs->lcdc_lcden);
 460         writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
 461         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
 462                                 true, 1000, false);
 463         if (ret)
 464                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 465         value = readl(&regs->lcdc_lcden);
 466         writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
 467         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
 468                                 true, 1000, false);
 469         if (ret)
 470                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 471         value = readl(&regs->lcdc_lcden);
 472         writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
 473         ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
 474                                 true, 1000, false);
 475         if (ret)
 476                 printf("%s: %d: Timeout!\n", __func__, __LINE__);
 477 }
 478
 479 static int atmel_hlcdc_probe(struct udevice *dev)
 480 {
 481         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 482         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 483         int ret;
 484
 485         ret = at91_hlcdc_enable_clk(dev);
 486         if (ret)
 487                 return ret;
 488
 489         atmel_hlcdc_init(dev);
 490
 491         uc_priv->xsize = priv->timing.hactive.typ;
 492         uc_priv->ysize = priv->timing.vactive.typ;
 493         uc_priv->bpix = priv->vl_bpix;
 494
 495         /* Enable flushing if we enabled dcache */
 496         video_set_flush_dcache(dev, true);
 497
 498         return 0;
 499 }
 500
 501 static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
 502 {
 503         struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
 504         const void *blob = gd->fdt_blob;
 505         int node = dev_of_offset(dev);
 506
 507         priv->regs = (struct atmel_hlcd_regs *)devfdt_get_addr(dev);
 508         if (!priv->regs) {
 509                 debug("%s: No display controller address\n", __func__);
 510                 return -EINVAL;
 511         }
 512
 513         if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
 514                                          0, &priv->timing)) {
 515                 debug("%s: Failed to decode display timing\n", __func__);
 516                 return -EINVAL;
 517         }
 518
 519         if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
 520                 priv->timing.hactive.typ = LCD_MAX_WIDTH;
 521
 522         if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
 523                 priv->timing.vactive.typ = LCD_MAX_HEIGHT;
 524
 525         priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
 526         if (!priv->vl_bpix) {
 527                 debug("%s: Failed to get bits per pixel\n", __func__);
 528                 return -EINVAL;
 529         }
 530
 531         priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
 532         priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
 533
 534         return 0;
 535 }
 536
 537 static int atmel_hlcdc_bind(struct udevice *dev)
 538 {
 539         struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
 540
 541         uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 542                                 (1 << LCD_MAX_LOG2_BPP) / 8;
 543
 544         debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
 545
 546         return 0;
 547 }
 548
 549 static const struct udevice_id atmel_hlcdc_ids[] = {
 550         { .compatible = "atmel,sama5d2-hlcdc" },
 551         { .compatible = "atmel,at91sam9x5-hlcdc" },
 552         { }
 553 };
 554
 555 U_BOOT_DRIVER(atmel_hlcdfb) = {
 556         .name   = "atmel_hlcdfb",
 557         .id     = UCLASS_VIDEO,
 558         .of_match = atmel_hlcdc_ids,
 559         .bind   = atmel_hlcdc_bind,
 560         .probe  = atmel_hlcdc_probe,
 561         .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata,
 562         .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv),
 563 };
 564
 565 #endif