drivers/video/anx9804.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) 2015 Hans de Goede <hdegoede@redhat.com>
   4  */
   5
   6 /*
   7  * Support for the ANX9804 bridge chip, which can take pixel data coming
   8  * from a parallel LCD interface and translate it on the flight into a DP
   9  * interface for driving eDP TFT displays.
  10  */
  11
  12 #include <common.h>
  13 #include <i2c.h>
  14 #include <linux/delay.h>
  15 #include "anx98xx-edp.h"
  16 #include "anx9804.h"
  17
  18 /**
  19  * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
  20  *
  21  * This function will init an anx9804 parallel lcd to dp bridge chip
  22  * using the passed in parameters.
  23  *
  24  * @i2c_bus:    Number of the i2c bus to which the anx9804 is connected.
  25  * @lanes:      Number of displayport lanes to use
  26  * @data_rate:  Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
  27  * @bpp:        Bits per pixel, must be 18 or 24
  28  */
  29 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
  30 {
  31         unsigned int orig_i2c_bus = i2c_get_bus_num();
  32         u8 c, colordepth;
  33         int i;
  34
  35         i2c_set_bus_num(i2c_bus);
  36
  37         if (bpp == 18)
  38                 colordepth = 0x00; /* 6 bit */
  39         else
  40                 colordepth = 0x10; /* 8 bit */
  41
  42         /* Reset */
  43         i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
  44         mdelay(100);
  45         i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
  46
  47         /* Write 0 to the powerdown reg (powerup everything) */
  48         i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
  49
  50         c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
  51         if (c != 0x98) {
  52                 printf("Error anx9804 chipid mismatch\n");
  53                 i2c_set_bus_num(orig_i2c_bus);
  54                 return;
  55         }
  56
  57         for (i = 0; i < 100; i++) {
  58                 c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
  59                 i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
  60                 c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
  61                 if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
  62                         break;
  63
  64                 mdelay(5);
  65         }
  66         if (i == 100)
  67                 printf("Error anx9804 clock is not stable\n");
  68
  69         i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
  70
  71         /* Set a bunch of analog related register values */
  72         i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
  73         i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
  74         i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
  75         i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
  76         i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
  77         i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
  78         i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
  79         i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
  80         i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
  81
  82         /* Force HPD */
  83         i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
  84                       ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
  85
  86         /* Power up and configure lanes */
  87         i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
  88         i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
  89         i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
  90         i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
  91         i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
  92
  93         /* Reset AUX CH */
  94         i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
  95                       ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
  96         i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
  97                       ANX9804_RST_CTRL2_AC_MODE);
  98
  99         /* Powerdown audio and some other unused bits */
 100         i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
 101         i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
 102         i2c_reg_write(0x38, 0xa7, 0x00);
 103
 104         /* Set data-rate / lanes */
 105         i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
 106         i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
 107
 108         /* Link training */
 109         i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
 110                       ANX9804_LINK_TRAINING_CTRL_EN);
 111         mdelay(5);
 112         for (i = 0; i < 100; i++) {
 113                 c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
 114                 if ((c & 0x01) == 0)
 115                         break;
 116
 117                 mdelay(5);
 118         }
 119         if(i == 100) {
 120                 printf("Error anx9804 link training timeout\n");
 121                 i2c_set_bus_num(orig_i2c_bus);
 122                 return;
 123         }
 124
 125         /* Enable */
 126         i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
 127                       ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
 128         /* Force stream valid */
 129         i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
 130                       ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
 131                       ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
 132
 133         i2c_set_bus_num(orig_i2c_bus);
 134 }