drivers/usb/phy/omap_usb_phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * OMAP USB PHY Support
   4  *
   5  * (C) Copyright 2013
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Author: Dan Murphy <dmurphy@ti.com>
   9  */
  10
  11 #include <common.h>
  12 #include <usb.h>
  13 #include <dm/device_compat.h>
  14 #include <linux/delay.h>
  15 #include <linux/errno.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/sys_proto.h>
  19
  20 #include <linux/compat.h>
  21 #include <linux/usb/dwc3.h>
  22 #include <linux/usb/xhci-omap.h>
  23
  24 #include <usb/xhci.h>
  25
  26 #ifdef CONFIG_OMAP_USB3PHY1_HOST
  27 struct usb3_dpll_params {
  28         u16     m;
  29         u8      n;
  30         u8      freq:3;
  31         u8      sd;
  32         u32     mf;
  33 };
  34
  35 struct usb3_dpll_map {
  36         unsigned long rate;
  37         struct usb3_dpll_params params;
  38         struct usb3_dpll_map *dpll_map;
  39 };
  40
  41 static struct usb3_dpll_map dpll_map_usb[] = {
  42         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
  43         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
  44         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
  45         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
  46         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
  47         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
  48         { },                                    /* Terminator */
  49 };
  50
  51 static struct usb3_dpll_params *omap_usb3_get_dpll_params(void)
  52 {
  53         unsigned long rate;
  54         struct usb3_dpll_map *dpll_map = dpll_map_usb;
  55
  56         rate = get_sys_clk_freq();
  57
  58         for (; dpll_map->rate; dpll_map++) {
  59                 if (rate == dpll_map->rate)
  60                         return &dpll_map->params;
  61         }
  62
  63         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
  64
  65         return NULL;
  66 }
  67
  68 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
  69 {
  70         u32 val;
  71
  72         writel(SET_PLL_GO, &phy_regs->pll_go);
  73         do {
  74                 val = readl(&phy_regs->pll_status);
  75                         if (val & PLL_LOCK)
  76                                 break;
  77         } while (1);
  78 }
  79
  80 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
  81 {
  82         struct usb3_dpll_params *dpll_params;
  83         u32 val;
  84
  85         dpll_params = omap_usb3_get_dpll_params();
  86         if (!dpll_params)
  87                 return;
  88
  89         val = readl(&phy_regs->pll_config_1);
  90         val &= ~PLL_REGN_MASK;
  91         val |= dpll_params->n << PLL_REGN_SHIFT;
  92         writel(val, &phy_regs->pll_config_1);
  93
  94         val = readl(&phy_regs->pll_config_2);
  95         val &= ~PLL_SELFREQDCO_MASK;
  96         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
  97         writel(val, &phy_regs->pll_config_2);
  98
  99         val = readl(&phy_regs->pll_config_1);
 100         val &= ~PLL_REGM_MASK;
 101         val |= dpll_params->m << PLL_REGM_SHIFT;
 102         writel(val, &phy_regs->pll_config_1);
 103
 104         val = readl(&phy_regs->pll_config_4);
 105         val &= ~PLL_REGM_F_MASK;
 106         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 107         writel(val, &phy_regs->pll_config_4);
 108
 109         val = readl(&phy_regs->pll_config_3);
 110         val &= ~PLL_SD_MASK;
 111         val |= dpll_params->sd << PLL_SD_SHIFT;
 112         writel(val, &phy_regs->pll_config_3);
 113
 114         omap_usb_dpll_relock(phy_regs);
 115 }
 116
 117 static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs)
 118 {
 119         u32 rate = get_sys_clk_freq()/1000000;
 120         u32 val;
 121
 122         val = readl((*ctrl)->control_phy_power_usb);
 123         val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK);
 124         val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON);
 125         val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT;
 126
 127         writel(val, (*ctrl)->control_phy_power_usb);
 128 }
 129
 130 void usb_phy_power(int on)
 131 {
 132         u32 val;
 133
 134         val = readl((*ctrl)->control_phy_power_usb);
 135         if (on) {
 136                 val &= ~USB3_PWRCTL_CLK_CMD_MASK;
 137                 val |= USB3_PHY_TX_RX_POWERON;
 138         } else {
 139                 val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON);
 140         }
 141
 142         writel(val, (*ctrl)->control_phy_power_usb);
 143 }
 144
 145 void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs)
 146 {
 147         omap_usb_dpll_lock(phy_regs);
 148         usb3_phy_partial_powerup(phy_regs);
 149         /*
 150          * Give enough time for the PHY to partially power-up before
 151          * powering it up completely. delay value suggested by the HW
 152          * team.
 153          */
 154         mdelay(100);
 155 }
 156
 157 static void omap_enable_usb3_phy(struct omap_xhci *omap)
 158 {
 159         u32     val;
 160
 161         val = (USBOTGSS_DMADISABLE |
 162                         USBOTGSS_STANDBYMODE_SMRT_WKUP |
 163                         USBOTGSS_IDLEMODE_NOIDLE);
 164         writel(val, &omap->otg_wrapper->sysconfig);
 165
 166         /* Clear the utmi OTG status */
 167         val = readl(&omap->otg_wrapper->utmi_otg_status);
 168         writel(val, &omap->otg_wrapper->utmi_otg_status);
 169
 170         /* Enable interrupts */
 171         writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0);
 172         val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN |
 173                         USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN |
 174                         USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN     |
 175                         USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN      |
 176                         USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN     |
 177                         USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN  |
 178                         USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN |
 179                         USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN |
 180                         USBOTGSS_IRQ_SET_1_OEVT_EN);
 181         writel(val, &omap->otg_wrapper->irqenable_set_1);
 182
 183         /* Clear the IRQ status */
 184         val = readl(&omap->otg_wrapper->irqstatus_1);
 185         writel(val, &omap->otg_wrapper->irqstatus_1);
 186         val = readl(&omap->otg_wrapper->irqstatus_0);
 187         writel(val, &omap->otg_wrapper->irqstatus_0);
 188 };
 189 #endif /* CONFIG_OMAP_USB3PHY1_HOST */
 190
 191 #ifdef CONFIG_OMAP_USB2PHY2_HOST
 192 static void omap_enable_usb2_phy2(struct omap_xhci *omap)
 193 {
 194         u32 reg, val;
 195
 196         val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET);
 197         writel(val, (*ctrl)->control_srcomp_north_side);
 198
 199         setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
 200                         USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 201
 202         setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl,
 203                                         (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K |
 204                                          OTG_SS_CLKCTRL_MODULEMODE_HW));
 205
 206         /* This is an undocumented Reserved register */
 207         reg = 0x4a0086c0;
 208         val = readl(reg);
 209         val |= 0x100;
 210         setbits_le32(reg, val);
 211 }
 212
 213 void usb_phy_power(int on)
 214 {
 215         return;
 216 }
 217 #endif /* CONFIG_OMAP_USB2PHY2_HOST */
 218
 219 #ifdef CONFIG_AM437X_USB2PHY2_HOST
 220 static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
 221 {
 222         const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN |
 223                                 USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
 224
 225         writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL);
 226         writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL);
 227
 228         writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL);
 229         writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL);
 230 }
 231
 232 void usb_phy_power(int on)
 233 {
 234         u32 val;
 235
 236         /* USB1_CTRL */
 237         val = readl(USB1_CTRL);
 238         if (on) {
 239                 /*
 240                  * these bits are re-used on AM437x to power up/down the USB
 241                  * CM and OTG PHYs, if we don't toggle them, USB will not be
 242                  * functional on newer silicon revisions
 243                  */
 244                 val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN);
 245         } else {
 246                 val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN;
 247         }
 248
 249         writel(val, USB1_CTRL);
 250 }
 251 #endif /* CONFIG_AM437X_USB2PHY2_HOST */
 252
 253 void omap_enable_phy(struct omap_xhci *omap)
 254 {
 255 #ifdef CONFIG_OMAP_USB2PHY2_HOST
 256         omap_enable_usb2_phy2(omap);
 257 #endif
 258
 259 #ifdef CONFIG_AM437X_USB2PHY2_HOST
 260         am437x_enable_usb2_phy2(omap);
 261 #endif
 262
 263 #ifdef CONFIG_OMAP_USB3PHY1_HOST
 264         omap_enable_usb3_phy(omap);
 265         omap_usb3_phy_init(omap->usb3_phy);
 266 #endif
 267 }