1 // SPDX-License-Identifier: GPL-2.0
3 * Allwinner SUNXI "glue layer"
5 * Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
6 * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
8 * Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
9 * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
10 * javen <javen@allwinnertech.com>
12 * Based on the DA8xx "glue layer" code.
13 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
14 * Copyright (C) 2005-2006 by Texas Instruments
16 * This file is part of the Inventra Controller Driver for Linux.
21 #include <generic-phy.h>
24 #include <phy-sun4i-usb.h>
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/gpio.h>
29 #include <asm-generic/gpio.h>
30 #include <dm/device_compat.h>
33 #include <linux/delay.h>
34 #include <linux/usb/musb.h>
35 #include "linux-compat.h"
36 #include "musb_core.h"
37 #include "musb_uboot.h"
39 /******************************************************************************
40 ******************************************************************************
41 * From the Allwinner driver
42 ******************************************************************************
43 ******************************************************************************/
45 /******************************************************************************
46 * From include/sunxi_usb_bsp.h
47 ******************************************************************************/
50 #define USBC_REG_o_ISCR 0x0400
51 #define USBC_REG_o_PHYCTL 0x0404
52 #define USBC_REG_o_PHYBIST 0x0408
53 #define USBC_REG_o_PHYTUNE 0x040c
55 #define USBC_REG_o_VEND0 0x0043
57 /* Interface Status and Control */
58 #define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
59 #define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
60 #define USBC_BP_ISCR_EXT_ID_STATUS 28
61 #define USBC_BP_ISCR_EXT_DM_STATUS 27
62 #define USBC_BP_ISCR_EXT_DP_STATUS 26
63 #define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
64 #define USBC_BP_ISCR_MERGED_ID_STATUS 24
66 #define USBC_BP_ISCR_ID_PULLUP_EN 17
67 #define USBC_BP_ISCR_DPDM_PULLUP_EN 16
68 #define USBC_BP_ISCR_FORCE_ID 14
69 #define USBC_BP_ISCR_FORCE_VBUS_VALID 12
70 #define USBC_BP_ISCR_VBUS_VALID_SRC 10
72 #define USBC_BP_ISCR_HOSC_EN 7
73 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
74 #define USBC_BP_ISCR_ID_CHANGE_DETECT 5
75 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
76 #define USBC_BP_ISCR_IRQ_ENABLE 3
77 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
78 #define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
79 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
81 /******************************************************************************
83 ******************************************************************************/
85 #define OFF_SUN6I_AHB_RESET0 0x2c0
87 struct sunxi_musb_config {
88 struct musb_hdrc_config *config;
92 struct musb_host_data mdata;
95 struct sunxi_musb_config *cfg;
99 #define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev)
101 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
105 temp &= ~BIT(USBC_BP_ISCR_VBUS_CHANGE_DETECT);
106 temp &= ~BIT(USBC_BP_ISCR_ID_CHANGE_DETECT);
107 temp &= ~BIT(USBC_BP_ISCR_DPDM_CHANGE_DETECT);
112 static void USBC_EnableIdPullUp(__iomem void *base)
116 reg_val = musb_readl(base, USBC_REG_o_ISCR);
117 reg_val |= BIT(USBC_BP_ISCR_ID_PULLUP_EN);
118 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
119 musb_writel(base, USBC_REG_o_ISCR, reg_val);
122 static void USBC_EnableDpDmPullUp(__iomem void *base)
126 reg_val = musb_readl(base, USBC_REG_o_ISCR);
127 reg_val |= BIT(USBC_BP_ISCR_DPDM_PULLUP_EN);
128 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
129 musb_writel(base, USBC_REG_o_ISCR, reg_val);
132 static void USBC_ForceIdToLow(__iomem void *base)
136 reg_val = musb_readl(base, USBC_REG_o_ISCR);
137 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
138 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
139 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
140 musb_writel(base, USBC_REG_o_ISCR, reg_val);
143 static void USBC_ForceIdToHigh(__iomem void *base)
147 reg_val = musb_readl(base, USBC_REG_o_ISCR);
148 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
149 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
150 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
151 musb_writel(base, USBC_REG_o_ISCR, reg_val);
154 static void USBC_ForceVbusValidToLow(__iomem void *base)
158 reg_val = musb_readl(base, USBC_REG_o_ISCR);
159 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
160 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID);
161 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
162 musb_writel(base, USBC_REG_o_ISCR, reg_val);
165 static void USBC_ForceVbusValidToHigh(__iomem void *base)
169 reg_val = musb_readl(base, USBC_REG_o_ISCR);
170 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
171 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
172 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
173 musb_writel(base, USBC_REG_o_ISCR, reg_val);
176 static void USBC_ConfigFIFO_Base(void)
180 /* config usb fifo, 8kb mode */
181 reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
182 reg_value &= ~(0x03 << 0);
184 writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
187 /******************************************************************************
188 * Needed for the DFU polling magic
189 ******************************************************************************/
191 static u8 last_int_usb;
193 bool dfu_usb_get_reset(void)
195 return !!(last_int_usb & MUSB_INTR_RESET);
198 /******************************************************************************
200 ******************************************************************************/
202 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
204 struct musb *musb = __hci;
205 irqreturn_t retval = IRQ_NONE;
207 /* read and flush interrupts */
208 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
209 last_int_usb = musb->int_usb;
211 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
212 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
214 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
215 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
217 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
219 if (musb->int_usb || musb->int_tx || musb->int_rx)
220 retval |= musb_interrupt(musb);
225 /* musb_core does not call enable / disable in a balanced manner <sigh> */
226 static bool enabled = false;
228 static int sunxi_musb_enable(struct musb *musb)
230 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
233 pr_debug("%s():\n", __func__);
235 musb_ep_select(musb->mregs, 0);
236 musb_writeb(musb->mregs, MUSB_FADDR, 0);
241 /* select PIO mode */
242 musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
244 if (is_host_enabled(musb)) {
245 ret = sun4i_usb_phy_vbus_detect(&glue->phy);
247 printf("A charger is plugged into the OTG: ");
251 ret = sun4i_usb_phy_id_detect(&glue->phy);
253 printf("No host cable detected: ");
257 ret = generic_phy_power_on(&glue->phy);
259 pr_err("failed to power on USB PHY\n");
264 USBC_ForceVbusValidToHigh(musb->mregs);
270 static void sunxi_musb_disable(struct musb *musb)
272 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
275 pr_debug("%s():\n", __func__);
280 if (is_host_enabled(musb)) {
281 ret = generic_phy_power_off(&glue->phy);
283 pr_err("failed to power off USB PHY\n");
288 USBC_ForceVbusValidToLow(musb->mregs);
289 mdelay(200); /* Wait for the current session to timeout */
294 static int sunxi_musb_init(struct musb *musb)
296 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
299 pr_debug("%s():\n", __func__);
301 ret = clk_enable(&glue->clk);
303 dev_err(dev, "failed to enable clock\n");
307 if (reset_valid(&glue->rst)) {
308 ret = reset_deassert(&glue->rst);
310 dev_err(dev, "failed to deassert reset\n");
315 ret = generic_phy_init(&glue->phy);
317 dev_err(dev, "failed to init USB PHY\n");
321 musb->isr = sunxi_musb_interrupt;
323 USBC_ConfigFIFO_Base();
324 USBC_EnableDpDmPullUp(musb->mregs);
325 USBC_EnableIdPullUp(musb->mregs);
327 if (is_host_enabled(musb)) {
329 USBC_ForceIdToLow(musb->mregs);
331 /* Peripheral mode */
332 USBC_ForceIdToHigh(musb->mregs);
334 USBC_ForceVbusValidToHigh(musb->mregs);
339 if (reset_valid(&glue->rst))
340 reset_assert(&glue->rst);
342 clk_disable(&glue->clk);
346 static int sunxi_musb_exit(struct musb *musb)
348 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
351 if (generic_phy_valid(&glue->phy)) {
352 ret = generic_phy_exit(&glue->phy);
354 dev_err(dev, "failed to power off usb phy\n");
359 if (reset_valid(&glue->rst))
360 reset_assert(&glue->rst);
361 clk_disable(&glue->clk);
366 static void sunxi_musb_pre_root_reset_end(struct musb *musb)
368 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
370 sun4i_usb_phy_set_squelch_detect(&glue->phy, false);
373 static void sunxi_musb_post_root_reset_end(struct musb *musb)
375 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
377 sun4i_usb_phy_set_squelch_detect(&glue->phy, true);
380 static const struct musb_platform_ops sunxi_musb_ops = {
381 .init = sunxi_musb_init,
382 .exit = sunxi_musb_exit,
383 .enable = sunxi_musb_enable,
384 .disable = sunxi_musb_disable,
385 .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
386 .post_root_reset_end = sunxi_musb_post_root_reset_end,
389 /* Allwinner OTG supports up to 5 endpoints */
390 #define SUNXI_MUSB_MAX_EP_NUM 6
391 #define SUNXI_MUSB_RAM_BITS 11
393 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
394 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
395 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
396 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
397 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
398 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
399 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
400 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
401 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
402 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
403 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
406 /* H3/V3s OTG supports only 4 endpoints */
407 #define SUNXI_MUSB_MAX_EP_NUM_H3 5
409 static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
410 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
411 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
412 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
413 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
414 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
415 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
416 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
417 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
420 static struct musb_hdrc_config musb_config = {
421 .fifo_cfg = sunxi_musb_mode_cfg,
422 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
425 .num_eps = SUNXI_MUSB_MAX_EP_NUM,
426 .ram_bits = SUNXI_MUSB_RAM_BITS,
429 static struct musb_hdrc_config musb_config_h3 = {
430 .fifo_cfg = sunxi_musb_mode_cfg_h3,
431 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
435 .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
436 .ram_bits = SUNXI_MUSB_RAM_BITS,
439 static int musb_usb_probe(struct udevice *dev)
441 struct sunxi_glue *glue = dev_get_priv(dev);
442 struct musb_host_data *host = &glue->mdata;
443 struct musb_hdrc_platform_data pdata;
444 void *base = dev_read_addr_ptr(dev);
447 #ifdef CONFIG_USB_MUSB_HOST
448 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
454 glue->cfg = (struct sunxi_musb_config *)dev_get_driver_data(dev);
458 ret = clk_get_by_index(dev, 0, &glue->clk);
460 dev_err(dev, "failed to get clock\n");
464 ret = reset_get_by_index(dev, 0, &glue->rst);
465 if (ret && ret != -ENOENT) {
466 dev_err(dev, "failed to get reset\n");
470 ret = generic_phy_get_by_name(dev, "usb", &glue->phy);
472 pr_err("failed to get usb PHY\n");
476 memset(&pdata, 0, sizeof(pdata));
478 pdata.platform_ops = &sunxi_musb_ops;
479 pdata.config = glue->cfg->config;
481 #ifdef CONFIG_USB_MUSB_HOST
482 priv->desc_before_addr = true;
484 pdata.mode = MUSB_HOST;
485 host->host = musb_init_controller(&pdata, &glue->dev, base);
489 ret = musb_lowlevel_init(host);
491 printf("Allwinner mUSB OTG (Host)\n");
493 pdata.mode = MUSB_PERIPHERAL;
494 host->host = musb_register(&pdata, &glue->dev, base);
498 printf("Allwinner mUSB OTG (Peripheral)\n");
504 static int musb_usb_remove(struct udevice *dev)
506 struct sunxi_glue *glue = dev_get_priv(dev);
507 struct musb_host_data *host = &glue->mdata;
509 musb_stop(host->host);
516 static const struct sunxi_musb_config sun4i_a10_cfg = {
517 .config = &musb_config,
520 static const struct sunxi_musb_config sun6i_a31_cfg = {
521 .config = &musb_config,
524 static const struct sunxi_musb_config sun8i_h3_cfg = {
525 .config = &musb_config_h3,
528 static const struct udevice_id sunxi_musb_ids[] = {
529 { .compatible = "allwinner,sun4i-a10-musb",
530 .data = (ulong)&sun4i_a10_cfg },
531 { .compatible = "allwinner,sun6i-a31-musb",
532 .data = (ulong)&sun6i_a31_cfg },
533 { .compatible = "allwinner,sun8i-a33-musb",
534 .data = (ulong)&sun6i_a31_cfg },
535 { .compatible = "allwinner,sun8i-h3-musb",
536 .data = (ulong)&sun8i_h3_cfg },
540 U_BOOT_DRIVER(usb_musb) = {
541 .name = "sunxi-musb",
542 #ifdef CONFIG_USB_MUSB_HOST
545 .id = UCLASS_USB_GADGET_GENERIC,
547 .of_match = sunxi_musb_ids,
548 .probe = musb_usb_probe,
549 .remove = musb_usb_remove,
550 #ifdef CONFIG_USB_MUSB_HOST
551 .ops = &musb_usb_ops,
553 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
554 .priv_auto_alloc_size = sizeof(struct sunxi_glue),