1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments AM35x "glue layer"
5 * Copyright (c) 2010, by Texas Instruments
7 * Based on the DA8xx "glue layer" code.
8 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
10 * This file is part of the Inventra Controller Driver for Linux.
15 #include <dm/device_compat.h>
16 #include <dm/devres.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
28 #include <asm/omap_musb.h>
29 #include <linux/bug.h>
30 #include "linux-compat.h"
33 #include "musb_core.h"
36 * AM35x specific definitions
38 /* USB 2.0 OTG module registers */
39 #define USB_REVISION_REG 0x00
40 #define USB_CTRL_REG 0x04
41 #define USB_STAT_REG 0x08
42 #define USB_EMULATION_REG 0x0c
44 #define USB_AUTOREQ_REG 0x14
45 #define USB_SRP_FIX_TIME_REG 0x18
46 #define USB_TEARDOWN_REG 0x1c
47 #define EP_INTR_SRC_REG 0x20
48 #define EP_INTR_SRC_SET_REG 0x24
49 #define EP_INTR_SRC_CLEAR_REG 0x28
50 #define EP_INTR_MASK_REG 0x2c
51 #define EP_INTR_MASK_SET_REG 0x30
52 #define EP_INTR_MASK_CLEAR_REG 0x34
53 #define EP_INTR_SRC_MASKED_REG 0x38
54 #define CORE_INTR_SRC_REG 0x40
55 #define CORE_INTR_SRC_SET_REG 0x44
56 #define CORE_INTR_SRC_CLEAR_REG 0x48
57 #define CORE_INTR_MASK_REG 0x4c
58 #define CORE_INTR_MASK_SET_REG 0x50
59 #define CORE_INTR_MASK_CLEAR_REG 0x54
60 #define CORE_INTR_SRC_MASKED_REG 0x58
62 #define USB_END_OF_INTR_REG 0x60
64 /* Control register bits */
65 #define AM35X_SOFT_RESET_MASK 1
67 /* USB interrupt register bits */
68 #define AM35X_INTR_USB_SHIFT 16
69 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
70 #define AM35X_INTR_DRVVBUS 0x100
71 #define AM35X_INTR_RX_SHIFT 16
72 #define AM35X_INTR_TX_SHIFT 0
73 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
74 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
75 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
76 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
78 #define USB_MENTOR_CORE_OFFSET 0x400
82 struct platform_device *musb;
86 #define glue_to_musb(g) platform_get_drvdata(g->musb)
89 * am35x_musb_enable - enable interrupts
92 static void am35x_musb_enable(struct musb *musb)
94 static int am35x_musb_enable(struct musb *musb)
97 void __iomem *reg_base = musb->ctrl_base;
100 /* Workaround: setup IRQs through both register sets. */
101 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
102 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
104 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
105 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
107 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
108 if (is_otg_enabled(musb))
109 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
110 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
117 * am35x_musb_disable - disable HDRC and flush interrupts
119 static void am35x_musb_disable(struct musb *musb)
121 void __iomem *reg_base = musb->ctrl_base;
123 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
124 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
125 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
126 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
127 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
131 #define portstate(stmt) stmt
133 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
135 WARN_ON(is_on && is_peripheral_active(musb));
138 #define POLL_SECONDS 2
140 static struct timer_list otg_workaround;
142 static void otg_timer(unsigned long _musb)
144 struct musb *musb = (void *)_musb;
145 void __iomem *mregs = musb->mregs;
150 * We poll because AM35x's won't expose several OTG-critical
151 * status change events (from the transceiver) otherwise.
153 devctl = musb_readb(mregs, MUSB_DEVCTL);
154 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
155 otg_state_string(musb->xceiv->state));
157 spin_lock_irqsave(&musb->lock, flags);
158 switch (musb->xceiv->state) {
159 case OTG_STATE_A_WAIT_BCON:
160 devctl &= ~MUSB_DEVCTL_SESSION;
161 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
163 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
164 if (devctl & MUSB_DEVCTL_BDEVICE) {
165 musb->xceiv->state = OTG_STATE_B_IDLE;
168 musb->xceiv->state = OTG_STATE_A_IDLE;
172 case OTG_STATE_A_WAIT_VFALL:
173 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
174 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
175 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
177 case OTG_STATE_B_IDLE:
178 if (!is_peripheral_enabled(musb))
181 devctl = musb_readb(mregs, MUSB_DEVCTL);
182 if (devctl & MUSB_DEVCTL_BDEVICE)
183 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
185 musb->xceiv->state = OTG_STATE_A_IDLE;
190 spin_unlock_irqrestore(&musb->lock, flags);
193 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
195 static unsigned long last_timer;
197 if (!is_otg_enabled(musb))
201 timeout = jiffies + msecs_to_jiffies(3);
203 /* Never idle if active, or when VBUS timeout is not set as host */
204 if (musb->is_active || (musb->a_wait_bcon == 0 &&
205 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
206 dev_dbg(musb->controller, "%s active, deleting timer\n",
207 otg_state_string(musb->xceiv->state));
208 del_timer(&otg_workaround);
209 last_timer = jiffies;
213 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
214 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
217 last_timer = timeout;
219 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
220 otg_state_string(musb->xceiv->state),
221 jiffies_to_msecs(timeout - jiffies));
222 mod_timer(&otg_workaround, timeout);
226 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
228 struct musb *musb = hci;
229 void __iomem *reg_base = musb->ctrl_base;
231 struct device *dev = musb->controller;
232 struct musb_hdrc_platform_data *plat = dev->platform_data;
233 struct omap_musb_board_data *data = plat->board_data;
234 struct usb_otg *otg = musb->xceiv->otg;
236 struct omap_musb_board_data *data =
237 (struct omap_musb_board_data *)musb->controller;
240 irqreturn_t ret = IRQ_NONE;
245 * It seems that on AM35X interrupt registers can be updated
246 * before core registers. This confuses the code.
247 * As a workaround add a small delay here.
251 spin_lock_irqsave(&musb->lock, flags);
253 /* Get endpoint interrupts */
254 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
257 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
260 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
262 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
265 /* Get usb core interrupts */
266 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
267 if (!usbintr && !epintr)
271 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
274 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
278 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
279 * AM35x's missing ID change IRQ. We need an ID change IRQ to
280 * switch appropriately between halves of the OTG state machine.
281 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
282 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
283 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
285 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
286 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
287 void __iomem *mregs = musb->mregs;
288 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
291 err = is_host_enabled(musb) && (musb->int_usb &
292 MUSB_INTR_VBUSERROR);
295 * The Mentor core doesn't debounce VBUS as needed
296 * to cope with device connect current spikes. This
297 * means it's not uncommon for bus-powered devices
298 * to get VBUS errors during enumeration.
300 * This is a workaround, but newer RTL from Mentor
301 * seems to allow a better one: "re"-starting sessions
302 * without waiting for VBUS to stop registering in
305 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
306 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
307 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
308 WARNING("VBUS error workaround (delay coming)\n");
309 } else if (is_host_enabled(musb) && drvvbus) {
312 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
313 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
314 del_timer(&otg_workaround);
319 musb->xceiv->state = OTG_STATE_B_IDLE;
320 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
323 /* NOTE: this must complete power-on within 100 ms. */
324 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
325 drvvbus ? "on" : "off",
326 otg_state_string(musb->xceiv->state),
333 if (musb->int_tx || musb->int_rx || musb->int_usb)
334 ret |= musb_interrupt(musb);
337 /* EOI needs to be written for the IRQ to be re-asserted. */
338 if (ret == IRQ_HANDLED || epintr || usbintr) {
339 /* clear level interrupt */
341 data->clear_irq(data->dev);
343 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
347 /* Poll for ID change */
348 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
349 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
352 spin_unlock_irqrestore(&musb->lock, flags);
358 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
360 struct device *dev = musb->controller;
361 struct musb_hdrc_platform_data *plat = dev->platform_data;
362 struct omap_musb_board_data *data = plat->board_data;
366 data->set_mode(musb_mode);
374 static int am35x_musb_init(struct musb *musb)
377 struct device *dev = musb->controller;
378 struct musb_hdrc_platform_data *plat = dev->platform_data;
379 struct omap_musb_board_data *data = plat->board_data;
381 struct omap_musb_board_data *data =
382 (struct omap_musb_board_data *)musb->controller;
384 void __iomem *reg_base = musb->ctrl_base;
387 musb->mregs += USB_MENTOR_CORE_OFFSET;
389 /* Returns zero if e.g. not clocked */
390 rev = musb_readl(reg_base, USB_REVISION_REG);
395 usb_nop_xceiv_register();
396 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
397 if (IS_ERR_OR_NULL(musb->xceiv))
400 if (is_host_enabled(musb))
401 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
406 data->reset(data->dev);
408 /* Reset the controller */
409 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
411 /* Start the on-chip PHY and its PLL. */
412 if (data && data->set_phy_power)
413 data->set_phy_power(data->dev, 1);
417 musb->isr = am35x_musb_interrupt;
419 /* clear level interrupt */
421 data->clear_irq(data->dev);
426 static int am35x_musb_exit(struct musb *musb)
429 struct device *dev = musb->controller;
430 struct musb_hdrc_platform_data *plat = dev->platform_data;
431 struct omap_musb_board_data *data = plat->board_data;
433 struct omap_musb_board_data *data =
434 (struct omap_musb_board_data *)musb->controller;
438 if (is_host_enabled(musb))
439 del_timer_sync(&otg_workaround);
442 /* Shutdown the on-chip PHY and its PLL. */
443 if (data && data->set_phy_power)
444 data->set_phy_power(data->dev, 0);
447 usb_put_phy(musb->xceiv);
448 usb_nop_xceiv_unregister();
454 /* AM35x supports only 32bit read operation */
455 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
457 void __iomem *fifo = hw_ep->fifo;
461 /* Read for 32bit-aligned destination address */
462 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
463 readsl(fifo, dst, len >> 2);
468 * Now read the remaining 1 to 3 byte or complete length if
472 for (i = 0; i < (len >> 2); i++) {
473 *(u32 *) dst = musb_readl(fifo, 0);
479 val = musb_readl(fifo, 0);
480 memcpy(dst, &val, len);
485 static const struct musb_platform_ops am35x_ops = {
487 const struct musb_platform_ops am35x_ops = {
489 .init = am35x_musb_init,
490 .exit = am35x_musb_exit,
492 .enable = am35x_musb_enable,
493 .disable = am35x_musb_disable,
496 .set_mode = am35x_musb_set_mode,
497 .try_idle = am35x_musb_try_idle,
499 .set_vbus = am35x_musb_set_vbus,
504 static u64 am35x_dmamask = DMA_BIT_MASK(32);
506 static int __devinit am35x_probe(struct platform_device *pdev)
508 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
509 struct platform_device *musb;
510 struct am35x_glue *glue;
517 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
519 dev_err(&pdev->dev, "failed to allocate glue context\n");
523 musb = platform_device_alloc("musb-hdrc", -1);
525 dev_err(&pdev->dev, "failed to allocate musb device\n");
529 phy_clk = clk_get(&pdev->dev, "fck");
530 if (IS_ERR(phy_clk)) {
531 dev_err(&pdev->dev, "failed to get PHY clock\n");
532 ret = PTR_ERR(phy_clk);
536 clk = clk_get(&pdev->dev, "ick");
538 dev_err(&pdev->dev, "failed to get clock\n");
543 ret = clk_enable(phy_clk);
545 dev_err(&pdev->dev, "failed to enable PHY clock\n");
549 ret = clk_enable(clk);
551 dev_err(&pdev->dev, "failed to enable clock\n");
555 musb->dev.parent = &pdev->dev;
556 musb->dev.dma_mask = &am35x_dmamask;
557 musb->dev.coherent_dma_mask = am35x_dmamask;
559 glue->dev = &pdev->dev;
561 glue->phy_clk = phy_clk;
564 pdata->platform_ops = &am35x_ops;
566 platform_set_drvdata(pdev, glue);
568 ret = platform_device_add_resources(musb, pdev->resource,
569 pdev->num_resources);
571 dev_err(&pdev->dev, "failed to add resources\n");
575 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
577 dev_err(&pdev->dev, "failed to add platform_data\n");
581 ret = platform_device_add(musb);
583 dev_err(&pdev->dev, "failed to register musb device\n");
593 clk_disable(phy_clk);
602 platform_device_put(musb);
611 static int __devexit am35x_remove(struct platform_device *pdev)
613 struct am35x_glue *glue = platform_get_drvdata(pdev);
615 platform_device_del(glue->musb);
616 platform_device_put(glue->musb);
617 clk_disable(glue->clk);
618 clk_disable(glue->phy_clk);
620 clk_put(glue->phy_clk);
627 static int am35x_suspend(struct device *dev)
629 struct am35x_glue *glue = dev_get_drvdata(dev);
630 struct musb_hdrc_platform_data *plat = dev->platform_data;
631 struct omap_musb_board_data *data = plat->board_data;
633 /* Shutdown the on-chip PHY and its PLL. */
634 if (data && data->set_phy_power)
635 data->set_phy_power(data->dev, 0);
637 clk_disable(glue->phy_clk);
638 clk_disable(glue->clk);
643 static int am35x_resume(struct device *dev)
645 struct am35x_glue *glue = dev_get_drvdata(dev);
646 struct musb_hdrc_platform_data *plat = dev->platform_data;
647 struct omap_musb_board_data *data = plat->board_data;
650 /* Start the on-chip PHY and its PLL. */
651 if (data && data->set_phy_power)
652 data->set_phy_power(data->dev, 1);
654 ret = clk_enable(glue->phy_clk);
656 dev_err(dev, "failed to enable PHY clock\n");
660 ret = clk_enable(glue->clk);
662 dev_err(dev, "failed to enable clock\n");
669 static struct dev_pm_ops am35x_pm_ops = {
670 .suspend = am35x_suspend,
671 .resume = am35x_resume,
674 #define DEV_PM_OPS &am35x_pm_ops
676 #define DEV_PM_OPS NULL
679 static struct platform_driver am35x_driver = {
680 .probe = am35x_probe,
681 .remove = __devexit_p(am35x_remove),
683 .name = "musb-am35x",
688 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
689 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
690 MODULE_LICENSE("GPL v2");
692 static int __init am35x_init(void)
694 return platform_driver_register(&am35x_driver);
696 module_init(am35x_init);
698 static void __exit am35x_exit(void)
700 platform_driver_unregister(&am35x_driver);
702 module_exit(am35x_exit);