1 // SPDX-License-Identifier: GPL-2.0+
3 * USB HOST XHCI Controller stack
5 * Based on xHCI host controller driver in linux-kernel
8 * Copyright (C) 2008 Intel Corp.
11 * Copyright (C) 2013 Samsung Electronics Co.Ltd
12 * Authors: Vivek Gautam <gautam.vivek@samsung.com>
13 * Vikas Sajjan <vikas.sajjan@samsung.com>
17 * This file gives the xhci stack for usb3.0 looking into
18 * xhci specification Rev1.0 (5/21/10).
19 * The quirk devices support hasn't been given yet.
26 #include <asm/byteorder.h>
30 #include <asm/cache.h>
31 #include <asm/unaligned.h>
32 #include <linux/bitops.h>
33 #include <linux/bug.h>
34 #include <linux/delay.h>
35 #include <linux/errno.h>
38 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
39 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
42 static struct descriptor {
43 struct usb_hub_descriptor hub;
44 struct usb_device_descriptor device;
45 struct usb_config_descriptor config;
46 struct usb_interface_descriptor interface;
47 struct usb_endpoint_descriptor endpoint;
48 struct usb_ss_ep_comp_descriptor ep_companion;
49 } __attribute__ ((packed)) descriptor = {
51 0xc, /* bDescLength */
52 0x2a, /* bDescriptorType: hub descriptor */
53 2, /* bNrPorts -- runtime modified */
54 cpu_to_le16(0x8), /* wHubCharacteristics */
55 10, /* bPwrOn2PwrGood */
56 0, /* bHubCntrCurrent */
57 { /* Device removable */
58 } /* at most 7 ports! XXX */
62 1, /* bDescriptorType: UDESC_DEVICE */
63 cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
64 9, /* bDeviceClass: UDCLASS_HUB */
65 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
66 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
67 9, /* bMaxPacketSize: 512 bytes 2^9 */
68 0x0000, /* idVendor */
69 0x0000, /* idProduct */
70 cpu_to_le16(0x0100), /* bcdDevice */
71 1, /* iManufacturer */
73 0, /* iSerialNumber */
74 1 /* bNumConfigurations: 1 */
78 2, /* bDescriptorType: UDESC_CONFIG */
79 cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
80 1, /* bNumInterface */
81 1, /* bConfigurationValue */
82 0, /* iConfiguration */
83 0x40, /* bmAttributes: UC_SELF_POWER */
88 4, /* bDescriptorType: UDESC_INTERFACE */
89 0, /* bInterfaceNumber */
90 0, /* bAlternateSetting */
91 1, /* bNumEndpoints */
92 9, /* bInterfaceClass: UICLASS_HUB */
93 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
94 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
99 5, /* bDescriptorType: UDESC_ENDPOINT */
100 0x81, /* bEndpointAddress: IN endpoint 1 */
101 3, /* bmAttributes: UE_INTERRUPT */
102 8, /* wMaxPacketSize */
106 0x06, /* ss_bLength */
107 0x30, /* ss_bDescriptorType: SS EP Companion */
108 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
109 /* ss_bmAttributes: 1 packet per service interval */
111 /* ss_wBytesPerInterval: 15 bits for max 15 ports */
116 #if !CONFIG_IS_ENABLED(DM_USB)
117 static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
120 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
122 #if CONFIG_IS_ENABLED(DM_USB)
125 /* Find the USB controller */
126 for (dev = udev->dev;
127 device_get_uclass_id(dev) != UCLASS_USB;
130 return dev_get_priv(dev);
132 return udev->controller;
137 * Waits for as per specified amount of time
138 * for the "result" to match with "done"
140 * @param ptr pointer to the register to be read
141 * @param mask mask for the value read
142 * @param done value to be campared with result
143 * @param usec time to wait till
144 * @return 0 if handshake is success else < 0 on failure
146 static int handshake(uint32_t volatile *ptr, uint32_t mask,
147 uint32_t done, int usec)
152 result = xhci_readl(ptr);
153 if (result == ~(uint32_t)0)
166 * Set the run bit and wait for the host to be running.
168 * @param hcor pointer to host controller operation registers
169 * @return status of the Handshake
171 static int xhci_start(struct xhci_hcor *hcor)
176 puts("Starting the controller\n");
177 temp = xhci_readl(&hcor->or_usbcmd);
179 xhci_writel(&hcor->or_usbcmd, temp);
182 * Wait for the HCHalted Status bit to be 0 to indicate the host is
185 ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
187 debug("Host took too long to start, "
188 "waited %u microseconds.\n",
194 * Resets the XHCI Controller
196 * @param hcor pointer to host controller operation registers
197 * @return -EBUSY if XHCI Controller is not halted else status of handshake
199 static int xhci_reset(struct xhci_hcor *hcor)
205 /* Halting the Host first */
206 debug("// Halt the HC: %p\n", hcor);
207 state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
209 cmd = xhci_readl(&hcor->or_usbcmd);
211 xhci_writel(&hcor->or_usbcmd, cmd);
214 ret = handshake(&hcor->or_usbsts,
215 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
217 printf("Host not halted after %u microseconds.\n",
222 debug("// Reset the HC\n");
223 cmd = xhci_readl(&hcor->or_usbcmd);
225 xhci_writel(&hcor->or_usbcmd, cmd);
227 ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
232 * xHCI cannot write to any doorbells or operational registers other
233 * than status until the "Controller Not Ready" flag is cleared.
235 return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
239 * Used for passing endpoint bitmasks between the core and HCDs.
240 * Find the index for an endpoint given its descriptor.
241 * Use the return value to right shift 1 for the bitmask.
243 * Index = (epnum * 2) + direction - 1,
244 * where direction = 0 for OUT, 1 for IN.
245 * For control endpoints, the IN index is used (OUT index is unused), so
246 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
248 * @param desc USB enpdoint Descriptor
249 * @return index of the Endpoint
251 static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
255 if (usb_endpoint_xfer_control(desc))
256 index = (unsigned int)(usb_endpoint_num(desc) * 2);
258 index = (unsigned int)((usb_endpoint_num(desc) * 2) -
259 (usb_endpoint_dir_in(desc) ? 0 : 1));
265 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
266 * microframes, rounded down to nearest power of 2.
268 static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval,
269 unsigned int min_exponent,
270 unsigned int max_exponent)
272 unsigned int interval;
274 interval = fls(desc_interval) - 1;
275 interval = clamp_val(interval, min_exponent, max_exponent);
276 if ((1 << interval) != desc_interval)
277 debug("rounding interval to %d microframes, "\
278 "ep desc says %d microframes\n",
279 1 << interval, desc_interval);
284 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
285 struct usb_endpoint_descriptor *endpt_desc)
287 if (endpt_desc->bInterval == 0)
290 return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15);
293 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
294 struct usb_endpoint_descriptor *endpt_desc)
296 return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10);
300 * Convert interval expressed as 2^(bInterval - 1) == interval into
301 * straight exponent value 2^n == interval.
303 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
304 struct usb_endpoint_descriptor *endpt_desc)
306 unsigned int interval;
308 interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1;
309 if (interval != endpt_desc->bInterval - 1)
310 debug("ep %#x - rounding interval to %d %sframes\n",
311 endpt_desc->bEndpointAddress, 1 << interval,
312 udev->speed == USB_SPEED_FULL ? "" : "micro");
314 if (udev->speed == USB_SPEED_FULL) {
316 * Full speed isoc endpoints specify interval in frames,
317 * not microframes. We are using microframes everywhere,
318 * so adjust accordingly.
320 interval += 3; /* 1 frame = 2^3 uframes */
327 * Return the polling or NAK interval.
329 * The polling interval is expressed in "microframes". If xHCI's Interval field
330 * is set to N, it will service the endpoint every 2^(Interval)*125us.
332 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
335 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
336 struct usb_endpoint_descriptor *endpt_desc)
338 unsigned int interval = 0;
340 switch (udev->speed) {
343 if (usb_endpoint_xfer_control(endpt_desc) ||
344 usb_endpoint_xfer_bulk(endpt_desc)) {
345 interval = xhci_parse_microframe_interval(udev,
349 /* Fall through - SS and HS isoc/int have same decoding */
351 case USB_SPEED_SUPER:
352 if (usb_endpoint_xfer_int(endpt_desc) ||
353 usb_endpoint_xfer_isoc(endpt_desc)) {
354 interval = xhci_parse_exponent_interval(udev,
360 if (usb_endpoint_xfer_isoc(endpt_desc)) {
361 interval = xhci_parse_exponent_interval(udev,
366 * Fall through for interrupt endpoint interval decoding
367 * since it uses the same rules as low speed interrupt
372 if (usb_endpoint_xfer_int(endpt_desc) ||
373 usb_endpoint_xfer_isoc(endpt_desc)) {
374 interval = xhci_parse_frame_interval(udev, endpt_desc);
386 * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
387 * High speed endpoint descriptors can define "the number of additional
388 * transaction opportunities per microframe", but that goes in the Max Burst
389 * endpoint context field.
391 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
392 struct usb_endpoint_descriptor *endpt_desc,
393 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
395 if (udev->speed < USB_SPEED_SUPER ||
396 !usb_endpoint_xfer_isoc(endpt_desc))
399 return ss_ep_comp_desc->bmAttributes;
402 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
403 struct usb_endpoint_descriptor *endpt_desc,
404 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
406 /* Super speed and Plus have max burst in ep companion desc */
407 if (udev->speed >= USB_SPEED_SUPER)
408 return ss_ep_comp_desc->bMaxBurst;
410 if (udev->speed == USB_SPEED_HIGH &&
411 (usb_endpoint_xfer_isoc(endpt_desc) ||
412 usb_endpoint_xfer_int(endpt_desc)))
413 return usb_endpoint_maxp_mult(endpt_desc) - 1;
419 * Return the maximum endpoint service interval time (ESIT) payload.
420 * Basically, this is the maxpacket size, multiplied by the burst size
423 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
424 struct usb_endpoint_descriptor *endpt_desc,
425 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
430 /* Only applies for interrupt or isochronous endpoints */
431 if (usb_endpoint_xfer_control(endpt_desc) ||
432 usb_endpoint_xfer_bulk(endpt_desc))
435 /* SuperSpeed Isoc ep with less than 48k per esit */
436 if (udev->speed >= USB_SPEED_SUPER)
437 return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval);
439 max_packet = usb_endpoint_maxp(endpt_desc);
440 max_burst = usb_endpoint_maxp_mult(endpt_desc);
442 /* A 0 in max burst means 1 transfer per ESIT */
443 return max_packet * max_burst;
447 * Issue a configure endpoint command or evaluate context command
448 * and wait for it to finish.
450 * @param udev pointer to the Device Data Structure
451 * @param ctx_change flag to indicate the Context has changed or NOT
452 * @return 0 on success, -1 on failure
454 static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
456 struct xhci_container_ctx *in_ctx;
457 struct xhci_virt_device *virt_dev;
458 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
459 union xhci_trb *event;
461 virt_dev = ctrl->devs[udev->slot_id];
462 in_ctx = virt_dev->in_ctx;
464 xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
465 xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
466 ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
467 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
468 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
471 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
473 debug("Successful %s command\n",
474 ctx_change ? "Evaluate Context" : "Configure Endpoint");
477 printf("ERROR: %s command returned completion code %d.\n",
478 ctx_change ? "Evaluate Context" : "Configure Endpoint",
479 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
483 xhci_acknowledge_event(ctrl);
489 * Configure the endpoint, programming the device contexts.
491 * @param udev pointer to the USB device structure
492 * @return returns the status of the xhci_configure_endpoints
494 static int xhci_set_configuration(struct usb_device *udev)
496 struct xhci_container_ctx *in_ctx;
497 struct xhci_container_ctx *out_ctx;
498 struct xhci_input_control_ctx *ctrl_ctx;
499 struct xhci_slot_ctx *slot_ctx;
500 struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
505 unsigned int ep_type;
506 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
510 int slot_id = udev->slot_id;
511 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
512 struct usb_interface *ifdesc;
513 u32 max_esit_payload;
514 unsigned int interval;
516 unsigned int max_burst;
517 unsigned int avg_trb_len;
518 unsigned int err_count = 0;
520 out_ctx = virt_dev->out_ctx;
521 in_ctx = virt_dev->in_ctx;
523 num_of_ep = udev->config.if_desc[0].no_of_ep;
524 ifdesc = &udev->config.if_desc[0];
526 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
527 /* Initialize the input context control */
528 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
529 ctrl_ctx->drop_flags = 0;
531 /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
532 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
533 ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
534 ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
535 if (max_ep_flag < ep_flag)
536 max_ep_flag = ep_flag;
539 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
542 xhci_slot_copy(ctrl, in_ctx, out_ctx);
543 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
544 slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK));
545 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
547 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
549 /* filling up ep contexts */
550 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
551 struct usb_endpoint_descriptor *endpt_desc = NULL;
552 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
554 endpt_desc = &ifdesc->ep_desc[cur_ep];
555 ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep];
559 * Get values to fill the endpoint context, mostly from ep
560 * descriptor. The average TRB buffer lengt for bulk endpoints
561 * is unclear as we have no clue on scatter gather list entry
562 * size. For Isoc and Int, set it to max available.
563 * See xHCI 1.1 spec 4.14.1.1 for details.
565 max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc,
567 interval = xhci_get_endpoint_interval(udev, endpt_desc);
568 mult = xhci_get_endpoint_mult(udev, endpt_desc,
570 max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc,
572 avg_trb_len = max_esit_payload;
574 ep_index = xhci_get_ep_index(endpt_desc);
575 ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
577 /* Allocate the ep rings */
578 virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
579 if (!virt_dev->eps[ep_index].ring)
582 /*NOTE: ep_desc[0] actually represents EP1 and so on */
583 dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
584 ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
586 ep_ctx[ep_index]->ep_info =
587 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
588 EP_INTERVAL(interval) | EP_MULT(mult));
590 ep_ctx[ep_index]->ep_info2 =
591 cpu_to_le32(ep_type << EP_TYPE_SHIFT);
592 ep_ctx[ep_index]->ep_info2 |=
593 cpu_to_le32(MAX_PACKET
594 (get_unaligned(&endpt_desc->wMaxPacketSize)));
596 /* Allow 3 retries for everything but isoc, set CErr = 3 */
597 if (!usb_endpoint_xfer_isoc(endpt_desc))
599 ep_ctx[ep_index]->ep_info2 |=
600 cpu_to_le32(MAX_BURST(max_burst) |
601 ERROR_COUNT(err_count));
604 virt_dev->eps[ep_index].ring->enqueue;
605 ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
606 virt_dev->eps[ep_index].ring->cycle_state);
610 * 'Average TRB Length' should be 8 for control endpoints.
612 if (usb_endpoint_xfer_control(endpt_desc))
614 ep_ctx[ep_index]->tx_info =
615 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
616 EP_AVG_TRB_LENGTH(avg_trb_len));
619 * The MediaTek xHCI defines some extra SW parameters which
620 * are put into reserved DWs in Slot and Endpoint Contexts
621 * for synchronous endpoints.
623 if (IS_ENABLED(CONFIG_USB_XHCI_MTK)) {
624 ep_ctx[ep_index]->reserved[0] =
625 cpu_to_le32(EP_BPKTS(1) | EP_BBM(1));
629 return xhci_configure_endpoints(udev, false);
633 * Issue an Address Device command (which will issue a SetAddress request to
636 * @param udev pointer to the Device Data Structure
637 * @return 0 if successful else error code on failure
639 static int xhci_address_device(struct usb_device *udev, int root_portnr)
642 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
643 struct xhci_slot_ctx *slot_ctx;
644 struct xhci_input_control_ctx *ctrl_ctx;
645 struct xhci_virt_device *virt_dev;
646 int slot_id = udev->slot_id;
647 union xhci_trb *event;
649 virt_dev = ctrl->devs[slot_id];
652 * This is the first Set Address since device plug-in
653 * so setting up the slot context.
655 debug("Setting up addressable devices %p\n", ctrl->dcbaa);
656 xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
658 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
659 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
660 ctrl_ctx->drop_flags = 0;
662 xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
663 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
664 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
666 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
669 printf("Setup ERROR: address device command for slot %d.\n",
674 puts("Device not responding to set address.\n");
678 puts("ERROR: Incompatible device"
679 "for address device command.\n");
683 debug("Successful Address Device command\n");
687 printf("ERROR: unexpected command completion code 0x%x.\n",
688 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
693 xhci_acknowledge_event(ctrl);
697 * TODO: Unsuccessful Address Device command shall leave the
698 * slot in default state. So, issue Disable Slot command now.
702 xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
703 virt_dev->out_ctx->size);
704 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
706 debug("xHC internal address is: %d\n",
707 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
713 * Issue Enable slot command to the controller to allocate
714 * device slot and assign the slot id. It fails if the xHC
715 * ran out of device slots, the Enable Slot command timed out,
716 * or allocating memory failed.
718 * @param udev pointer to the Device Data Structure
719 * @return Returns 0 on succes else return error code on failure
721 static int _xhci_alloc_device(struct usb_device *udev)
723 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
724 union xhci_trb *event;
728 * Root hub will be first device to be initailized.
729 * If this device is root-hub, don't do any xHC related
732 if (ctrl->rootdev == 0) {
733 udev->speed = USB_SPEED_SUPER;
737 xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
738 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
739 BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
742 udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
744 xhci_acknowledge_event(ctrl);
746 ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
749 * TODO: Unsuccessful Address Device command shall leave
750 * the slot in default. So, issue Disable Slot command now.
752 puts("Could not allocate xHCI USB device data structures\n");
759 #if !CONFIG_IS_ENABLED(DM_USB)
760 int usb_alloc_device(struct usb_device *udev)
762 return _xhci_alloc_device(udev);
767 * Full speed devices may have a max packet size greater than 8 bytes, but the
768 * USB core doesn't know that until it reads the first 8 bytes of the
769 * descriptor. If the usb_device's max packet size changes after that point,
770 * we need to issue an evaluate context command and wait on it.
772 * @param udev pointer to the Device Data Structure
773 * @return returns the status of the xhci_configure_endpoints
775 int xhci_check_maxpacket(struct usb_device *udev)
777 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
778 unsigned int slot_id = udev->slot_id;
779 int ep_index = 0; /* control endpoint */
780 struct xhci_container_ctx *in_ctx;
781 struct xhci_container_ctx *out_ctx;
782 struct xhci_input_control_ctx *ctrl_ctx;
783 struct xhci_ep_ctx *ep_ctx;
785 int hw_max_packet_size;
788 out_ctx = ctrl->devs[slot_id]->out_ctx;
789 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
791 ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
792 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
793 max_packet_size = udev->epmaxpacketin[0];
794 if (hw_max_packet_size != max_packet_size) {
795 debug("Max Packet Size for ep 0 changed.\n");
796 debug("Max packet size in usb_device = %d\n", max_packet_size);
797 debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
798 debug("Issuing evaluate context command.\n");
800 /* Set up the modified control endpoint 0 */
801 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
802 ctrl->devs[slot_id]->out_ctx, ep_index);
803 in_ctx = ctrl->devs[slot_id]->in_ctx;
804 ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
805 ep_ctx->ep_info2 &= cpu_to_le32(~((0xffff & MAX_PACKET_MASK)
806 << MAX_PACKET_SHIFT));
807 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
810 * Set up the input context flags for the command
811 * FIXME: This won't work if a non-default control endpoint
812 * changes max packet sizes.
814 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
815 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
816 ctrl_ctx->drop_flags = 0;
818 ret = xhci_configure_endpoints(udev, true);
824 * Clears the Change bits of the Port Status Register
826 * @param wValue request value
827 * @param wIndex request index
828 * @param addr address of posrt status register
829 * @param port_status state of port status register
832 static void xhci_clear_port_change_bit(u16 wValue,
833 u16 wIndex, volatile uint32_t *addr, u32 port_status)
835 char *port_change_bit;
839 case USB_PORT_FEAT_C_RESET:
841 port_change_bit = "reset";
843 case USB_PORT_FEAT_C_CONNECTION:
845 port_change_bit = "connect";
847 case USB_PORT_FEAT_C_OVER_CURRENT:
849 port_change_bit = "over-current";
851 case USB_PORT_FEAT_C_ENABLE:
853 port_change_bit = "enable/disable";
855 case USB_PORT_FEAT_C_SUSPEND:
857 port_change_bit = "suspend/resume";
860 /* Should never happen */
864 /* Change bits are all write 1 to clear */
865 xhci_writel(addr, port_status | status);
867 port_status = xhci_readl(addr);
868 debug("clear port %s change, actual port %d status = 0x%x\n",
869 port_change_bit, wIndex, port_status);
873 * Save Read Only (RO) bits and save read/write bits where
874 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
875 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
877 * @param state state of the Port Status and Control Regsiter
878 * @return a value that would result in the port being in the
879 * same state, if the value was written to the port
880 * status control register.
882 static u32 xhci_port_state_to_neutral(u32 state)
884 /* Save read-only status and port state */
885 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
889 * Submits the Requests to the XHCI Host Controller
891 * @param udev pointer to the USB device structure
892 * @param pipe contains the DIR_IN or OUT , devnum
893 * @param buffer buffer to be read/written based on the request
894 * @return returns 0 if successful else -1 on failure
896 static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
897 void *buffer, struct devrequest *req)
904 volatile uint32_t *status_reg;
905 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
906 struct xhci_hccr *hccr = ctrl->hccr;
907 struct xhci_hcor *hcor = ctrl->hcor;
908 int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
910 if ((req->requesttype & USB_RT_PORT) &&
911 le16_to_cpu(req->index) > max_ports) {
912 printf("The request port(%d) exceeds maximum port number\n",
913 le16_to_cpu(req->index) - 1);
917 status_reg = (volatile uint32_t *)
918 (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
921 typeReq = req->request | req->requesttype << 8;
924 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
925 switch (le16_to_cpu(req->value) >> 8) {
927 debug("USB_DT_DEVICE request\n");
928 srcptr = &descriptor.device;
932 debug("USB_DT_CONFIG config\n");
933 srcptr = &descriptor.config;
937 debug("USB_DT_STRING config\n");
938 switch (le16_to_cpu(req->value) & 0xff) {
939 case 0: /* Language */
940 srcptr = "\4\3\11\4";
943 case 1: /* Vendor String */
944 srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
947 case 2: /* Product Name */
948 srcptr = "\52\3X\0H\0C\0I\0 "
950 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
954 printf("unknown value DT_STRING %x\n",
955 le16_to_cpu(req->value));
960 printf("unknown value %x\n", le16_to_cpu(req->value));
964 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
965 switch (le16_to_cpu(req->value) >> 8) {
968 debug("USB_DT_HUB config\n");
969 srcptr = &descriptor.hub;
973 printf("unknown value %x\n", le16_to_cpu(req->value));
977 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
978 debug("USB_REQ_SET_ADDRESS\n");
979 ctrl->rootdev = le16_to_cpu(req->value);
981 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
984 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
985 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
990 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
991 memset(tmpbuf, 0, 4);
992 reg = xhci_readl(status_reg);
993 if (reg & PORT_CONNECT) {
994 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
995 switch (reg & DEV_SPEED_MASK) {
997 debug("SPEED = FULLSPEED\n");
1000 debug("SPEED = LOWSPEED\n");
1001 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
1004 debug("SPEED = HIGHSPEED\n");
1005 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
1008 debug("SPEED = SUPERSPEED\n");
1009 tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
1014 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
1015 if ((reg & PORT_PLS_MASK) == XDEV_U3)
1016 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
1018 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
1019 if (reg & PORT_RESET)
1020 tmpbuf[0] |= USB_PORT_STAT_RESET;
1021 if (reg & PORT_POWER)
1023 * XXX: This Port power bit (for USB 3.0 hub)
1024 * we are faking in USB 2.0 hub port status;
1025 * since there's a change in bit positions in
1027 * USB 2.0 port status PP is at position[8]
1028 * USB 3.0 port status PP is at position[9]
1029 * So, we are still keeping it at position [8]
1031 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
1033 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
1035 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
1037 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
1039 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
1044 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
1045 reg = xhci_readl(status_reg);
1046 reg = xhci_port_state_to_neutral(reg);
1047 switch (le16_to_cpu(req->value)) {
1048 case USB_PORT_FEAT_ENABLE:
1050 xhci_writel(status_reg, reg);
1052 case USB_PORT_FEAT_POWER:
1054 xhci_writel(status_reg, reg);
1056 case USB_PORT_FEAT_RESET:
1058 xhci_writel(status_reg, reg);
1061 printf("unknown feature %x\n", le16_to_cpu(req->value));
1065 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
1066 reg = xhci_readl(status_reg);
1067 reg = xhci_port_state_to_neutral(reg);
1068 switch (le16_to_cpu(req->value)) {
1069 case USB_PORT_FEAT_ENABLE:
1072 case USB_PORT_FEAT_POWER:
1075 case USB_PORT_FEAT_C_RESET:
1076 case USB_PORT_FEAT_C_CONNECTION:
1077 case USB_PORT_FEAT_C_OVER_CURRENT:
1078 case USB_PORT_FEAT_C_ENABLE:
1079 xhci_clear_port_change_bit((le16_to_cpu(req->value)),
1080 le16_to_cpu(req->index),
1084 printf("unknown feature %x\n", le16_to_cpu(req->value));
1087 xhci_writel(status_reg, reg);
1090 puts("Unknown request\n");
1094 debug("scrlen = %d\n req->length = %d\n",
1095 srclen, le16_to_cpu(req->length));
1097 len = min(srclen, (int)le16_to_cpu(req->length));
1099 if (srcptr != NULL && len > 0)
1100 memcpy(buffer, srcptr, len);
1102 debug("Len is 0\n");
1104 udev->act_len = len;
1111 udev->status = USB_ST_STALLED;
1117 * Submits the INT request to XHCI Host cotroller
1119 * @param udev pointer to the USB device
1120 * @param pipe contains the DIR_IN or OUT , devnum
1121 * @param buffer buffer to be read/written based on the request
1122 * @param length length of the buffer
1123 * @param interval interval of the interrupt
1126 static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
1127 void *buffer, int length, int interval,
1130 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1131 printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1136 * xHCI uses normal TRBs for both bulk and interrupt. When the
1137 * interrupt endpoint is to be serviced, the xHC will consume
1138 * (at most) one TD. A TD (comprised of sg list entries) can
1139 * take several service intervals to transmit.
1141 return xhci_bulk_tx(udev, pipe, length, buffer);
1145 * submit the BULK type of request to the USB Device
1147 * @param udev pointer to the USB device
1148 * @param pipe contains the DIR_IN or OUT , devnum
1149 * @param buffer buffer to be read/written based on the request
1150 * @param length length of the buffer
1151 * @return returns 0 if successful else -1 on failure
1153 static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
1154 void *buffer, int length)
1156 if (usb_pipetype(pipe) != PIPE_BULK) {
1157 printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1161 return xhci_bulk_tx(udev, pipe, length, buffer);
1165 * submit the control type of request to the Root hub/Device based on the devnum
1167 * @param udev pointer to the USB device
1168 * @param pipe contains the DIR_IN or OUT , devnum
1169 * @param buffer buffer to be read/written based on the request
1170 * @param length length of the buffer
1171 * @param setup Request type
1172 * @param root_portnr Root port number that this device is on
1173 * @return returns 0 if successful else -1 on failure
1175 static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
1176 void *buffer, int length,
1177 struct devrequest *setup, int root_portnr)
1179 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
1182 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1183 printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
1187 if (usb_pipedevice(pipe) == ctrl->rootdev)
1188 return xhci_submit_root(udev, pipe, buffer, setup);
1190 if (setup->request == USB_REQ_SET_ADDRESS &&
1191 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1192 return xhci_address_device(udev, root_portnr);
1194 if (setup->request == USB_REQ_SET_CONFIGURATION &&
1195 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1196 ret = xhci_set_configuration(udev);
1198 puts("Failed to configure xHCI endpoint\n");
1203 return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
1206 static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
1208 struct xhci_hccr *hccr;
1209 struct xhci_hcor *hcor;
1217 * Program the Number of Device Slots Enabled field in the CONFIG
1218 * register with the max value of slots the HC can handle.
1220 val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
1221 val2 = xhci_readl(&hcor->or_config);
1222 val |= (val2 & ~HCS_SLOTS_MASK);
1223 xhci_writel(&hcor->or_config, val);
1225 /* initializing xhci data structures */
1226 if (xhci_mem_init(ctrl, hccr, hcor) < 0)
1229 reg = xhci_readl(&hccr->cr_hcsparams1);
1230 descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
1231 HCS_MAX_PORTS_SHIFT);
1232 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1234 /* Port Indicators */
1235 reg = xhci_readl(&hccr->cr_hccparams);
1236 if (HCS_INDICATOR(reg))
1237 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1238 | 0x80, &descriptor.hub.wHubCharacteristics);
1240 /* Port Power Control */
1242 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1243 | 0x01, &descriptor.hub.wHubCharacteristics);
1245 if (xhci_start(hcor)) {
1250 /* Zero'ing IRQ control register and IRQ pending register */
1251 xhci_writel(&ctrl->ir_set->irq_control, 0x0);
1252 xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
1254 reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
1255 printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
1260 static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
1264 xhci_reset(ctrl->hcor);
1266 debug("// Disabling event ring interrupts\n");
1267 temp = xhci_readl(&ctrl->hcor->or_usbsts);
1268 xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
1269 temp = xhci_readl(&ctrl->ir_set->irq_pending);
1270 xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
1275 #if !CONFIG_IS_ENABLED(DM_USB)
1276 int submit_control_msg(struct usb_device *udev, unsigned long pipe,
1277 void *buffer, int length, struct devrequest *setup)
1279 struct usb_device *hop = udev;
1282 while (hop->parent->parent)
1285 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
1289 int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
1292 return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
1295 int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
1296 int length, int interval, bool nonblock)
1298 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
1303 * Intialises the XHCI host controller
1304 * and allocates the necessary data structures
1306 * @param index index to the host controller data structure
1307 * @return pointer to the intialised controller
1309 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1311 struct xhci_hccr *hccr;
1312 struct xhci_hcor *hcor;
1313 struct xhci_ctrl *ctrl;
1318 if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
1321 if (xhci_reset(hcor) != 0)
1324 ctrl = &xhcic[index];
1329 ret = xhci_lowlevel_init(ctrl);
1335 *controller = &xhcic[index];
1342 * Stops the XHCI host controller
1343 * and cleans up all the related data structures
1345 * @param index index to the host controller data structure
1348 int usb_lowlevel_stop(int index)
1350 struct xhci_ctrl *ctrl = (xhcic + index);
1353 xhci_lowlevel_stop(ctrl);
1354 xhci_hcd_stop(index);
1360 #endif /* CONFIG_IS_ENABLED(DM_USB) */
1362 #if CONFIG_IS_ENABLED(DM_USB)
1364 static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1365 unsigned long pipe, void *buffer, int length,
1366 struct devrequest *setup)
1368 struct usb_device *uhop;
1369 struct udevice *hub;
1370 int root_portnr = 0;
1372 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1373 dev->name, udev, udev->dev->name, udev->portnr);
1375 if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
1376 /* Figure out our port number on the root hub */
1377 if (usb_hub_is_root_hub(hub)) {
1378 root_portnr = udev->portnr;
1380 while (!usb_hub_is_root_hub(hub->parent))
1382 uhop = dev_get_parent_priv(hub);
1383 root_portnr = uhop->portnr;
1387 struct usb_device *hop = udev;
1390 while (hop->parent->parent)
1393 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
1397 static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1398 unsigned long pipe, void *buffer, int length)
1400 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1401 return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
1404 static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1405 unsigned long pipe, void *buffer, int length,
1406 int interval, bool nonblock)
1408 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1409 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
1413 static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
1415 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1416 return _xhci_alloc_device(udev);
1419 static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
1421 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1422 struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
1423 struct xhci_virt_device *virt_dev;
1424 struct xhci_input_control_ctx *ctrl_ctx;
1425 struct xhci_container_ctx *out_ctx;
1426 struct xhci_container_ctx *in_ctx;
1427 struct xhci_slot_ctx *slot_ctx;
1428 int slot_id = udev->slot_id;
1429 unsigned think_time;
1431 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1433 /* Ignore root hubs */
1434 if (usb_hub_is_root_hub(udev->dev))
1437 virt_dev = ctrl->devs[slot_id];
1440 out_ctx = virt_dev->out_ctx;
1441 in_ctx = virt_dev->in_ctx;
1443 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1444 /* Initialize the input context control */
1445 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1446 ctrl_ctx->drop_flags = 0;
1448 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
1451 xhci_slot_copy(ctrl, in_ctx, out_ctx);
1452 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
1454 /* Update hub related fields */
1455 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
1457 * refer to section 6.2.2: MTT should be 0 for full speed hub,
1458 * but it may be already set to 1 when setup an xHCI virtual
1459 * device, so clear it anyway.
1462 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1463 else if (udev->speed == USB_SPEED_FULL)
1464 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
1465 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
1467 * Set TT think time - convert from ns to FS bit times.
1468 * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
1470 * 0 = 8 FS bit times, 1 = 16 FS bit times,
1471 * 2 = 24 FS bit times, 3 = 32 FS bit times.
1473 * This field shall be 0 if the device is not a high-spped hub.
1475 think_time = hub->tt.think_time;
1476 if (think_time != 0)
1477 think_time = (think_time / 666) - 1;
1478 if (udev->speed == USB_SPEED_HIGH)
1479 slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
1480 slot_ctx->dev_state = 0;
1482 return xhci_configure_endpoints(udev, false);
1485 static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size)
1488 * xHCD allocates one segment which includes 64 TRBs for each endpoint
1489 * and the last TRB in this segment is configured as a link TRB to form
1490 * a TRB ring. Each TRB can transfer up to 64K bytes, however data
1491 * buffers referenced by transfer TRBs shall not span 64KB boundaries.
1492 * Hence the maximum number of TRBs we can use in one transfer is 62.
1494 *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE;
1499 int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
1500 struct xhci_hcor *hcor)
1502 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1503 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1506 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
1512 * XHCI needs to issue a Address device command to setup
1513 * proper device context structures, before it can interact
1514 * with the device. So a get_descriptor will fail before any
1515 * of that is done for XHCI unlike EHCI.
1517 priv->desc_before_addr = false;
1519 ret = xhci_reset(hcor);
1525 ret = xhci_lowlevel_init(ctrl);
1532 debug("%s: failed, ret=%d\n", __func__, ret);
1536 int xhci_deregister(struct udevice *dev)
1538 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1540 xhci_lowlevel_stop(ctrl);
1546 struct dm_usb_ops xhci_usb_ops = {
1547 .control = xhci_submit_control_msg,
1548 .bulk = xhci_submit_bulk_msg,
1549 .interrupt = xhci_submit_int_msg,
1550 .alloc_device = xhci_alloc_device,
1551 .update_hub_device = xhci_update_hub_device,
1552 .get_max_xfer_size = xhci_get_max_xfer_size,