drivers/usb/host/xhci-dwc3.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  *
   5  * DWC3 controller driver
   6  *
   7  * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <generic-phy.h>
  13 #include <usb.h>
  14 #include <dwc3-uboot.h>
  15
  16 #include <usb/xhci.h>
  17 #include <asm/io.h>
  18 #include <linux/usb/dwc3.h>
  19 #include <linux/usb/otg.h>
  20
  21 struct xhci_dwc3_platdata {
  22         struct phy_bulk *usb_phys;
  23 };
  24
  25 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
  26 {
  27         clrsetbits_le32(&dwc3_reg->g_ctl,
  28                         DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
  29                         DWC3_GCTL_PRTCAPDIR(mode));
  30 }
  31
  32 static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
  33 {
  34         /* Assert USB3 PHY reset */
  35         setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  36
  37         /* Assert USB2 PHY reset */
  38         setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  39
  40         mdelay(100);
  41
  42         /* Clear USB3 PHY reset */
  43         clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  44
  45         /* Clear USB2 PHY reset */
  46         clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  47 }
  48
  49 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
  50 {
  51         /* Before Resetting PHY, put Core in Reset */
  52         setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  53
  54         /* reset USB3 phy - if required */
  55         dwc3_phy_reset(dwc3_reg);
  56
  57         mdelay(100);
  58
  59         /* After PHYs are stable we can take Core out of reset state */
  60         clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  61 }
  62
  63 int dwc3_core_init(struct dwc3 *dwc3_reg)
  64 {
  65         u32 reg;
  66         u32 revision;
  67         unsigned int dwc3_hwparams1;
  68
  69         revision = readl(&dwc3_reg->g_snpsid);
  70         /* This should read as U3 followed by revision number */
  71         if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
  72                 puts("this is not a DesignWare USB3 DRD Core\n");
  73                 return -1;
  74         }
  75
  76         dwc3_core_soft_reset(dwc3_reg);
  77
  78         dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
  79
  80         reg = readl(&dwc3_reg->g_ctl);
  81         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  82         reg &= ~DWC3_GCTL_DISSCRAMBLE;
  83         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
  84         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  85                 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  86                 break;
  87         default:
  88                 debug("No power optimization available\n");
  89         }
  90
  91         /*
  92          * WORKAROUND: DWC3 revisions <1.90a have a bug
  93          * where the device can fail to connect at SuperSpeed
  94          * and falls back to high-speed mode which causes
  95          * the device to enter a Connect/Disconnect loop
  96          */
  97         if ((revision & DWC3_REVISION_MASK) < 0x190a)
  98                 reg |= DWC3_GCTL_U2RSTECN;
  99
 100         writel(reg, &dwc3_reg->g_ctl);
 101
 102         return 0;
 103 }
 104
 105 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
 106 {
 107         setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
 108                         GFLADJ_30MHZ(val));
 109 }
 110
 111 #if CONFIG_IS_ENABLED(DM_USB)
 112 static int xhci_dwc3_probe(struct udevice *dev)
 113 {
 114         struct xhci_hcor *hcor;
 115         struct xhci_hccr *hccr;
 116         struct dwc3 *dwc3_reg;
 117         enum usb_dr_mode dr_mode;
 118         struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
 119         const char *phy;
 120         u32 reg;
 121         int ret;
 122
 123         hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
 124         hcor = (struct xhci_hcor *)((uintptr_t)hccr +
 125                         HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
 126
 127         ret = dwc3_setup_phy(dev, plat->usb_phys);
 128         if (ret && (ret != -ENOTSUPP))
 129                 return ret;
 130
 131         dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
 132
 133         dwc3_core_init(dwc3_reg);
 134
 135         /* Set dwc3 usb2 phy config */
 136         reg = readl(&dwc3_reg->g_usb2phycfg[0]);
 137
 138         phy = dev_read_string(dev, "phy_type");
 139         if (phy && strcmp(phy, "utmi_wide") == 0) {
 140                 reg |= DWC3_GUSB2PHYCFG_PHYIF;
 141                 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
 142                 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
 143         }
 144
 145         if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
 146                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 147
 148         if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
 149                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 150
 151         if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
 152                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 153
 154         writel(reg, &dwc3_reg->g_usb2phycfg[0]);
 155
 156         dr_mode = usb_get_dr_mode(dev->node);
 157         if (dr_mode == USB_DR_MODE_UNKNOWN)
 158                 /* by default set dual role mode to HOST */
 159                 dr_mode = USB_DR_MODE_HOST;
 160
 161         dwc3_set_mode(dwc3_reg, dr_mode);
 162
 163         return xhci_register(dev, hccr, hcor);
 164 }
 165
 166 static int xhci_dwc3_remove(struct udevice *dev)
 167 {
 168         struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
 169
 170         dwc3_shutdown_phy(dev, plat->usb_phys);
 171
 172         return xhci_deregister(dev);
 173 }
 174
 175 static const struct udevice_id xhci_dwc3_ids[] = {
 176         { .compatible = "snps,dwc3" },
 177         { }
 178 };
 179
 180 U_BOOT_DRIVER(xhci_dwc3) = {
 181         .name = "xhci-dwc3",
 182         .id = UCLASS_USB,
 183         .of_match = xhci_dwc3_ids,
 184         .probe = xhci_dwc3_probe,
 185         .remove = xhci_dwc3_remove,
 186         .ops = &xhci_usb_ops,
 187         .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
 188         .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
 189         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 190 };
 191 #endif