37b59c80fd82b7a063f72105cbcfcaf0b1b01d72
[oweals/u-boot.git] / drivers / usb / host / xhci-dwc3.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2015 Freescale Semiconductor, Inc.
4  *
5  * DWC3 controller driver
6  *
7  * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
8  */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <generic-phy.h>
13 #include <log.h>
14 #include <usb.h>
15 #include <dwc3-uboot.h>
16
17 #include <usb/xhci.h>
18 #include <asm/io.h>
19 #include <linux/usb/dwc3.h>
20 #include <linux/usb/otg.h>
21
22 struct xhci_dwc3_platdata {
23         struct phy_bulk *usb_phys;
24 };
25
26 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
27 {
28         clrsetbits_le32(&dwc3_reg->g_ctl,
29                         DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
30                         DWC3_GCTL_PRTCAPDIR(mode));
31 }
32
33 static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
34 {
35         /* Assert USB3 PHY reset */
36         setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
37
38         /* Assert USB2 PHY reset */
39         setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
40
41         mdelay(100);
42
43         /* Clear USB3 PHY reset */
44         clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
45
46         /* Clear USB2 PHY reset */
47         clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
48 }
49
50 void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
51 {
52         /* Before Resetting PHY, put Core in Reset */
53         setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
54
55         /* reset USB3 phy - if required */
56         dwc3_phy_reset(dwc3_reg);
57
58         mdelay(100);
59
60         /* After PHYs are stable we can take Core out of reset state */
61         clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
62 }
63
64 int dwc3_core_init(struct dwc3 *dwc3_reg)
65 {
66         u32 reg;
67         u32 revision;
68         unsigned int dwc3_hwparams1;
69
70         revision = readl(&dwc3_reg->g_snpsid);
71         /* This should read as U3 followed by revision number */
72         if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
73                 puts("this is not a DesignWare USB3 DRD Core\n");
74                 return -1;
75         }
76
77         dwc3_core_soft_reset(dwc3_reg);
78
79         dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
80
81         reg = readl(&dwc3_reg->g_ctl);
82         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
83         reg &= ~DWC3_GCTL_DISSCRAMBLE;
84         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
85         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
86                 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
87                 break;
88         default:
89                 debug("No power optimization available\n");
90         }
91
92         /*
93          * WORKAROUND: DWC3 revisions <1.90a have a bug
94          * where the device can fail to connect at SuperSpeed
95          * and falls back to high-speed mode which causes
96          * the device to enter a Connect/Disconnect loop
97          */
98         if ((revision & DWC3_REVISION_MASK) < 0x190a)
99                 reg |= DWC3_GCTL_U2RSTECN;
100
101         writel(reg, &dwc3_reg->g_ctl);
102
103         return 0;
104 }
105
106 void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
107 {
108         setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
109                         GFLADJ_30MHZ(val));
110 }
111
112 #if CONFIG_IS_ENABLED(DM_USB)
113 static int xhci_dwc3_probe(struct udevice *dev)
114 {
115         struct xhci_hcor *hcor;
116         struct xhci_hccr *hccr;
117         struct dwc3 *dwc3_reg;
118         enum usb_dr_mode dr_mode;
119         struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
120         const char *phy;
121         u32 reg;
122         int ret;
123
124         hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
125         hcor = (struct xhci_hcor *)((uintptr_t)hccr +
126                         HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
127
128         ret = dwc3_setup_phy(dev, plat->usb_phys);
129         if (ret && (ret != -ENOTSUPP))
130                 return ret;
131
132         dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
133
134         dwc3_core_init(dwc3_reg);
135
136         /* Set dwc3 usb2 phy config */
137         reg = readl(&dwc3_reg->g_usb2phycfg[0]);
138
139         phy = dev_read_string(dev, "phy_type");
140         if (phy && strcmp(phy, "utmi_wide") == 0) {
141                 reg |= DWC3_GUSB2PHYCFG_PHYIF;
142                 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
143                 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
144         }
145
146         if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
147                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
148
149         if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
150                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
151
152         if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
153                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
154
155         writel(reg, &dwc3_reg->g_usb2phycfg[0]);
156
157         dr_mode = usb_get_dr_mode(dev->node);
158         if (dr_mode == USB_DR_MODE_UNKNOWN)
159                 /* by default set dual role mode to HOST */
160                 dr_mode = USB_DR_MODE_HOST;
161
162         dwc3_set_mode(dwc3_reg, dr_mode);
163
164         return xhci_register(dev, hccr, hcor);
165 }
166
167 static int xhci_dwc3_remove(struct udevice *dev)
168 {
169         struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
170
171         dwc3_shutdown_phy(dev, plat->usb_phys);
172
173         return xhci_deregister(dev);
174 }
175
176 static const struct udevice_id xhci_dwc3_ids[] = {
177         { .compatible = "snps,dwc3" },
178         { }
179 };
180
181 U_BOOT_DRIVER(xhci_dwc3) = {
182         .name = "xhci-dwc3",
183         .id = UCLASS_USB,
184         .of_match = xhci_dwc3_ids,
185         .probe = xhci_dwc3_probe,
186         .remove = xhci_dwc3_remove,
187         .ops = &xhci_usb_ops,
188         .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
189         .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
190         .flags = DM_FLAG_ALLOC_PRIV_DMA,
191 };
192 #endif