drivers/usb/host/ehci-marvell.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Marvell Semiconductor <www.marvell.com>
   5  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   6  */
   7
   8 #include <common.h>
   9 #include <log.h>
  10 #include <asm/io.h>
  11 #include <usb.h>
  12 #include <linux/delay.h>
  13 #include "ehci.h"
  14 #include <linux/mbus.h>
  15 #include <asm/arch/cpu.h>
  16 #include <dm.h>
  17
  18 #if defined(CONFIG_ARCH_KIRKWOOD)
  19 #include <asm/arch/soc.h>
  20 #elif defined(CONFIG_ARCH_ORION5X)
  21 #include <asm/arch/orion5x.h>
  22 #endif
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define USB_WINDOW_CTRL(i)      (0x320 + ((i) << 4))
  27 #define USB_WINDOW_BASE(i)      (0x324 + ((i) << 4))
  28 #define USB_TARGET_DRAM         0x0
  29
  30 #define USB2_SBUSCFG_OFF        0x90
  31
  32 #define USB_SBUSCFG_BAWR_OFF    0x6
  33 #define USB_SBUSCFG_BARD_OFF    0x3
  34 #define USB_SBUSCFG_AHBBRST_OFF 0x0
  35
  36 #define USB_SBUSCFG_BAWR_ALIGN_64B      0x4
  37 #define USB_SBUSCFG_BARD_ALIGN_64B      0x4
  38 #define USB_SBUSCFG_AHBBRST_INCR16      0x7
  39
  40 /*
  41  * USB 2.0 Bridge Address Decoding registers setup
  42  */
  43 #if CONFIG_IS_ENABLED(DM_USB)
  44
  45 struct ehci_mvebu_priv {
  46         struct ehci_ctrl ehci;
  47         fdt_addr_t hcd_base;
  48 };
  49
  50 /*
  51  * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
  52  * to the common mvebu archticture including the mbus setup, this
  53  * will be the only function needed to configure the access windows
  54  */
  55 static void usb_brg_adrdec_setup(void *base)
  56 {
  57         const struct mbus_dram_target_info *dram;
  58         int i;
  59
  60         dram = mvebu_mbus_dram_info();
  61
  62         for (i = 0; i < 4; i++) {
  63                 writel(0, base + USB_WINDOW_CTRL(i));
  64                 writel(0, base + USB_WINDOW_BASE(i));
  65         }
  66
  67         for (i = 0; i < dram->num_cs; i++) {
  68                 const struct mbus_dram_window *cs = dram->cs + i;
  69
  70                 /* Write size, attributes and target id to control register */
  71                 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  72                        (dram->mbus_dram_target_id << 4) | 1,
  73                        base + USB_WINDOW_CTRL(i));
  74
  75                 /* Write base address to base register */
  76                 writel(cs->base, base + USB_WINDOW_BASE(i));
  77         }
  78 }
  79
  80 static void marvell_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
  81                                        uint32_t *status_reg, uint32_t *reg)
  82 {
  83         struct ehci_mvebu_priv *priv = ctrl->priv;
  84
  85         /*
  86          * Set default value for reg SBUSCFG, which is Control for the AMBA
  87          * system bus interface:
  88          * BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes
  89          * AHBBRST = 7     : Align AHB burst for packets larger than 64 bytes
  90          */
  91         writel((USB_SBUSCFG_BAWR_ALIGN_64B << USB_SBUSCFG_BAWR_OFF) |
  92                (USB_SBUSCFG_BARD_ALIGN_64B << USB_SBUSCFG_BARD_OFF) |
  93                (USB_SBUSCFG_AHBBRST_INCR16 << USB_SBUSCFG_AHBBRST_OFF),
  94                priv->hcd_base + USB2_SBUSCFG_OFF);
  95
  96         mdelay(50);
  97 }
  98
  99 static struct ehci_ops marvell_ehci_ops = {
 100         .powerup_fixup  = NULL,
 101 };
 102
 103 static int ehci_mvebu_probe(struct udevice *dev)
 104 {
 105         struct ehci_mvebu_priv *priv = dev_get_priv(dev);
 106         struct ehci_hccr *hccr;
 107         struct ehci_hcor *hcor;
 108
 109         /*
 110          * Get the base address for EHCI controller from the device node
 111          */
 112         priv->hcd_base = devfdt_get_addr(dev);
 113         if (priv->hcd_base == FDT_ADDR_T_NONE) {
 114                 debug("Can't get the EHCI register base address\n");
 115                 return -ENXIO;
 116         }
 117
 118         /*
 119          * For SoCs without hlock like Armada3700 we need to program the sbuscfg
 120          * reg to guarantee AHB master's burst will not overrun or underrun
 121          * the FIFO. Otherwise all USB2 write option will fail.
 122          * Also, the address decoder doesn't need to get setup with this
 123          * SoC, so don't call usb_brg_adrdec_setup().
 124          */
 125         if (device_is_compatible(dev, "marvell,armada3700-ehci"))
 126                 marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup;
 127         else
 128                 usb_brg_adrdec_setup((void *)priv->hcd_base);
 129
 130         hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
 131         hcor = (struct ehci_hcor *)
 132                 ((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 133
 134         debug("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n",
 135               (uintptr_t)hccr, (uintptr_t)hcor,
 136               (uintptr_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 137
 138         return ehci_register(dev, hccr, hcor, &marvell_ehci_ops, 0,
 139                              USB_INIT_HOST);
 140 }
 141
 142 static const struct udevice_id ehci_usb_ids[] = {
 143         { .compatible = "marvell,orion-ehci", },
 144         { .compatible = "marvell,armada3700-ehci", },
 145         { }
 146 };
 147
 148 U_BOOT_DRIVER(ehci_mvebu) = {
 149         .name   = "ehci_mvebu",
 150         .id     = UCLASS_USB,
 151         .of_match = ehci_usb_ids,
 152         .probe = ehci_mvebu_probe,
 153         .remove = ehci_deregister,
 154         .ops    = &ehci_usb_ops,
 155         .platdata_auto_alloc_size = sizeof(struct usb_platdata),
 156         .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv),
 157         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
 158 };
 159
 160 #else
 161 #define MVUSB_BASE(port)        MVUSB0_BASE
 162
 163 static void usb_brg_adrdec_setup(int index)
 164 {
 165         int i;
 166         u32 size, base, attrib;
 167
 168         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 169
 170                 /* Enable DRAM bank */
 171                 switch (i) {
 172                 case 0:
 173                         attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
 174                         break;
 175                 case 1:
 176                         attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
 177                         break;
 178                 case 2:
 179                         attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
 180                         break;
 181                 case 3:
 182                         attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
 183                         break;
 184                 default:
 185                         /* invalide bank, disable access */
 186                         attrib = 0;
 187                         break;
 188                 }
 189
 190                 size = gd->bd->bi_dram[i].size;
 191                 base = gd->bd->bi_dram[i].start;
 192                 if ((size) && (attrib))
 193                         writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
 194                                                    attrib, MVCPU_WIN_ENABLE),
 195                                 MVUSB0_BASE + USB_WINDOW_CTRL(i));
 196                 else
 197                         writel(MVCPU_WIN_DISABLE,
 198                                MVUSB0_BASE + USB_WINDOW_CTRL(i));
 199
 200                 writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
 201         }
 202 }
 203
 204 /*
 205  * Create the appropriate control structures to manage
 206  * a new EHCI host controller.
 207  */
 208 int ehci_hcd_init(int index, enum usb_init_type init,
 209                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 210 {
 211         usb_brg_adrdec_setup(index);
 212
 213         *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
 214         *hcor = (struct ehci_hcor *)((uint32_t) *hccr
 215                         + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 216
 217         debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
 218                 (uint32_t)*hccr, (uint32_t)*hcor,
 219                 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 220
 221         return 0;
 222 }
 223
 224 /*
 225  * Destroy the appropriate control structures corresponding
 226  * the the EHCI host controller.
 227  */
 228 int ehci_hcd_stop(int index)
 229 {
 230         return 0;
 231 }
 232
 233 #endif /* CONFIG_IS_ENABLED(DM_USB) */