drivers/usb/host/dwc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   4  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <generic-phy.h>
  13 #include <malloc.h>
  14 #include <memalign.h>
  15 #include <phys2bus.h>
  16 #include <usb.h>
  17 #include <usbroothubdes.h>
  18 #include <wait_bit.h>
  19 #include <asm/io.h>
  20 #include <dm/device_compat.h>
  21 #include <power/regulator.h>
  22 #include <reset.h>
  23
  24 #include "dwc2.h"
  25
  26 /* Use only HC channel 0. */
  27 #define DWC2_HC_CHANNEL                 0
  28
  29 #define DWC2_STATUS_BUF_SIZE            64
  30 #define DWC2_DATA_BUF_SIZE              (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
  31
  32 #define MAX_DEVICE                      16
  33 #define MAX_ENDPOINT                    16
  34
  35 struct dwc2_priv {
  36 #if CONFIG_IS_ENABLED(DM_USB)
  37         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  38         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  39 #ifdef CONFIG_DM_REGULATOR
  40         struct udevice *vbus_supply;
  41 #endif
  42         struct phy phy;
  43         struct clk_bulk clks;
  44 #else
  45         uint8_t *aligned_buffer;
  46         uint8_t *status_buffer;
  47 #endif
  48         u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  49         u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  50         struct dwc2_core_regs *regs;
  51         int root_hub_devnum;
  52         bool ext_vbus;
  53         /*
  54          * The hnp/srp capability must be disabled if the platform
  55          * does't support hnp/srp. Otherwise the force mode can't work.
  56          */
  57         bool hnp_srp_disable;
  58         bool oc_disable;
  59
  60         struct reset_ctl_bulk   resets;
  61 };
  62
  63 #if !CONFIG_IS_ENABLED(DM_USB)
  64 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  65 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  66                 ARCH_DMA_MINALIGN);
  67 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  68                 ARCH_DMA_MINALIGN);
  69
  70 static struct dwc2_priv local;
  71 #endif
  72
  73 /*
  74  * DWC2 IP interface
  75  */
  76
  77 /*
  78  * Initializes the FSLSPClkSel field of the HCFG register
  79  * depending on the PHY type.
  80  */
  81 static void init_fslspclksel(struct dwc2_core_regs *regs)
  82 {
  83         uint32_t phyclk;
  84
  85 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  86         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  87 #else
  88         /* High speed PHY running at full speed or high speed */
  89         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  90 #endif
  91
  92 #ifdef CONFIG_DWC2_ULPI_FS_LS
  93         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  94         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  95                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  96         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  97                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  98
  99         if (hval == 2 && fval == 1)
 100                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
 101 #endif
 102
 103         clrsetbits_le32(&regs->host_regs.hcfg,
 104                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 105                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 106 }
 107
 108 /*
 109  * Flush a Tx FIFO.
 110  *
 111  * @param regs Programming view of DWC_otg controller.
 112  * @param num Tx FIFO to flush.
 113  */
 114 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 115 {
 116         int ret;
 117
 118         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 119                &regs->grstctl);
 120         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
 121                                 false, 1000, false);
 122         if (ret)
 123                 dev_info(dev, "%s: Timeout!\n", __func__);
 124
 125         /* Wait for 3 PHY Clocks */
 126         udelay(1);
 127 }
 128
 129 /*
 130  * Flush Rx FIFO.
 131  *
 132  * @param regs Programming view of DWC_otg controller.
 133  */
 134 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 135 {
 136         int ret;
 137
 138         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 139         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
 140                                 false, 1000, false);
 141         if (ret)
 142                 dev_info(dev, "%s: Timeout!\n", __func__);
 143
 144         /* Wait for 3 PHY Clocks */
 145         udelay(1);
 146 }
 147
 148 /*
 149  * Do core a soft reset of the core.  Be careful with this because it
 150  * resets all the internal state machines of the core.
 151  */
 152 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 153 {
 154         int ret;
 155
 156         /* Wait for AHB master IDLE state. */
 157         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
 158                                 true, 1000, false);
 159         if (ret)
 160                 dev_info(dev, "%s: Timeout!\n", __func__);
 161
 162         /* Core Soft Reset */
 163         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 164         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
 165                                 false, 1000, false);
 166         if (ret)
 167                 dev_info(dev, "%s: Timeout!\n", __func__);
 168
 169         /*
 170          * Wait for core to come out of reset.
 171          * NOTE: This long sleep is _very_ important, otherwise the core will
 172          *       not stay in host mode after a connector ID change!
 173          */
 174         mdelay(100);
 175 }
 176
 177 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
 178 static int dwc_vbus_supply_init(struct udevice *dev)
 179 {
 180         struct dwc2_priv *priv = dev_get_priv(dev);
 181         int ret;
 182
 183         ret = device_get_supply_regulator(dev, "vbus-supply",
 184                                           &priv->vbus_supply);
 185         if (ret) {
 186                 debug("%s: No vbus supply\n", dev->name);
 187                 return 0;
 188         }
 189
 190         ret = regulator_set_enable(priv->vbus_supply, true);
 191         if (ret) {
 192                 dev_err(dev, "Error enabling vbus supply\n");
 193                 return ret;
 194         }
 195
 196         return 0;
 197 }
 198
 199 static int dwc_vbus_supply_exit(struct udevice *dev)
 200 {
 201         struct dwc2_priv *priv = dev_get_priv(dev);
 202         int ret;
 203
 204         if (priv->vbus_supply) {
 205                 ret = regulator_set_enable(priv->vbus_supply, false);
 206                 if (ret) {
 207                         dev_err(dev, "Error disabling vbus supply\n");
 208                         return ret;
 209                 }
 210         }
 211
 212         return 0;
 213 }
 214 #else
 215 static int dwc_vbus_supply_init(struct udevice *dev)
 216 {
 217         return 0;
 218 }
 219
 220 #if CONFIG_IS_ENABLED(DM_USB)
 221 static int dwc_vbus_supply_exit(struct udevice *dev)
 222 {
 223         return 0;
 224 }
 225 #endif
 226 #endif
 227
 228 /*
 229  * This function initializes the DWC_otg controller registers for
 230  * host mode.
 231  *
 232  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 233  * request queues. Host channels are reset to ensure that they are ready for
 234  * performing transfers.
 235  *
 236  * @param dev USB Device (NULL if driver model is not being used)
 237  * @param regs Programming view of DWC_otg controller
 238  *
 239  */
 240 static void dwc_otg_core_host_init(struct udevice *dev,
 241                                    struct dwc2_core_regs *regs)
 242 {
 243         uint32_t nptxfifosize = 0;
 244         uint32_t ptxfifosize = 0;
 245         uint32_t hprt0 = 0;
 246         int i, ret, num_channels;
 247
 248         /* Restart the Phy Clock */
 249         writel(0, &regs->pcgcctl);
 250
 251         /* Initialize Host Configuration Register */
 252         init_fslspclksel(regs);
 253 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 254         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 255 #endif
 256
 257         /* Configure data FIFO sizes */
 258 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 259         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 260                 /* Rx FIFO */
 261                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 262
 263                 /* Non-periodic Tx FIFO */
 264                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 265                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 266                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 267                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 268                 writel(nptxfifosize, &regs->gnptxfsiz);
 269
 270                 /* Periodic Tx FIFO */
 271                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 272                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 273                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 274                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 275                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 276                 writel(ptxfifosize, &regs->hptxfsiz);
 277         }
 278 #endif
 279
 280         /* Clear Host Set HNP Enable in the OTG Control Register */
 281         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 282
 283         /* Make sure the FIFOs are flushed. */
 284         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 285         dwc_otg_flush_rx_fifo(regs);
 286
 287         /* Flush out any leftover queued requests. */
 288         num_channels = readl(&regs->ghwcfg2);
 289         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 290         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 291         num_channels += 1;
 292
 293         for (i = 0; i < num_channels; i++)
 294                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 295                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 296                                 DWC2_HCCHAR_CHDIS);
 297
 298         /* Halt all channels to put them into a known state. */
 299         for (i = 0; i < num_channels; i++) {
 300                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 301                                 DWC2_HCCHAR_EPDIR,
 302                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 303                 ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
 304                                         DWC2_HCCHAR_CHEN, false, 1000, false);
 305                 if (ret)
 306                         dev_info("%s: Timeout!\n", __func__);
 307         }
 308
 309         /* Turn on the vbus power. */
 310         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 311                 hprt0 = readl(&regs->hprt0);
 312                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 313                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 314                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 315                         hprt0 |= DWC2_HPRT0_PRTPWR;
 316                         writel(hprt0, &regs->hprt0);
 317                 }
 318         }
 319
 320         if (dev)
 321                 dwc_vbus_supply_init(dev);
 322 }
 323
 324 /*
 325  * This function initializes the DWC_otg controller registers and
 326  * prepares the core for device mode or host mode operation.
 327  *
 328  * @param regs Programming view of the DWC_otg controller
 329  */
 330 static void dwc_otg_core_init(struct dwc2_priv *priv)
 331 {
 332         struct dwc2_core_regs *regs = priv->regs;
 333         uint32_t ahbcfg = 0;
 334         uint32_t usbcfg = 0;
 335         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 336
 337         /* Common Initialization */
 338         usbcfg = readl(&regs->gusbcfg);
 339
 340         /* Program the ULPI External VBUS bit if needed */
 341         if (priv->ext_vbus) {
 342                 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 343                 if (!priv->oc_disable) {
 344                         usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
 345                                   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
 346                 }
 347         } else {
 348                 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 349         }
 350
 351         /* Set external TS Dline pulsing */
 352 #ifdef CONFIG_DWC2_TS_DLINE
 353         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 354 #else
 355         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 356 #endif
 357         writel(usbcfg, &regs->gusbcfg);
 358
 359         /* Reset the Controller */
 360         dwc_otg_core_reset(regs);
 361
 362         /*
 363          * This programming sequence needs to happen in FS mode before
 364          * any other programming occurs
 365          */
 366 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 367         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 368         /* If FS mode with FS PHY */
 369         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 370
 371         /* Reset after a PHY select */
 372         dwc_otg_core_reset(regs);
 373
 374         /*
 375          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 376          * Also do this on HNP Dev/Host mode switches (done in dev_init
 377          * and host_init).
 378          */
 379         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 380                 init_fslspclksel(regs);
 381
 382 #ifdef CONFIG_DWC2_I2C_ENABLE
 383         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 384         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 385
 386         /* Program GI2CCTL.I2CEn */
 387         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 388                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 389                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 390         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 391 #endif
 392
 393 #else
 394         /* High speed PHY. */
 395
 396         /*
 397          * HS PHY parameters. These parameters are preserved during
 398          * soft reset so only program the first time. Do a soft reset
 399          * immediately after setting phyif.
 400          */
 401         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 402         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 403
 404         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 405 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 406                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 407 #else
 408                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 409 #endif
 410         } else {        /* UTMI+ interface */
 411 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
 412                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 413 #endif
 414         }
 415
 416         writel(usbcfg, &regs->gusbcfg);
 417
 418         /* Reset after setting the PHY parameters */
 419         dwc_otg_core_reset(regs);
 420 #endif
 421
 422         usbcfg = readl(&regs->gusbcfg);
 423         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 424 #ifdef CONFIG_DWC2_ULPI_FS_LS
 425         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 426         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 427                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 428         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 429                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 430         if (hval == 2 && fval == 1) {
 431                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 432                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 433         }
 434 #endif
 435         if (priv->hnp_srp_disable)
 436                 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
 437
 438         writel(usbcfg, &regs->gusbcfg);
 439
 440         /* Program the GAHBCFG Register. */
 441         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 442         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 443                 break;
 444         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 445                 while (brst_sz > 1) {
 446                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 447                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 448                         brst_sz >>= 1;
 449                 }
 450
 451 #ifdef CONFIG_DWC2_DMA_ENABLE
 452                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 453 #endif
 454                 break;
 455
 456         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 457                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 458 #ifdef CONFIG_DWC2_DMA_ENABLE
 459                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 460 #endif
 461                 break;
 462         }
 463
 464         writel(ahbcfg, &regs->gahbcfg);
 465
 466         /* Program the capabilities in GUSBCFG Register */
 467         usbcfg = 0;
 468
 469         if (!priv->hnp_srp_disable)
 470                 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
 471 #ifdef CONFIG_DWC2_IC_USB_CAP
 472         usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
 473 #endif
 474
 475         setbits_le32(&regs->gusbcfg, usbcfg);
 476 }
 477
 478 /*
 479  * Prepares a host channel for transferring packets to/from a specific
 480  * endpoint. The HCCHARn register is set up with the characteristics specified
 481  * in _hc. Host channel interrupts that may need to be serviced while this
 482  * transfer is in progress are enabled.
 483  *
 484  * @param regs Programming view of DWC_otg controller
 485  * @param hc Information needed to initialize the host channel
 486  */
 487 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 488                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 489                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 490 {
 491         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 492         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 493                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 494                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 495                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 496                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 497
 498         if (dev->speed == USB_SPEED_LOW)
 499                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 500
 501         /*
 502          * Program the HCCHARn register with the endpoint characteristics
 503          * for the current transfer.
 504          */
 505         writel(hcchar, &hc_regs->hcchar);
 506
 507         /* Program the HCSPLIT register, default to no SPLIT */
 508         writel(0, &hc_regs->hcsplt);
 509 }
 510
 511 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
 512                                   uint8_t hub_devnum, uint8_t hub_port)
 513 {
 514         uint32_t hcsplt = 0;
 515
 516         hcsplt = DWC2_HCSPLT_SPLTENA;
 517         hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
 518         hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
 519
 520         /* Program the HCSPLIT register for SPLITs */
 521         writel(hcsplt, &hc_regs->hcsplt);
 522 }
 523
 524 /*
 525  * DWC2 to USB API interface
 526  */
 527 /* Direction: In ; Request: Status */
 528 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 529                                            struct usb_device *dev, void *buffer,
 530                                            int txlen, struct devrequest *cmd)
 531 {
 532         uint32_t hprt0 = 0;
 533         uint32_t port_status = 0;
 534         uint32_t port_change = 0;
 535         int len = 0;
 536         int stat = 0;
 537
 538         switch (cmd->requesttype & ~USB_DIR_IN) {
 539         case 0:
 540                 *(uint16_t *)buffer = cpu_to_le16(1);
 541                 len = 2;
 542                 break;
 543         case USB_RECIP_INTERFACE:
 544         case USB_RECIP_ENDPOINT:
 545                 *(uint16_t *)buffer = cpu_to_le16(0);
 546                 len = 2;
 547                 break;
 548         case USB_TYPE_CLASS:
 549                 *(uint32_t *)buffer = cpu_to_le32(0);
 550                 len = 4;
 551                 break;
 552         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 553                 hprt0 = readl(&regs->hprt0);
 554                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 555                         port_status |= USB_PORT_STAT_CONNECTION;
 556                 if (hprt0 & DWC2_HPRT0_PRTENA)
 557                         port_status |= USB_PORT_STAT_ENABLE;
 558                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 559                         port_status |= USB_PORT_STAT_SUSPEND;
 560                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 561                         port_status |= USB_PORT_STAT_OVERCURRENT;
 562                 if (hprt0 & DWC2_HPRT0_PRTRST)
 563                         port_status |= USB_PORT_STAT_RESET;
 564                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 565                         port_status |= USB_PORT_STAT_POWER;
 566
 567                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 568                         port_status |= USB_PORT_STAT_LOW_SPEED;
 569                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 570                          DWC2_HPRT0_PRTSPD_HIGH)
 571                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 572
 573                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 574                         port_change |= USB_PORT_STAT_C_ENABLE;
 575                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 576                         port_change |= USB_PORT_STAT_C_CONNECTION;
 577                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 578                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 579
 580                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 581                                         (port_change << 16));
 582                 len = 4;
 583                 break;
 584         default:
 585                 puts("unsupported root hub command\n");
 586                 stat = USB_ST_STALLED;
 587         }
 588
 589         dev->act_len = min(len, txlen);
 590         dev->status = stat;
 591
 592         return stat;
 593 }
 594
 595 /* Direction: In ; Request: Descriptor */
 596 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 597                                                void *buffer, int txlen,
 598                                                struct devrequest *cmd)
 599 {
 600         unsigned char data[32];
 601         uint32_t dsc;
 602         int len = 0;
 603         int stat = 0;
 604         uint16_t wValue = cpu_to_le16(cmd->value);
 605         uint16_t wLength = cpu_to_le16(cmd->length);
 606
 607         switch (cmd->requesttype & ~USB_DIR_IN) {
 608         case 0:
 609                 switch (wValue & 0xff00) {
 610                 case 0x0100:    /* device descriptor */
 611                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 612                         memcpy(buffer, root_hub_dev_des, len);
 613                         break;
 614                 case 0x0200:    /* configuration descriptor */
 615                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 616                         memcpy(buffer, root_hub_config_des, len);
 617                         break;
 618                 case 0x0300:    /* string descriptors */
 619                         switch (wValue & 0xff) {
 620                         case 0x00:
 621                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 622                                            (int)wLength);
 623                                 memcpy(buffer, root_hub_str_index0, len);
 624                                 break;
 625                         case 0x01:
 626                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 627                                            (int)wLength);
 628                                 memcpy(buffer, root_hub_str_index1, len);
 629                                 break;
 630                         }
 631                         break;
 632                 default:
 633                         stat = USB_ST_STALLED;
 634                 }
 635                 break;
 636
 637         case USB_TYPE_CLASS:
 638                 /* Root port config, set 1 port and nothing else. */
 639                 dsc = 0x00000001;
 640
 641                 data[0] = 9;            /* min length; */
 642                 data[1] = 0x29;
 643                 data[2] = dsc & RH_A_NDP;
 644                 data[3] = 0;
 645                 if (dsc & RH_A_PSM)
 646                         data[3] |= 0x1;
 647                 if (dsc & RH_A_NOCP)
 648                         data[3] |= 0x10;
 649                 else if (dsc & RH_A_OCPM)
 650                         data[3] |= 0x8;
 651
 652                 /* corresponds to data[4-7] */
 653                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 654                 data[7] = dsc & RH_B_DR;
 655                 if (data[2] < 7) {
 656                         data[8] = 0xff;
 657                 } else {
 658                         data[0] += 2;
 659                         data[8] = (dsc & RH_B_DR) >> 8;
 660                         data[9] = 0xff;
 661                         data[10] = data[9];
 662                 }
 663
 664                 len = min3(txlen, (int)data[0], (int)wLength);
 665                 memcpy(buffer, data, len);
 666                 break;
 667         default:
 668                 puts("unsupported root hub command\n");
 669                 stat = USB_ST_STALLED;
 670         }
 671
 672         dev->act_len = min(len, txlen);
 673         dev->status = stat;
 674
 675         return stat;
 676 }
 677
 678 /* Direction: In ; Request: Configuration */
 679 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 680                                                   void *buffer, int txlen,
 681                                                   struct devrequest *cmd)
 682 {
 683         int len = 0;
 684         int stat = 0;
 685
 686         switch (cmd->requesttype & ~USB_DIR_IN) {
 687         case 0:
 688                 *(uint8_t *)buffer = 0x01;
 689                 len = 1;
 690                 break;
 691         default:
 692                 puts("unsupported root hub command\n");
 693                 stat = USB_ST_STALLED;
 694         }
 695
 696         dev->act_len = min(len, txlen);
 697         dev->status = stat;
 698
 699         return stat;
 700 }
 701
 702 /* Direction: In */
 703 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 704                                     struct usb_device *dev, void *buffer,
 705                                     int txlen, struct devrequest *cmd)
 706 {
 707         switch (cmd->request) {
 708         case USB_REQ_GET_STATUS:
 709                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 710                                                        txlen, cmd);
 711         case USB_REQ_GET_DESCRIPTOR:
 712                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 713                                                            txlen, cmd);
 714         case USB_REQ_GET_CONFIGURATION:
 715                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 716                                                               txlen, cmd);
 717         default:
 718                 puts("unsupported root hub command\n");
 719                 return USB_ST_STALLED;
 720         }
 721 }
 722
 723 /* Direction: Out */
 724 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 725                                      struct usb_device *dev,
 726                                      void *buffer, int txlen,
 727                                      struct devrequest *cmd)
 728 {
 729         struct dwc2_core_regs *regs = priv->regs;
 730         int len = 0;
 731         int stat = 0;
 732         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 733         uint16_t wValue = cpu_to_le16(cmd->value);
 734
 735         switch (bmrtype_breq & ~USB_DIR_IN) {
 736         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 737         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 738                 break;
 739
 740         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 741                 switch (wValue) {
 742                 case USB_PORT_FEAT_C_CONNECTION:
 743                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 744                         break;
 745                 }
 746                 break;
 747
 748         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 749                 switch (wValue) {
 750                 case USB_PORT_FEAT_SUSPEND:
 751                         break;
 752
 753                 case USB_PORT_FEAT_RESET:
 754                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 755                                         DWC2_HPRT0_PRTCONNDET |
 756                                         DWC2_HPRT0_PRTENCHNG |
 757                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 758                                         DWC2_HPRT0_PRTRST);
 759                         mdelay(50);
 760                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 761                         break;
 762
 763                 case USB_PORT_FEAT_POWER:
 764                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 765                                         DWC2_HPRT0_PRTCONNDET |
 766                                         DWC2_HPRT0_PRTENCHNG |
 767                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 768                                         DWC2_HPRT0_PRTRST);
 769                         break;
 770
 771                 case USB_PORT_FEAT_ENABLE:
 772                         break;
 773                 }
 774                 break;
 775         case (USB_REQ_SET_ADDRESS << 8):
 776                 priv->root_hub_devnum = wValue;
 777                 break;
 778         case (USB_REQ_SET_CONFIGURATION << 8):
 779                 break;
 780         default:
 781                 puts("unsupported root hub command\n");
 782                 stat = USB_ST_STALLED;
 783         }
 784
 785         len = min(len, txlen);
 786
 787         dev->act_len = len;
 788         dev->status = stat;
 789
 790         return stat;
 791 }
 792
 793 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 794                                  unsigned long pipe, void *buffer, int txlen,
 795                                  struct devrequest *cmd)
 796 {
 797         int stat = 0;
 798
 799         if (usb_pipeint(pipe)) {
 800                 puts("Root-Hub submit IRQ: NOT implemented\n");
 801                 return 0;
 802         }
 803
 804         if (cmd->requesttype & USB_DIR_IN)
 805                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 806         else
 807                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 808
 809         mdelay(1);
 810
 811         return stat;
 812 }
 813
 814 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
 815 {
 816         int ret;
 817         uint32_t hcint, hctsiz;
 818
 819         ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
 820                                 2000, false);
 821         if (ret)
 822                 return ret;
 823
 824         hcint = readl(&hc_regs->hcint);
 825         hctsiz = readl(&hc_regs->hctsiz);
 826         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 827                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 828         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 829
 830         debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
 831               *toggle);
 832
 833         if (hcint & DWC2_HCINT_XFERCOMP)
 834                 return 0;
 835
 836         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 837                 return -EAGAIN;
 838
 839         debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 840         return -EINVAL;
 841 }
 842
 843 static int dwc2_eptype[] = {
 844         DWC2_HCCHAR_EPTYPE_ISOC,
 845         DWC2_HCCHAR_EPTYPE_INTR,
 846         DWC2_HCCHAR_EPTYPE_CONTROL,
 847         DWC2_HCCHAR_EPTYPE_BULK,
 848 };
 849
 850 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
 851                           u8 *pid, int in, void *buffer, int num_packets,
 852                           int xfer_len, int *actual_len, int odd_frame)
 853 {
 854         int ret = 0;
 855         uint32_t sub;
 856
 857         debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 858               *pid, xfer_len, num_packets);
 859
 860         writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 861                (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 862                (*pid << DWC2_HCTSIZ_PID_OFFSET),
 863                &hc_regs->hctsiz);
 864
 865         if (xfer_len) {
 866                 if (in) {
 867                         invalidate_dcache_range(
 868                                         (uintptr_t)aligned_buffer,
 869                                         (uintptr_t)aligned_buffer +
 870                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 871                 } else {
 872                         memcpy(aligned_buffer, buffer, xfer_len);
 873                         flush_dcache_range(
 874                                         (uintptr_t)aligned_buffer,
 875                                         (uintptr_t)aligned_buffer +
 876                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 877                 }
 878         }
 879
 880         writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
 881
 882         /* Clear old interrupt conditions for this host channel. */
 883         writel(0x3fff, &hc_regs->hcint);
 884
 885         /* Set host channel enable after all other setup is complete. */
 886         clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 887                         DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
 888                         DWC2_HCCHAR_ODDFRM,
 889                         (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 890                         (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
 891                         DWC2_HCCHAR_CHEN);
 892
 893         ret = wait_for_chhltd(hc_regs, &sub, pid);
 894         if (ret < 0)
 895                 return ret;
 896
 897         if (in) {
 898                 xfer_len -= sub;
 899
 900                 invalidate_dcache_range((unsigned long)aligned_buffer,
 901                                         (unsigned long)aligned_buffer +
 902                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 903
 904                 memcpy(buffer, aligned_buffer, xfer_len);
 905         }
 906         *actual_len = xfer_len;
 907
 908         return ret;
 909 }
 910
 911 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 912               unsigned long pipe, u8 *pid, int in, void *buffer, int len)
 913 {
 914         struct dwc2_core_regs *regs = priv->regs;
 915         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 916         struct dwc2_host_regs *host_regs = &regs->host_regs;
 917         int devnum = usb_pipedevice(pipe);
 918         int ep = usb_pipeendpoint(pipe);
 919         int max = usb_maxpacket(dev, pipe);
 920         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 921         int done = 0;
 922         int ret = 0;
 923         int do_split = 0;
 924         int complete_split = 0;
 925         uint32_t xfer_len;
 926         uint32_t num_packets;
 927         int stop_transfer = 0;
 928         uint32_t max_xfer_len;
 929         int ssplit_frame_num = 0;
 930
 931         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 932               in, len);
 933
 934         max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
 935         if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 936                 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
 937         if (max_xfer_len > DWC2_DATA_BUF_SIZE)
 938                 max_xfer_len = DWC2_DATA_BUF_SIZE;
 939
 940         /* Make sure that max_xfer_len is a multiple of max packet size. */
 941         num_packets = max_xfer_len / max;
 942         max_xfer_len = num_packets * max;
 943
 944         /* Initialize channel */
 945         dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 946                         eptype, max);
 947
 948         /* Check if the target is a FS/LS device behind a HS hub */
 949         if (dev->speed != USB_SPEED_HIGH) {
 950                 uint8_t hub_addr;
 951                 uint8_t hub_port;
 952                 uint32_t hprt0 = readl(&regs->hprt0);
 953                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 954                      DWC2_HPRT0_PRTSPD_HIGH) {
 955                         usb_find_usb2_hub_address_port(dev, &hub_addr,
 956                                                        &hub_port);
 957                         dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
 958
 959                         do_split = 1;
 960                         num_packets = 1;
 961                         max_xfer_len = max;
 962                 }
 963         }
 964
 965         do {
 966                 int actual_len = 0;
 967                 uint32_t hcint;
 968                 int odd_frame = 0;
 969                 xfer_len = len - done;
 970
 971                 if (xfer_len > max_xfer_len)
 972                         xfer_len = max_xfer_len;
 973                 else if (xfer_len > max)
 974                         num_packets = (xfer_len + max - 1) / max;
 975                 else
 976                         num_packets = 1;
 977
 978                 if (complete_split)
 979                         setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 980                 else if (do_split)
 981                         clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 982
 983                 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
 984                         int uframe_num = readl(&host_regs->hfnum);
 985                         if (!(uframe_num & 0x1))
 986                                 odd_frame = 1;
 987                 }
 988
 989                 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 990                                      in, (char *)buffer + done, num_packets,
 991                                      xfer_len, &actual_len, odd_frame);
 992
 993                 hcint = readl(&hc_regs->hcint);
 994                 if (complete_split) {
 995                         stop_transfer = 0;
 996                         if (hcint & DWC2_HCINT_NYET) {
 997                                 ret = 0;
 998                                 int frame_num = DWC2_HFNUM_MAX_FRNUM &
 999                                                 readl(&host_regs->hfnum);
1000                                 if (((frame_num - ssplit_frame_num) &
1001                                     DWC2_HFNUM_MAX_FRNUM) > 4)
1002                                         ret = -EAGAIN;
1003                         } else
1004                                 complete_split = 0;
1005                 } else if (do_split) {
1006                         if (hcint & DWC2_HCINT_ACK) {
1007                                 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1008                                                    readl(&host_regs->hfnum);
1009                                 ret = 0;
1010                                 complete_split = 1;
1011                         }
1012                 }
1013
1014                 if (ret)
1015                         break;
1016
1017                 if (actual_len < xfer_len)
1018                         stop_transfer = 1;
1019
1020                 done += actual_len;
1021
1022         /* Transactions are done when when either all data is transferred or
1023          * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1024          * is executed.
1025          */
1026         } while (((done < len) && !stop_transfer) || complete_split);
1027
1028         writel(0, &hc_regs->hcintmsk);
1029         writel(0xFFFFFFFF, &hc_regs->hcint);
1030
1031         dev->status = 0;
1032         dev->act_len = done;
1033
1034         return ret;
1035 }
1036
1037 /* U-Boot USB transmission interface */
1038 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1039                      unsigned long pipe, void *buffer, int len)
1040 {
1041         int devnum = usb_pipedevice(pipe);
1042         int ep = usb_pipeendpoint(pipe);
1043         u8* pid;
1044
1045         if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1046                 dev->status = 0;
1047                 return -EINVAL;
1048         }
1049
1050         if (usb_pipein(pipe))
1051                 pid = &priv->in_data_toggle[devnum][ep];
1052         else
1053                 pid = &priv->out_data_toggle[devnum][ep];
1054
1055         return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1056 }
1057
1058 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1059                                unsigned long pipe, void *buffer, int len,
1060                                struct devrequest *setup)
1061 {
1062         int devnum = usb_pipedevice(pipe);
1063         int ret, act_len;
1064         u8 pid;
1065         /* For CONTROL endpoint pid should start with DATA1 */
1066         int status_direction;
1067
1068         if (devnum == priv->root_hub_devnum) {
1069                 dev->status = 0;
1070                 dev->speed = USB_SPEED_HIGH;
1071                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1072                                              setup);
1073         }
1074
1075         /* SETUP stage */
1076         pid = DWC2_HC_PID_SETUP;
1077         do {
1078                 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1079         } while (ret == -EAGAIN);
1080         if (ret)
1081                 return ret;
1082
1083         /* DATA stage */
1084         act_len = 0;
1085         if (buffer) {
1086                 pid = DWC2_HC_PID_DATA1;
1087                 do {
1088                         ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1089                                         buffer, len);
1090                         act_len += dev->act_len;
1091                         buffer += dev->act_len;
1092                         len -= dev->act_len;
1093                 } while (ret == -EAGAIN);
1094                 if (ret)
1095                         return ret;
1096                 status_direction = usb_pipeout(pipe);
1097         } else {
1098                 /* No-data CONTROL always ends with an IN transaction */
1099                 status_direction = 1;
1100         }
1101
1102         /* STATUS stage */
1103         pid = DWC2_HC_PID_DATA1;
1104         do {
1105                 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1106                                 priv->status_buffer, 0);
1107         } while (ret == -EAGAIN);
1108         if (ret)
1109                 return ret;
1110
1111         dev->act_len = act_len;
1112
1113         return 0;
1114 }
1115
1116 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1117                     unsigned long pipe, void *buffer, int len, int interval,
1118                     bool nonblock)
1119 {
1120         unsigned long timeout;
1121         int ret;
1122
1123         /* FIXME: what is interval? */
1124
1125         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1126         for (;;) {
1127                 if (get_timer(0) > timeout) {
1128                         dev_err(dev, "Timeout poll on interrupt endpoint\n");
1129                         return -ETIMEDOUT;
1130                 }
1131                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1132                 if ((ret != -EAGAIN) || nonblock)
1133                         return ret;
1134         }
1135 }
1136
1137 static int dwc2_reset(struct udevice *dev)
1138 {
1139         int ret;
1140         struct dwc2_priv *priv = dev_get_priv(dev);
1141
1142         ret = reset_get_bulk(dev, &priv->resets);
1143         if (ret) {
1144                 dev_warn(dev, "Can't get reset: %d\n", ret);
1145                 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1146                  * DT property is not present.
1147                  */
1148                 if (ret == -ENOENT || ret == -ENOTSUPP)
1149                         return 0;
1150                 else
1151                         return ret;
1152         }
1153
1154         /* force reset to clear all IP register */
1155         reset_assert_bulk(&priv->resets);
1156         ret = reset_deassert_bulk(&priv->resets);
1157         if (ret) {
1158                 reset_release_bulk(&priv->resets);
1159                 dev_err(dev, "Failed to reset: %d\n", ret);
1160                 return ret;
1161         }
1162
1163         return 0;
1164 }
1165
1166 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1167 {
1168         struct dwc2_core_regs *regs = priv->regs;
1169         uint32_t snpsid;
1170         int i, j;
1171         int ret;
1172
1173         ret = dwc2_reset(dev);
1174         if (ret)
1175                 return ret;
1176
1177         snpsid = readl(&regs->gsnpsid);
1178         dev_info(dev, "Core Release: %x.%03x\n",
1179                  snpsid >> 12 & 0xf, snpsid & 0xfff);
1180
1181         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1182             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1183                 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1184                          snpsid);
1185                 return -ENODEV;
1186         }
1187
1188 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1189         priv->ext_vbus = 1;
1190 #else
1191         priv->ext_vbus = 0;
1192 #endif
1193
1194         dwc_otg_core_init(priv);
1195         dwc_otg_core_host_init(dev, regs);
1196
1197         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1198                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1199                         DWC2_HPRT0_PRTOVRCURRCHNG,
1200                         DWC2_HPRT0_PRTRST);
1201         mdelay(50);
1202         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1203                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1204                      DWC2_HPRT0_PRTRST);
1205
1206         for (i = 0; i < MAX_DEVICE; i++) {
1207                 for (j = 0; j < MAX_ENDPOINT; j++) {
1208                         priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1209                         priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1210                 }
1211         }
1212
1213         /*
1214          * Add a 1 second delay here. This gives the host controller
1215          * a bit time before the comminucation with the USB devices
1216          * is started (the bus is scanned) and  fixes the USB detection
1217          * problems with some problematic USB keys.
1218          */
1219         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1220                 mdelay(1000);
1221
1222         printf("USB DWC2\n");
1223
1224         return 0;
1225 }
1226
1227 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1228 {
1229         /* Put everything in reset. */
1230         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1231                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1232                         DWC2_HPRT0_PRTOVRCURRCHNG,
1233                         DWC2_HPRT0_PRTRST);
1234 }
1235
1236 #if !CONFIG_IS_ENABLED(DM_USB)
1237 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1238                        int len, struct devrequest *setup)
1239 {
1240         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1241 }
1242
1243 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1244                     int len)
1245 {
1246         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1247 }
1248
1249 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1250                    int len, int interval, bool nonblock)
1251 {
1252         return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1253                                nonblock);
1254 }
1255
1256 /* U-Boot USB control interface */
1257 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1258 {
1259         struct dwc2_priv *priv = &local;
1260
1261         memset(priv, '\0', sizeof(*priv));
1262         priv->root_hub_devnum = 0;
1263         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1264         priv->aligned_buffer = aligned_buffer_addr;
1265         priv->status_buffer = status_buffer_addr;
1266
1267         /* board-dependant init */
1268         if (board_usb_init(index, USB_INIT_HOST))
1269                 return -1;
1270
1271         return dwc2_init_common(NULL, priv);
1272 }
1273
1274 int usb_lowlevel_stop(int index)
1275 {
1276         dwc2_uninit_common(local.regs);
1277
1278         return 0;
1279 }
1280 #endif
1281
1282 #if CONFIG_IS_ENABLED(DM_USB)
1283 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1284                                    unsigned long pipe, void *buffer, int length,
1285                                    struct devrequest *setup)
1286 {
1287         struct dwc2_priv *priv = dev_get_priv(dev);
1288
1289         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1290               dev->name, udev, udev->dev->name, udev->portnr);
1291
1292         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1293 }
1294
1295 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1296                                 unsigned long pipe, void *buffer, int length)
1297 {
1298         struct dwc2_priv *priv = dev_get_priv(dev);
1299
1300         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1301
1302         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1303 }
1304
1305 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1306                                unsigned long pipe, void *buffer, int length,
1307                                int interval, bool nonblock)
1308 {
1309         struct dwc2_priv *priv = dev_get_priv(dev);
1310
1311         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1312
1313         return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1314                                nonblock);
1315 }
1316
1317 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1318 {
1319         struct dwc2_priv *priv = dev_get_priv(dev);
1320         fdt_addr_t addr;
1321
1322         addr = dev_read_addr(dev);
1323         if (addr == FDT_ADDR_T_NONE)
1324                 return -EINVAL;
1325         priv->regs = (struct dwc2_core_regs *)addr;
1326
1327         priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1328         priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1329
1330         return 0;
1331 }
1332
1333 static int dwc2_setup_phy(struct udevice *dev)
1334 {
1335         struct dwc2_priv *priv = dev_get_priv(dev);
1336         int ret;
1337
1338         ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1339         if (ret) {
1340                 if (ret == -ENOENT)
1341                         return 0; /* no PHY, nothing to do */
1342                 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1343                 return ret;
1344         }
1345
1346         ret = generic_phy_init(&priv->phy);
1347         if (ret) {
1348                 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1349                 return ret;
1350         }
1351
1352         ret = generic_phy_power_on(&priv->phy);
1353         if (ret) {
1354                 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1355                 generic_phy_exit(&priv->phy);
1356                 return ret;
1357         }
1358
1359         return 0;
1360 }
1361
1362 static int dwc2_shutdown_phy(struct udevice *dev)
1363 {
1364         struct dwc2_priv *priv = dev_get_priv(dev);
1365         int ret;
1366
1367         /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1368         if (!generic_phy_valid(&priv->phy))
1369                 return 0; /* no PHY, nothing to do */
1370
1371         ret = generic_phy_power_off(&priv->phy);
1372         if (ret) {
1373                 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1374                 return ret;
1375         }
1376
1377         ret = generic_phy_exit(&priv->phy);
1378         if (ret) {
1379                 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1380                 return ret;
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int dwc2_clk_init(struct udevice *dev)
1387 {
1388         struct dwc2_priv *priv = dev_get_priv(dev);
1389         int ret;
1390
1391         ret = clk_get_bulk(dev, &priv->clks);
1392         if (ret == -ENOSYS || ret == -ENOENT)
1393                 return 0;
1394         if (ret)
1395                 return ret;
1396
1397         ret = clk_enable_bulk(&priv->clks);
1398         if (ret) {
1399                 clk_release_bulk(&priv->clks);
1400                 return ret;
1401         }
1402
1403         return 0;
1404 }
1405
1406 static int dwc2_usb_probe(struct udevice *dev)
1407 {
1408         struct dwc2_priv *priv = dev_get_priv(dev);
1409         struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1410         int ret;
1411
1412         bus_priv->desc_before_addr = true;
1413
1414         ret = dwc2_clk_init(dev);
1415         if (ret)
1416                 return ret;
1417
1418         ret = dwc2_setup_phy(dev);
1419         if (ret)
1420                 return ret;
1421
1422         return dwc2_init_common(dev, priv);
1423 }
1424
1425 static int dwc2_usb_remove(struct udevice *dev)
1426 {
1427         struct dwc2_priv *priv = dev_get_priv(dev);
1428         int ret;
1429
1430         ret = dwc_vbus_supply_exit(dev);
1431         if (ret)
1432                 return ret;
1433
1434         ret = dwc2_shutdown_phy(dev);
1435         if (ret) {
1436                 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1437                 return ret;
1438         }
1439
1440         dwc2_uninit_common(priv->regs);
1441
1442         reset_release_bulk(&priv->resets);
1443         clk_disable_bulk(&priv->clks);
1444         clk_release_bulk(&priv->clks);
1445
1446         return 0;
1447 }
1448
1449 struct dm_usb_ops dwc2_usb_ops = {
1450         .control = dwc2_submit_control_msg,
1451         .bulk = dwc2_submit_bulk_msg,
1452         .interrupt = dwc2_submit_int_msg,
1453 };
1454
1455 static const struct udevice_id dwc2_usb_ids[] = {
1456         { .compatible = "brcm,bcm2835-usb" },
1457         { .compatible = "brcm,bcm2708-usb" },
1458         { .compatible = "snps,dwc2" },
1459         { }
1460 };
1461
1462 U_BOOT_DRIVER(usb_dwc2) = {
1463         .name   = "dwc2_usb",
1464         .id     = UCLASS_USB,
1465         .of_match = dwc2_usb_ids,
1466         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1467         .probe  = dwc2_usb_probe,
1468         .remove = dwc2_usb_remove,
1469         .ops    = &dwc2_usb_ops,
1470         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1471         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1472 };
1473 #endif