drivers/usb/host/dwc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   4  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <usb.h>
  12 #include <malloc.h>
  13 #include <memalign.h>
  14 #include <phys2bus.h>
  15 #include <usbroothubdes.h>
  16 #include <wait_bit.h>
  17 #include <asm/io.h>
  18 #include <power/regulator.h>
  19 #include <reset.h>
  20
  21 #include "dwc2.h"
  22
  23 /* Use only HC channel 0. */
  24 #define DWC2_HC_CHANNEL                 0
  25
  26 #define DWC2_STATUS_BUF_SIZE            64
  27 #define DWC2_DATA_BUF_SIZE              (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
  28
  29 #define MAX_DEVICE                      16
  30 #define MAX_ENDPOINT                    16
  31
  32 struct dwc2_priv {
  33 #if CONFIG_IS_ENABLED(DM_USB)
  34         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  35         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  36 #ifdef CONFIG_DM_REGULATOR
  37         struct udevice *vbus_supply;
  38 #endif
  39 #else
  40         uint8_t *aligned_buffer;
  41         uint8_t *status_buffer;
  42 #endif
  43         u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  44         u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  45         struct dwc2_core_regs *regs;
  46         int root_hub_devnum;
  47         bool ext_vbus;
  48         /*
  49          * The hnp/srp capability must be disabled if the platform
  50          * does't support hnp/srp. Otherwise the force mode can't work.
  51          */
  52         bool hnp_srp_disable;
  53         bool oc_disable;
  54
  55         struct reset_ctl_bulk   resets;
  56 };
  57
  58 #if !CONFIG_IS_ENABLED(DM_USB)
  59 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  60 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  61                 ARCH_DMA_MINALIGN);
  62 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  63                 ARCH_DMA_MINALIGN);
  64
  65 static struct dwc2_priv local;
  66 #endif
  67
  68 /*
  69  * DWC2 IP interface
  70  */
  71
  72 /*
  73  * Initializes the FSLSPClkSel field of the HCFG register
  74  * depending on the PHY type.
  75  */
  76 static void init_fslspclksel(struct dwc2_core_regs *regs)
  77 {
  78         uint32_t phyclk;
  79
  80 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  81         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  82 #else
  83         /* High speed PHY running at full speed or high speed */
  84         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  85 #endif
  86
  87 #ifdef CONFIG_DWC2_ULPI_FS_LS
  88         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  89         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  90                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  91         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  92                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  93
  94         if (hval == 2 && fval == 1)
  95                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  96 #endif
  97
  98         clrsetbits_le32(&regs->host_regs.hcfg,
  99                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 100                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 101 }
 102
 103 /*
 104  * Flush a Tx FIFO.
 105  *
 106  * @param regs Programming view of DWC_otg controller.
 107  * @param num Tx FIFO to flush.
 108  */
 109 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 110 {
 111         int ret;
 112
 113         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 114                &regs->grstctl);
 115         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
 116                                 false, 1000, false);
 117         if (ret)
 118                 dev_info(dev, "%s: Timeout!\n", __func__);
 119
 120         /* Wait for 3 PHY Clocks */
 121         udelay(1);
 122 }
 123
 124 /*
 125  * Flush Rx FIFO.
 126  *
 127  * @param regs Programming view of DWC_otg controller.
 128  */
 129 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 130 {
 131         int ret;
 132
 133         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 134         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
 135                                 false, 1000, false);
 136         if (ret)
 137                 dev_info(dev, "%s: Timeout!\n", __func__);
 138
 139         /* Wait for 3 PHY Clocks */
 140         udelay(1);
 141 }
 142
 143 /*
 144  * Do core a soft reset of the core.  Be careful with this because it
 145  * resets all the internal state machines of the core.
 146  */
 147 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 148 {
 149         int ret;
 150
 151         /* Wait for AHB master IDLE state. */
 152         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
 153                                 true, 1000, false);
 154         if (ret)
 155                 dev_info(dev, "%s: Timeout!\n", __func__);
 156
 157         /* Core Soft Reset */
 158         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 159         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
 160                                 false, 1000, false);
 161         if (ret)
 162                 dev_info(dev, "%s: Timeout!\n", __func__);
 163
 164         /*
 165          * Wait for core to come out of reset.
 166          * NOTE: This long sleep is _very_ important, otherwise the core will
 167          *       not stay in host mode after a connector ID change!
 168          */
 169         mdelay(100);
 170 }
 171
 172 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
 173 static int dwc_vbus_supply_init(struct udevice *dev)
 174 {
 175         struct dwc2_priv *priv = dev_get_priv(dev);
 176         int ret;
 177
 178         ret = device_get_supply_regulator(dev, "vbus-supply",
 179                                           &priv->vbus_supply);
 180         if (ret) {
 181                 debug("%s: No vbus supply\n", dev->name);
 182                 return 0;
 183         }
 184
 185         ret = regulator_set_enable(priv->vbus_supply, true);
 186         if (ret) {
 187                 dev_err(dev, "Error enabling vbus supply\n");
 188                 return ret;
 189         }
 190
 191         return 0;
 192 }
 193
 194 static int dwc_vbus_supply_exit(struct udevice *dev)
 195 {
 196         struct dwc2_priv *priv = dev_get_priv(dev);
 197         int ret;
 198
 199         if (priv->vbus_supply) {
 200                 ret = regulator_set_enable(priv->vbus_supply, false);
 201                 if (ret) {
 202                         dev_err(dev, "Error disabling vbus supply\n");
 203                         return ret;
 204                 }
 205         }
 206
 207         return 0;
 208 }
 209 #else
 210 static int dwc_vbus_supply_init(struct udevice *dev)
 211 {
 212         return 0;
 213 }
 214
 215 #if CONFIG_IS_ENABLED(DM_USB)
 216 static int dwc_vbus_supply_exit(struct udevice *dev)
 217 {
 218         return 0;
 219 }
 220 #endif
 221 #endif
 222
 223 /*
 224  * This function initializes the DWC_otg controller registers for
 225  * host mode.
 226  *
 227  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 228  * request queues. Host channels are reset to ensure that they are ready for
 229  * performing transfers.
 230  *
 231  * @param dev USB Device (NULL if driver model is not being used)
 232  * @param regs Programming view of DWC_otg controller
 233  *
 234  */
 235 static void dwc_otg_core_host_init(struct udevice *dev,
 236                                    struct dwc2_core_regs *regs)
 237 {
 238         uint32_t nptxfifosize = 0;
 239         uint32_t ptxfifosize = 0;
 240         uint32_t hprt0 = 0;
 241         int i, ret, num_channels;
 242
 243         /* Restart the Phy Clock */
 244         writel(0, &regs->pcgcctl);
 245
 246         /* Initialize Host Configuration Register */
 247         init_fslspclksel(regs);
 248 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 249         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 250 #endif
 251
 252         /* Configure data FIFO sizes */
 253 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 254         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 255                 /* Rx FIFO */
 256                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 257
 258                 /* Non-periodic Tx FIFO */
 259                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 260                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 261                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 262                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 263                 writel(nptxfifosize, &regs->gnptxfsiz);
 264
 265                 /* Periodic Tx FIFO */
 266                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 267                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 268                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 269                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 270                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 271                 writel(ptxfifosize, &regs->hptxfsiz);
 272         }
 273 #endif
 274
 275         /* Clear Host Set HNP Enable in the OTG Control Register */
 276         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 277
 278         /* Make sure the FIFOs are flushed. */
 279         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 280         dwc_otg_flush_rx_fifo(regs);
 281
 282         /* Flush out any leftover queued requests. */
 283         num_channels = readl(&regs->ghwcfg2);
 284         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 285         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 286         num_channels += 1;
 287
 288         for (i = 0; i < num_channels; i++)
 289                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 290                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 291                                 DWC2_HCCHAR_CHDIS);
 292
 293         /* Halt all channels to put them into a known state. */
 294         for (i = 0; i < num_channels; i++) {
 295                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 296                                 DWC2_HCCHAR_EPDIR,
 297                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 298                 ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
 299                                         DWC2_HCCHAR_CHEN, false, 1000, false);
 300                 if (ret)
 301                         dev_info("%s: Timeout!\n", __func__);
 302         }
 303
 304         /* Turn on the vbus power. */
 305         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 306                 hprt0 = readl(&regs->hprt0);
 307                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 308                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 309                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 310                         hprt0 |= DWC2_HPRT0_PRTPWR;
 311                         writel(hprt0, &regs->hprt0);
 312                 }
 313         }
 314
 315         if (dev)
 316                 dwc_vbus_supply_init(dev);
 317 }
 318
 319 /*
 320  * This function initializes the DWC_otg controller registers and
 321  * prepares the core for device mode or host mode operation.
 322  *
 323  * @param regs Programming view of the DWC_otg controller
 324  */
 325 static void dwc_otg_core_init(struct dwc2_priv *priv)
 326 {
 327         struct dwc2_core_regs *regs = priv->regs;
 328         uint32_t ahbcfg = 0;
 329         uint32_t usbcfg = 0;
 330         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 331
 332         /* Common Initialization */
 333         usbcfg = readl(&regs->gusbcfg);
 334
 335         /* Program the ULPI External VBUS bit if needed */
 336         if (priv->ext_vbus) {
 337                 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 338                 if (!priv->oc_disable) {
 339                         usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
 340                                   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
 341                 }
 342         } else {
 343                 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 344         }
 345
 346         /* Set external TS Dline pulsing */
 347 #ifdef CONFIG_DWC2_TS_DLINE
 348         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 349 #else
 350         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 351 #endif
 352         writel(usbcfg, &regs->gusbcfg);
 353
 354         /* Reset the Controller */
 355         dwc_otg_core_reset(regs);
 356
 357         /*
 358          * This programming sequence needs to happen in FS mode before
 359          * any other programming occurs
 360          */
 361 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 362         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 363         /* If FS mode with FS PHY */
 364         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 365
 366         /* Reset after a PHY select */
 367         dwc_otg_core_reset(regs);
 368
 369         /*
 370          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 371          * Also do this on HNP Dev/Host mode switches (done in dev_init
 372          * and host_init).
 373          */
 374         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 375                 init_fslspclksel(regs);
 376
 377 #ifdef CONFIG_DWC2_I2C_ENABLE
 378         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 379         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 380
 381         /* Program GI2CCTL.I2CEn */
 382         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 383                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 384                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 385         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 386 #endif
 387
 388 #else
 389         /* High speed PHY. */
 390
 391         /*
 392          * HS PHY parameters. These parameters are preserved during
 393          * soft reset so only program the first time. Do a soft reset
 394          * immediately after setting phyif.
 395          */
 396         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 397         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 398
 399         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 400 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 401                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 402 #else
 403                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 404 #endif
 405         } else {        /* UTMI+ interface */
 406 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
 407                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 408 #endif
 409         }
 410
 411         writel(usbcfg, &regs->gusbcfg);
 412
 413         /* Reset after setting the PHY parameters */
 414         dwc_otg_core_reset(regs);
 415 #endif
 416
 417         usbcfg = readl(&regs->gusbcfg);
 418         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 419 #ifdef CONFIG_DWC2_ULPI_FS_LS
 420         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 421         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 422                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 423         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 424                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 425         if (hval == 2 && fval == 1) {
 426                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 427                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 428         }
 429 #endif
 430         if (priv->hnp_srp_disable)
 431                 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
 432
 433         writel(usbcfg, &regs->gusbcfg);
 434
 435         /* Program the GAHBCFG Register. */
 436         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 437         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 438                 break;
 439         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 440                 while (brst_sz > 1) {
 441                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 442                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 443                         brst_sz >>= 1;
 444                 }
 445
 446 #ifdef CONFIG_DWC2_DMA_ENABLE
 447                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 448 #endif
 449                 break;
 450
 451         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 452                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 453 #ifdef CONFIG_DWC2_DMA_ENABLE
 454                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 455 #endif
 456                 break;
 457         }
 458
 459         writel(ahbcfg, &regs->gahbcfg);
 460
 461         /* Program the capabilities in GUSBCFG Register */
 462         usbcfg = 0;
 463
 464         if (!priv->hnp_srp_disable)
 465                 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
 466 #ifdef CONFIG_DWC2_IC_USB_CAP
 467         usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
 468 #endif
 469
 470         setbits_le32(&regs->gusbcfg, usbcfg);
 471 }
 472
 473 /*
 474  * Prepares a host channel for transferring packets to/from a specific
 475  * endpoint. The HCCHARn register is set up with the characteristics specified
 476  * in _hc. Host channel interrupts that may need to be serviced while this
 477  * transfer is in progress are enabled.
 478  *
 479  * @param regs Programming view of DWC_otg controller
 480  * @param hc Information needed to initialize the host channel
 481  */
 482 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 483                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 484                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 485 {
 486         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 487         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 488                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 489                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 490                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 491                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 492
 493         if (dev->speed == USB_SPEED_LOW)
 494                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 495
 496         /*
 497          * Program the HCCHARn register with the endpoint characteristics
 498          * for the current transfer.
 499          */
 500         writel(hcchar, &hc_regs->hcchar);
 501
 502         /* Program the HCSPLIT register, default to no SPLIT */
 503         writel(0, &hc_regs->hcsplt);
 504 }
 505
 506 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
 507                                   uint8_t hub_devnum, uint8_t hub_port)
 508 {
 509         uint32_t hcsplt = 0;
 510
 511         hcsplt = DWC2_HCSPLT_SPLTENA;
 512         hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
 513         hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
 514
 515         /* Program the HCSPLIT register for SPLITs */
 516         writel(hcsplt, &hc_regs->hcsplt);
 517 }
 518
 519 /*
 520  * DWC2 to USB API interface
 521  */
 522 /* Direction: In ; Request: Status */
 523 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 524                                            struct usb_device *dev, void *buffer,
 525                                            int txlen, struct devrequest *cmd)
 526 {
 527         uint32_t hprt0 = 0;
 528         uint32_t port_status = 0;
 529         uint32_t port_change = 0;
 530         int len = 0;
 531         int stat = 0;
 532
 533         switch (cmd->requesttype & ~USB_DIR_IN) {
 534         case 0:
 535                 *(uint16_t *)buffer = cpu_to_le16(1);
 536                 len = 2;
 537                 break;
 538         case USB_RECIP_INTERFACE:
 539         case USB_RECIP_ENDPOINT:
 540                 *(uint16_t *)buffer = cpu_to_le16(0);
 541                 len = 2;
 542                 break;
 543         case USB_TYPE_CLASS:
 544                 *(uint32_t *)buffer = cpu_to_le32(0);
 545                 len = 4;
 546                 break;
 547         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 548                 hprt0 = readl(&regs->hprt0);
 549                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 550                         port_status |= USB_PORT_STAT_CONNECTION;
 551                 if (hprt0 & DWC2_HPRT0_PRTENA)
 552                         port_status |= USB_PORT_STAT_ENABLE;
 553                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 554                         port_status |= USB_PORT_STAT_SUSPEND;
 555                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 556                         port_status |= USB_PORT_STAT_OVERCURRENT;
 557                 if (hprt0 & DWC2_HPRT0_PRTRST)
 558                         port_status |= USB_PORT_STAT_RESET;
 559                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 560                         port_status |= USB_PORT_STAT_POWER;
 561
 562                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 563                         port_status |= USB_PORT_STAT_LOW_SPEED;
 564                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 565                          DWC2_HPRT0_PRTSPD_HIGH)
 566                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 567
 568                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 569                         port_change |= USB_PORT_STAT_C_ENABLE;
 570                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 571                         port_change |= USB_PORT_STAT_C_CONNECTION;
 572                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 573                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 574
 575                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 576                                         (port_change << 16));
 577                 len = 4;
 578                 break;
 579         default:
 580                 puts("unsupported root hub command\n");
 581                 stat = USB_ST_STALLED;
 582         }
 583
 584         dev->act_len = min(len, txlen);
 585         dev->status = stat;
 586
 587         return stat;
 588 }
 589
 590 /* Direction: In ; Request: Descriptor */
 591 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 592                                                void *buffer, int txlen,
 593                                                struct devrequest *cmd)
 594 {
 595         unsigned char data[32];
 596         uint32_t dsc;
 597         int len = 0;
 598         int stat = 0;
 599         uint16_t wValue = cpu_to_le16(cmd->value);
 600         uint16_t wLength = cpu_to_le16(cmd->length);
 601
 602         switch (cmd->requesttype & ~USB_DIR_IN) {
 603         case 0:
 604                 switch (wValue & 0xff00) {
 605                 case 0x0100:    /* device descriptor */
 606                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 607                         memcpy(buffer, root_hub_dev_des, len);
 608                         break;
 609                 case 0x0200:    /* configuration descriptor */
 610                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 611                         memcpy(buffer, root_hub_config_des, len);
 612                         break;
 613                 case 0x0300:    /* string descriptors */
 614                         switch (wValue & 0xff) {
 615                         case 0x00:
 616                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 617                                            (int)wLength);
 618                                 memcpy(buffer, root_hub_str_index0, len);
 619                                 break;
 620                         case 0x01:
 621                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 622                                            (int)wLength);
 623                                 memcpy(buffer, root_hub_str_index1, len);
 624                                 break;
 625                         }
 626                         break;
 627                 default:
 628                         stat = USB_ST_STALLED;
 629                 }
 630                 break;
 631
 632         case USB_TYPE_CLASS:
 633                 /* Root port config, set 1 port and nothing else. */
 634                 dsc = 0x00000001;
 635
 636                 data[0] = 9;            /* min length; */
 637                 data[1] = 0x29;
 638                 data[2] = dsc & RH_A_NDP;
 639                 data[3] = 0;
 640                 if (dsc & RH_A_PSM)
 641                         data[3] |= 0x1;
 642                 if (dsc & RH_A_NOCP)
 643                         data[3] |= 0x10;
 644                 else if (dsc & RH_A_OCPM)
 645                         data[3] |= 0x8;
 646
 647                 /* corresponds to data[4-7] */
 648                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 649                 data[7] = dsc & RH_B_DR;
 650                 if (data[2] < 7) {
 651                         data[8] = 0xff;
 652                 } else {
 653                         data[0] += 2;
 654                         data[8] = (dsc & RH_B_DR) >> 8;
 655                         data[9] = 0xff;
 656                         data[10] = data[9];
 657                 }
 658
 659                 len = min3(txlen, (int)data[0], (int)wLength);
 660                 memcpy(buffer, data, len);
 661                 break;
 662         default:
 663                 puts("unsupported root hub command\n");
 664                 stat = USB_ST_STALLED;
 665         }
 666
 667         dev->act_len = min(len, txlen);
 668         dev->status = stat;
 669
 670         return stat;
 671 }
 672
 673 /* Direction: In ; Request: Configuration */
 674 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 675                                                   void *buffer, int txlen,
 676                                                   struct devrequest *cmd)
 677 {
 678         int len = 0;
 679         int stat = 0;
 680
 681         switch (cmd->requesttype & ~USB_DIR_IN) {
 682         case 0:
 683                 *(uint8_t *)buffer = 0x01;
 684                 len = 1;
 685                 break;
 686         default:
 687                 puts("unsupported root hub command\n");
 688                 stat = USB_ST_STALLED;
 689         }
 690
 691         dev->act_len = min(len, txlen);
 692         dev->status = stat;
 693
 694         return stat;
 695 }
 696
 697 /* Direction: In */
 698 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 699                                     struct usb_device *dev, void *buffer,
 700                                     int txlen, struct devrequest *cmd)
 701 {
 702         switch (cmd->request) {
 703         case USB_REQ_GET_STATUS:
 704                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 705                                                        txlen, cmd);
 706         case USB_REQ_GET_DESCRIPTOR:
 707                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 708                                                            txlen, cmd);
 709         case USB_REQ_GET_CONFIGURATION:
 710                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 711                                                               txlen, cmd);
 712         default:
 713                 puts("unsupported root hub command\n");
 714                 return USB_ST_STALLED;
 715         }
 716 }
 717
 718 /* Direction: Out */
 719 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 720                                      struct usb_device *dev,
 721                                      void *buffer, int txlen,
 722                                      struct devrequest *cmd)
 723 {
 724         struct dwc2_core_regs *regs = priv->regs;
 725         int len = 0;
 726         int stat = 0;
 727         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 728         uint16_t wValue = cpu_to_le16(cmd->value);
 729
 730         switch (bmrtype_breq & ~USB_DIR_IN) {
 731         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 732         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 733                 break;
 734
 735         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 736                 switch (wValue) {
 737                 case USB_PORT_FEAT_C_CONNECTION:
 738                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 739                         break;
 740                 }
 741                 break;
 742
 743         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 744                 switch (wValue) {
 745                 case USB_PORT_FEAT_SUSPEND:
 746                         break;
 747
 748                 case USB_PORT_FEAT_RESET:
 749                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 750                                         DWC2_HPRT0_PRTCONNDET |
 751                                         DWC2_HPRT0_PRTENCHNG |
 752                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 753                                         DWC2_HPRT0_PRTRST);
 754                         mdelay(50);
 755                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 756                         break;
 757
 758                 case USB_PORT_FEAT_POWER:
 759                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 760                                         DWC2_HPRT0_PRTCONNDET |
 761                                         DWC2_HPRT0_PRTENCHNG |
 762                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 763                                         DWC2_HPRT0_PRTRST);
 764                         break;
 765
 766                 case USB_PORT_FEAT_ENABLE:
 767                         break;
 768                 }
 769                 break;
 770         case (USB_REQ_SET_ADDRESS << 8):
 771                 priv->root_hub_devnum = wValue;
 772                 break;
 773         case (USB_REQ_SET_CONFIGURATION << 8):
 774                 break;
 775         default:
 776                 puts("unsupported root hub command\n");
 777                 stat = USB_ST_STALLED;
 778         }
 779
 780         len = min(len, txlen);
 781
 782         dev->act_len = len;
 783         dev->status = stat;
 784
 785         return stat;
 786 }
 787
 788 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 789                                  unsigned long pipe, void *buffer, int txlen,
 790                                  struct devrequest *cmd)
 791 {
 792         int stat = 0;
 793
 794         if (usb_pipeint(pipe)) {
 795                 puts("Root-Hub submit IRQ: NOT implemented\n");
 796                 return 0;
 797         }
 798
 799         if (cmd->requesttype & USB_DIR_IN)
 800                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 801         else
 802                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 803
 804         mdelay(1);
 805
 806         return stat;
 807 }
 808
 809 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
 810 {
 811         int ret;
 812         uint32_t hcint, hctsiz;
 813
 814         ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
 815                                 2000, false);
 816         if (ret)
 817                 return ret;
 818
 819         hcint = readl(&hc_regs->hcint);
 820         hctsiz = readl(&hc_regs->hctsiz);
 821         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 822                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 823         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 824
 825         debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
 826               *toggle);
 827
 828         if (hcint & DWC2_HCINT_XFERCOMP)
 829                 return 0;
 830
 831         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 832                 return -EAGAIN;
 833
 834         debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 835         return -EINVAL;
 836 }
 837
 838 static int dwc2_eptype[] = {
 839         DWC2_HCCHAR_EPTYPE_ISOC,
 840         DWC2_HCCHAR_EPTYPE_INTR,
 841         DWC2_HCCHAR_EPTYPE_CONTROL,
 842         DWC2_HCCHAR_EPTYPE_BULK,
 843 };
 844
 845 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
 846                           u8 *pid, int in, void *buffer, int num_packets,
 847                           int xfer_len, int *actual_len, int odd_frame)
 848 {
 849         int ret = 0;
 850         uint32_t sub;
 851
 852         debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 853               *pid, xfer_len, num_packets);
 854
 855         writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 856                (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 857                (*pid << DWC2_HCTSIZ_PID_OFFSET),
 858                &hc_regs->hctsiz);
 859
 860         if (xfer_len) {
 861                 if (in) {
 862                         invalidate_dcache_range(
 863                                         (uintptr_t)aligned_buffer,
 864                                         (uintptr_t)aligned_buffer +
 865                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 866                 } else {
 867                         memcpy(aligned_buffer, buffer, xfer_len);
 868                         flush_dcache_range(
 869                                         (uintptr_t)aligned_buffer,
 870                                         (uintptr_t)aligned_buffer +
 871                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 872                 }
 873         }
 874
 875         writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
 876
 877         /* Clear old interrupt conditions for this host channel. */
 878         writel(0x3fff, &hc_regs->hcint);
 879
 880         /* Set host channel enable after all other setup is complete. */
 881         clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 882                         DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
 883                         DWC2_HCCHAR_ODDFRM,
 884                         (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 885                         (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
 886                         DWC2_HCCHAR_CHEN);
 887
 888         ret = wait_for_chhltd(hc_regs, &sub, pid);
 889         if (ret < 0)
 890                 return ret;
 891
 892         if (in) {
 893                 xfer_len -= sub;
 894
 895                 invalidate_dcache_range((unsigned long)aligned_buffer,
 896                                         (unsigned long)aligned_buffer +
 897                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 898
 899                 memcpy(buffer, aligned_buffer, xfer_len);
 900         }
 901         *actual_len = xfer_len;
 902
 903         return ret;
 904 }
 905
 906 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 907               unsigned long pipe, u8 *pid, int in, void *buffer, int len)
 908 {
 909         struct dwc2_core_regs *regs = priv->regs;
 910         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 911         struct dwc2_host_regs *host_regs = &regs->host_regs;
 912         int devnum = usb_pipedevice(pipe);
 913         int ep = usb_pipeendpoint(pipe);
 914         int max = usb_maxpacket(dev, pipe);
 915         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 916         int done = 0;
 917         int ret = 0;
 918         int do_split = 0;
 919         int complete_split = 0;
 920         uint32_t xfer_len;
 921         uint32_t num_packets;
 922         int stop_transfer = 0;
 923         uint32_t max_xfer_len;
 924         int ssplit_frame_num = 0;
 925
 926         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 927               in, len);
 928
 929         max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
 930         if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 931                 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
 932         if (max_xfer_len > DWC2_DATA_BUF_SIZE)
 933                 max_xfer_len = DWC2_DATA_BUF_SIZE;
 934
 935         /* Make sure that max_xfer_len is a multiple of max packet size. */
 936         num_packets = max_xfer_len / max;
 937         max_xfer_len = num_packets * max;
 938
 939         /* Initialize channel */
 940         dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 941                         eptype, max);
 942
 943         /* Check if the target is a FS/LS device behind a HS hub */
 944         if (dev->speed != USB_SPEED_HIGH) {
 945                 uint8_t hub_addr;
 946                 uint8_t hub_port;
 947                 uint32_t hprt0 = readl(&regs->hprt0);
 948                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 949                      DWC2_HPRT0_PRTSPD_HIGH) {
 950                         usb_find_usb2_hub_address_port(dev, &hub_addr,
 951                                                        &hub_port);
 952                         dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
 953
 954                         do_split = 1;
 955                         num_packets = 1;
 956                         max_xfer_len = max;
 957                 }
 958         }
 959
 960         do {
 961                 int actual_len = 0;
 962                 uint32_t hcint;
 963                 int odd_frame = 0;
 964                 xfer_len = len - done;
 965
 966                 if (xfer_len > max_xfer_len)
 967                         xfer_len = max_xfer_len;
 968                 else if (xfer_len > max)
 969                         num_packets = (xfer_len + max - 1) / max;
 970                 else
 971                         num_packets = 1;
 972
 973                 if (complete_split)
 974                         setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 975                 else if (do_split)
 976                         clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 977
 978                 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
 979                         int uframe_num = readl(&host_regs->hfnum);
 980                         if (!(uframe_num & 0x1))
 981                                 odd_frame = 1;
 982                 }
 983
 984                 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 985                                      in, (char *)buffer + done, num_packets,
 986                                      xfer_len, &actual_len, odd_frame);
 987
 988                 hcint = readl(&hc_regs->hcint);
 989                 if (complete_split) {
 990                         stop_transfer = 0;
 991                         if (hcint & DWC2_HCINT_NYET) {
 992                                 ret = 0;
 993                                 int frame_num = DWC2_HFNUM_MAX_FRNUM &
 994                                                 readl(&host_regs->hfnum);
 995                                 if (((frame_num - ssplit_frame_num) &
 996                                     DWC2_HFNUM_MAX_FRNUM) > 4)
 997                                         ret = -EAGAIN;
 998                         } else
 999                                 complete_split = 0;
1000                 } else if (do_split) {
1001                         if (hcint & DWC2_HCINT_ACK) {
1002                                 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1003                                                    readl(&host_regs->hfnum);
1004                                 ret = 0;
1005                                 complete_split = 1;
1006                         }
1007                 }
1008
1009                 if (ret)
1010                         break;
1011
1012                 if (actual_len < xfer_len)
1013                         stop_transfer = 1;
1014
1015                 done += actual_len;
1016
1017         /* Transactions are done when when either all data is transferred or
1018          * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1019          * is executed.
1020          */
1021         } while (((done < len) && !stop_transfer) || complete_split);
1022
1023         writel(0, &hc_regs->hcintmsk);
1024         writel(0xFFFFFFFF, &hc_regs->hcint);
1025
1026         dev->status = 0;
1027         dev->act_len = done;
1028
1029         return ret;
1030 }
1031
1032 /* U-Boot USB transmission interface */
1033 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1034                      unsigned long pipe, void *buffer, int len)
1035 {
1036         int devnum = usb_pipedevice(pipe);
1037         int ep = usb_pipeendpoint(pipe);
1038         u8* pid;
1039
1040         if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1041                 dev->status = 0;
1042                 return -EINVAL;
1043         }
1044
1045         if (usb_pipein(pipe))
1046                 pid = &priv->in_data_toggle[devnum][ep];
1047         else
1048                 pid = &priv->out_data_toggle[devnum][ep];
1049
1050         return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1051 }
1052
1053 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1054                                unsigned long pipe, void *buffer, int len,
1055                                struct devrequest *setup)
1056 {
1057         int devnum = usb_pipedevice(pipe);
1058         int ret, act_len;
1059         u8 pid;
1060         /* For CONTROL endpoint pid should start with DATA1 */
1061         int status_direction;
1062
1063         if (devnum == priv->root_hub_devnum) {
1064                 dev->status = 0;
1065                 dev->speed = USB_SPEED_HIGH;
1066                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1067                                              setup);
1068         }
1069
1070         /* SETUP stage */
1071         pid = DWC2_HC_PID_SETUP;
1072         do {
1073                 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1074         } while (ret == -EAGAIN);
1075         if (ret)
1076                 return ret;
1077
1078         /* DATA stage */
1079         act_len = 0;
1080         if (buffer) {
1081                 pid = DWC2_HC_PID_DATA1;
1082                 do {
1083                         ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1084                                         buffer, len);
1085                         act_len += dev->act_len;
1086                         buffer += dev->act_len;
1087                         len -= dev->act_len;
1088                 } while (ret == -EAGAIN);
1089                 if (ret)
1090                         return ret;
1091                 status_direction = usb_pipeout(pipe);
1092         } else {
1093                 /* No-data CONTROL always ends with an IN transaction */
1094                 status_direction = 1;
1095         }
1096
1097         /* STATUS stage */
1098         pid = DWC2_HC_PID_DATA1;
1099         do {
1100                 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1101                                 priv->status_buffer, 0);
1102         } while (ret == -EAGAIN);
1103         if (ret)
1104                 return ret;
1105
1106         dev->act_len = act_len;
1107
1108         return 0;
1109 }
1110
1111 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1112                     unsigned long pipe, void *buffer, int len, int interval,
1113                     bool nonblock)
1114 {
1115         unsigned long timeout;
1116         int ret;
1117
1118         /* FIXME: what is interval? */
1119
1120         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1121         for (;;) {
1122                 if (get_timer(0) > timeout) {
1123                         dev_err(dev, "Timeout poll on interrupt endpoint\n");
1124                         return -ETIMEDOUT;
1125                 }
1126                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1127                 if ((ret != -EAGAIN) || nonblock)
1128                         return ret;
1129         }
1130 }
1131
1132 static int dwc2_reset(struct udevice *dev)
1133 {
1134         int ret;
1135         struct dwc2_priv *priv = dev_get_priv(dev);
1136
1137         ret = reset_get_bulk(dev, &priv->resets);
1138         if (ret) {
1139                 dev_warn(dev, "Can't get reset: %d\n", ret);
1140                 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1141                  * DT property is not present.
1142                  */
1143                 if (ret == -ENOENT || ret == -ENOTSUPP)
1144                         return 0;
1145                 else
1146                         return ret;
1147         }
1148
1149         ret = reset_deassert_bulk(&priv->resets);
1150         if (ret) {
1151                 reset_release_bulk(&priv->resets);
1152                 dev_err(dev, "Failed to reset: %d\n", ret);
1153                 return ret;
1154         }
1155
1156         return 0;
1157 }
1158
1159 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1160 {
1161         struct dwc2_core_regs *regs = priv->regs;
1162         uint32_t snpsid;
1163         int i, j;
1164         int ret;
1165
1166         ret = dwc2_reset(dev);
1167         if (ret)
1168                 return ret;
1169
1170         snpsid = readl(&regs->gsnpsid);
1171         dev_info(dev, "Core Release: %x.%03x\n",
1172                  snpsid >> 12 & 0xf, snpsid & 0xfff);
1173
1174         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1175             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1176                 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1177                          snpsid);
1178                 return -ENODEV;
1179         }
1180
1181 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1182         priv->ext_vbus = 1;
1183 #else
1184         priv->ext_vbus = 0;
1185 #endif
1186
1187         dwc_otg_core_init(priv);
1188         dwc_otg_core_host_init(dev, regs);
1189
1190         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1191                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1192                         DWC2_HPRT0_PRTOVRCURRCHNG,
1193                         DWC2_HPRT0_PRTRST);
1194         mdelay(50);
1195         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1196                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1197                      DWC2_HPRT0_PRTRST);
1198
1199         for (i = 0; i < MAX_DEVICE; i++) {
1200                 for (j = 0; j < MAX_ENDPOINT; j++) {
1201                         priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1202                         priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1203                 }
1204         }
1205
1206         /*
1207          * Add a 1 second delay here. This gives the host controller
1208          * a bit time before the comminucation with the USB devices
1209          * is started (the bus is scanned) and  fixes the USB detection
1210          * problems with some problematic USB keys.
1211          */
1212         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1213                 mdelay(1000);
1214
1215         return 0;
1216 }
1217
1218 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1219 {
1220         /* Put everything in reset. */
1221         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1222                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1223                         DWC2_HPRT0_PRTOVRCURRCHNG,
1224                         DWC2_HPRT0_PRTRST);
1225 }
1226
1227 #if !CONFIG_IS_ENABLED(DM_USB)
1228 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1229                        int len, struct devrequest *setup)
1230 {
1231         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1232 }
1233
1234 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1235                     int len)
1236 {
1237         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1238 }
1239
1240 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1241                    int len, int interval, bool nonblock)
1242 {
1243         return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1244                                nonblock);
1245 }
1246
1247 /* U-Boot USB control interface */
1248 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1249 {
1250         struct dwc2_priv *priv = &local;
1251
1252         memset(priv, '\0', sizeof(*priv));
1253         priv->root_hub_devnum = 0;
1254         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1255         priv->aligned_buffer = aligned_buffer_addr;
1256         priv->status_buffer = status_buffer_addr;
1257
1258         /* board-dependant init */
1259         if (board_usb_init(index, USB_INIT_HOST))
1260                 return -1;
1261
1262         return dwc2_init_common(NULL, priv);
1263 }
1264
1265 int usb_lowlevel_stop(int index)
1266 {
1267         dwc2_uninit_common(local.regs);
1268
1269         return 0;
1270 }
1271 #endif
1272
1273 #if CONFIG_IS_ENABLED(DM_USB)
1274 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1275                                    unsigned long pipe, void *buffer, int length,
1276                                    struct devrequest *setup)
1277 {
1278         struct dwc2_priv *priv = dev_get_priv(dev);
1279
1280         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1281               dev->name, udev, udev->dev->name, udev->portnr);
1282
1283         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1284 }
1285
1286 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1287                                 unsigned long pipe, void *buffer, int length)
1288 {
1289         struct dwc2_priv *priv = dev_get_priv(dev);
1290
1291         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1292
1293         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1294 }
1295
1296 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1297                                unsigned long pipe, void *buffer, int length,
1298                                int interval, bool nonblock)
1299 {
1300         struct dwc2_priv *priv = dev_get_priv(dev);
1301
1302         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1303
1304         return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1305                                nonblock);
1306 }
1307
1308 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1309 {
1310         struct dwc2_priv *priv = dev_get_priv(dev);
1311         fdt_addr_t addr;
1312
1313         addr = dev_read_addr(dev);
1314         if (addr == FDT_ADDR_T_NONE)
1315                 return -EINVAL;
1316         priv->regs = (struct dwc2_core_regs *)addr;
1317
1318         priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1319         priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1320
1321         return 0;
1322 }
1323
1324 static int dwc2_usb_probe(struct udevice *dev)
1325 {
1326         struct dwc2_priv *priv = dev_get_priv(dev);
1327         struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1328
1329         bus_priv->desc_before_addr = true;
1330
1331         return dwc2_init_common(dev, priv);
1332 }
1333
1334 static int dwc2_usb_remove(struct udevice *dev)
1335 {
1336         struct dwc2_priv *priv = dev_get_priv(dev);
1337         int ret;
1338
1339         ret = dwc_vbus_supply_exit(dev);
1340         if (ret)
1341                 return ret;
1342
1343         dwc2_uninit_common(priv->regs);
1344
1345         reset_release_bulk(&priv->resets);
1346
1347         return 0;
1348 }
1349
1350 struct dm_usb_ops dwc2_usb_ops = {
1351         .control = dwc2_submit_control_msg,
1352         .bulk = dwc2_submit_bulk_msg,
1353         .interrupt = dwc2_submit_int_msg,
1354 };
1355
1356 static const struct udevice_id dwc2_usb_ids[] = {
1357         { .compatible = "brcm,bcm2835-usb" },
1358         { .compatible = "brcm,bcm2708-usb" },
1359         { .compatible = "snps,dwc2" },
1360         { }
1361 };
1362
1363 U_BOOT_DRIVER(usb_dwc2) = {
1364         .name   = "dwc2_usb",
1365         .id     = UCLASS_USB,
1366         .of_match = dwc2_usb_ids,
1367         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1368         .probe  = dwc2_usb_probe,
1369         .remove = dwc2_usb_remove,
1370         .ops    = &dwc2_usb_ops,
1371         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1372         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1373 };
1374 #endif