drivers/usb/host/dwc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   4  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <generic-phy.h>
  13 #include <log.h>
  14 #include <malloc.h>
  15 #include <memalign.h>
  16 #include <phys2bus.h>
  17 #include <usb.h>
  18 #include <usbroothubdes.h>
  19 #include <wait_bit.h>
  20 #include <asm/cache.h>
  21 #include <asm/io.h>
  22 #include <dm/device_compat.h>
  23 #include <power/regulator.h>
  24 #include <reset.h>
  25
  26 #include "dwc2.h"
  27
  28 /* Use only HC channel 0. */
  29 #define DWC2_HC_CHANNEL                 0
  30
  31 #define DWC2_STATUS_BUF_SIZE            64
  32 #define DWC2_DATA_BUF_SIZE              (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
  33
  34 #define MAX_DEVICE                      16
  35 #define MAX_ENDPOINT                    16
  36
  37 struct dwc2_priv {
  38 #if CONFIG_IS_ENABLED(DM_USB)
  39         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  40         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  41 #ifdef CONFIG_DM_REGULATOR
  42         struct udevice *vbus_supply;
  43 #endif
  44         struct phy phy;
  45         struct clk_bulk clks;
  46 #else
  47         uint8_t *aligned_buffer;
  48         uint8_t *status_buffer;
  49 #endif
  50         u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  51         u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  52         struct dwc2_core_regs *regs;
  53         int root_hub_devnum;
  54         bool ext_vbus;
  55         /*
  56          * The hnp/srp capability must be disabled if the platform
  57          * does't support hnp/srp. Otherwise the force mode can't work.
  58          */
  59         bool hnp_srp_disable;
  60         bool oc_disable;
  61
  62         struct reset_ctl_bulk   resets;
  63 };
  64
  65 #if !CONFIG_IS_ENABLED(DM_USB)
  66 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  67 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  68                 ARCH_DMA_MINALIGN);
  69 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  70                 ARCH_DMA_MINALIGN);
  71
  72 static struct dwc2_priv local;
  73 #endif
  74
  75 /*
  76  * DWC2 IP interface
  77  */
  78
  79 /*
  80  * Initializes the FSLSPClkSel field of the HCFG register
  81  * depending on the PHY type.
  82  */
  83 static void init_fslspclksel(struct dwc2_core_regs *regs)
  84 {
  85         uint32_t phyclk;
  86
  87 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  88         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  89 #else
  90         /* High speed PHY running at full speed or high speed */
  91         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  92 #endif
  93
  94 #ifdef CONFIG_DWC2_ULPI_FS_LS
  95         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  96         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  97                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  98         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  99                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 100
 101         if (hval == 2 && fval == 1)
 102                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
 103 #endif
 104
 105         clrsetbits_le32(&regs->host_regs.hcfg,
 106                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 107                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 108 }
 109
 110 /*
 111  * Flush a Tx FIFO.
 112  *
 113  * @param regs Programming view of DWC_otg controller.
 114  * @param num Tx FIFO to flush.
 115  */
 116 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 117 {
 118         int ret;
 119
 120         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 121                &regs->grstctl);
 122         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
 123                                 false, 1000, false);
 124         if (ret)
 125                 dev_info(dev, "%s: Timeout!\n", __func__);
 126
 127         /* Wait for 3 PHY Clocks */
 128         udelay(1);
 129 }
 130
 131 /*
 132  * Flush Rx FIFO.
 133  *
 134  * @param regs Programming view of DWC_otg controller.
 135  */
 136 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 137 {
 138         int ret;
 139
 140         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 141         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
 142                                 false, 1000, false);
 143         if (ret)
 144                 dev_info(dev, "%s: Timeout!\n", __func__);
 145
 146         /* Wait for 3 PHY Clocks */
 147         udelay(1);
 148 }
 149
 150 /*
 151  * Do core a soft reset of the core.  Be careful with this because it
 152  * resets all the internal state machines of the core.
 153  */
 154 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 155 {
 156         int ret;
 157
 158         /* Wait for AHB master IDLE state. */
 159         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
 160                                 true, 1000, false);
 161         if (ret)
 162                 dev_info(dev, "%s: Timeout!\n", __func__);
 163
 164         /* Core Soft Reset */
 165         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 166         ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
 167                                 false, 1000, false);
 168         if (ret)
 169                 dev_info(dev, "%s: Timeout!\n", __func__);
 170
 171         /*
 172          * Wait for core to come out of reset.
 173          * NOTE: This long sleep is _very_ important, otherwise the core will
 174          *       not stay in host mode after a connector ID change!
 175          */
 176         mdelay(100);
 177 }
 178
 179 #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
 180 static int dwc_vbus_supply_init(struct udevice *dev)
 181 {
 182         struct dwc2_priv *priv = dev_get_priv(dev);
 183         int ret;
 184
 185         ret = device_get_supply_regulator(dev, "vbus-supply",
 186                                           &priv->vbus_supply);
 187         if (ret) {
 188                 debug("%s: No vbus supply\n", dev->name);
 189                 return 0;
 190         }
 191
 192         ret = regulator_set_enable(priv->vbus_supply, true);
 193         if (ret) {
 194                 dev_err(dev, "Error enabling vbus supply\n");
 195                 return ret;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int dwc_vbus_supply_exit(struct udevice *dev)
 202 {
 203         struct dwc2_priv *priv = dev_get_priv(dev);
 204         int ret;
 205
 206         if (priv->vbus_supply) {
 207                 ret = regulator_set_enable(priv->vbus_supply, false);
 208                 if (ret) {
 209                         dev_err(dev, "Error disabling vbus supply\n");
 210                         return ret;
 211                 }
 212         }
 213
 214         return 0;
 215 }
 216 #else
 217 static int dwc_vbus_supply_init(struct udevice *dev)
 218 {
 219         return 0;
 220 }
 221
 222 #if CONFIG_IS_ENABLED(DM_USB)
 223 static int dwc_vbus_supply_exit(struct udevice *dev)
 224 {
 225         return 0;
 226 }
 227 #endif
 228 #endif
 229
 230 /*
 231  * This function initializes the DWC_otg controller registers for
 232  * host mode.
 233  *
 234  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 235  * request queues. Host channels are reset to ensure that they are ready for
 236  * performing transfers.
 237  *
 238  * @param dev USB Device (NULL if driver model is not being used)
 239  * @param regs Programming view of DWC_otg controller
 240  *
 241  */
 242 static void dwc_otg_core_host_init(struct udevice *dev,
 243                                    struct dwc2_core_regs *regs)
 244 {
 245         uint32_t nptxfifosize = 0;
 246         uint32_t ptxfifosize = 0;
 247         uint32_t hprt0 = 0;
 248         int i, ret, num_channels;
 249
 250         /* Restart the Phy Clock */
 251         writel(0, &regs->pcgcctl);
 252
 253         /* Initialize Host Configuration Register */
 254         init_fslspclksel(regs);
 255 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 256         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 257 #endif
 258
 259         /* Configure data FIFO sizes */
 260 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 261         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 262                 /* Rx FIFO */
 263                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 264
 265                 /* Non-periodic Tx FIFO */
 266                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 267                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 268                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 269                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 270                 writel(nptxfifosize, &regs->gnptxfsiz);
 271
 272                 /* Periodic Tx FIFO */
 273                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 274                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 275                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 276                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 277                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 278                 writel(ptxfifosize, &regs->hptxfsiz);
 279         }
 280 #endif
 281
 282         /* Clear Host Set HNP Enable in the OTG Control Register */
 283         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 284
 285         /* Make sure the FIFOs are flushed. */
 286         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 287         dwc_otg_flush_rx_fifo(regs);
 288
 289         /* Flush out any leftover queued requests. */
 290         num_channels = readl(&regs->ghwcfg2);
 291         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 292         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 293         num_channels += 1;
 294
 295         for (i = 0; i < num_channels; i++)
 296                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 297                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 298                                 DWC2_HCCHAR_CHDIS);
 299
 300         /* Halt all channels to put them into a known state. */
 301         for (i = 0; i < num_channels; i++) {
 302                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 303                                 DWC2_HCCHAR_EPDIR,
 304                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 305                 ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
 306                                         DWC2_HCCHAR_CHEN, false, 1000, false);
 307                 if (ret)
 308                         dev_info("%s: Timeout!\n", __func__);
 309         }
 310
 311         /* Turn on the vbus power. */
 312         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 313                 hprt0 = readl(&regs->hprt0);
 314                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 315                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 316                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 317                         hprt0 |= DWC2_HPRT0_PRTPWR;
 318                         writel(hprt0, &regs->hprt0);
 319                 }
 320         }
 321
 322         if (dev)
 323                 dwc_vbus_supply_init(dev);
 324 }
 325
 326 /*
 327  * This function initializes the DWC_otg controller registers and
 328  * prepares the core for device mode or host mode operation.
 329  *
 330  * @param regs Programming view of the DWC_otg controller
 331  */
 332 static void dwc_otg_core_init(struct dwc2_priv *priv)
 333 {
 334         struct dwc2_core_regs *regs = priv->regs;
 335         uint32_t ahbcfg = 0;
 336         uint32_t usbcfg = 0;
 337         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 338
 339         /* Common Initialization */
 340         usbcfg = readl(&regs->gusbcfg);
 341
 342         /* Program the ULPI External VBUS bit if needed */
 343         if (priv->ext_vbus) {
 344                 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 345                 if (!priv->oc_disable) {
 346                         usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
 347                                   DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
 348                 }
 349         } else {
 350                 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 351         }
 352
 353         /* Set external TS Dline pulsing */
 354 #ifdef CONFIG_DWC2_TS_DLINE
 355         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 356 #else
 357         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 358 #endif
 359         writel(usbcfg, &regs->gusbcfg);
 360
 361         /* Reset the Controller */
 362         dwc_otg_core_reset(regs);
 363
 364         /*
 365          * This programming sequence needs to happen in FS mode before
 366          * any other programming occurs
 367          */
 368 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 369         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 370         /* If FS mode with FS PHY */
 371         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 372
 373         /* Reset after a PHY select */
 374         dwc_otg_core_reset(regs);
 375
 376         /*
 377          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 378          * Also do this on HNP Dev/Host mode switches (done in dev_init
 379          * and host_init).
 380          */
 381         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 382                 init_fslspclksel(regs);
 383
 384 #ifdef CONFIG_DWC2_I2C_ENABLE
 385         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 386         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 387
 388         /* Program GI2CCTL.I2CEn */
 389         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 390                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 391                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 392         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 393 #endif
 394
 395 #else
 396         /* High speed PHY. */
 397
 398         /*
 399          * HS PHY parameters. These parameters are preserved during
 400          * soft reset so only program the first time. Do a soft reset
 401          * immediately after setting phyif.
 402          */
 403         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 404         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 405
 406         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 407 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 408                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 409 #else
 410                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 411 #endif
 412         } else {        /* UTMI+ interface */
 413 #if (CONFIG_DWC2_UTMI_WIDTH == 16)
 414                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 415 #endif
 416         }
 417
 418         writel(usbcfg, &regs->gusbcfg);
 419
 420         /* Reset after setting the PHY parameters */
 421         dwc_otg_core_reset(regs);
 422 #endif
 423
 424         usbcfg = readl(&regs->gusbcfg);
 425         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 426 #ifdef CONFIG_DWC2_ULPI_FS_LS
 427         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 428         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 429                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 430         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 431                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 432         if (hval == 2 && fval == 1) {
 433                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 434                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 435         }
 436 #endif
 437         if (priv->hnp_srp_disable)
 438                 usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
 439
 440         writel(usbcfg, &regs->gusbcfg);
 441
 442         /* Program the GAHBCFG Register. */
 443         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 444         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 445                 break;
 446         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 447                 while (brst_sz > 1) {
 448                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 449                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 450                         brst_sz >>= 1;
 451                 }
 452
 453 #ifdef CONFIG_DWC2_DMA_ENABLE
 454                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 455 #endif
 456                 break;
 457
 458         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 459                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 460 #ifdef CONFIG_DWC2_DMA_ENABLE
 461                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 462 #endif
 463                 break;
 464         }
 465
 466         writel(ahbcfg, &regs->gahbcfg);
 467
 468         /* Program the capabilities in GUSBCFG Register */
 469         usbcfg = 0;
 470
 471         if (!priv->hnp_srp_disable)
 472                 usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
 473 #ifdef CONFIG_DWC2_IC_USB_CAP
 474         usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
 475 #endif
 476
 477         setbits_le32(&regs->gusbcfg, usbcfg);
 478 }
 479
 480 /*
 481  * Prepares a host channel for transferring packets to/from a specific
 482  * endpoint. The HCCHARn register is set up with the characteristics specified
 483  * in _hc. Host channel interrupts that may need to be serviced while this
 484  * transfer is in progress are enabled.
 485  *
 486  * @param regs Programming view of DWC_otg controller
 487  * @param hc Information needed to initialize the host channel
 488  */
 489 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 490                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 491                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 492 {
 493         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 494         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 495                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 496                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 497                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 498                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 499
 500         if (dev->speed == USB_SPEED_LOW)
 501                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 502
 503         /*
 504          * Program the HCCHARn register with the endpoint characteristics
 505          * for the current transfer.
 506          */
 507         writel(hcchar, &hc_regs->hcchar);
 508
 509         /* Program the HCSPLIT register, default to no SPLIT */
 510         writel(0, &hc_regs->hcsplt);
 511 }
 512
 513 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
 514                                   uint8_t hub_devnum, uint8_t hub_port)
 515 {
 516         uint32_t hcsplt = 0;
 517
 518         hcsplt = DWC2_HCSPLT_SPLTENA;
 519         hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
 520         hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
 521
 522         /* Program the HCSPLIT register for SPLITs */
 523         writel(hcsplt, &hc_regs->hcsplt);
 524 }
 525
 526 /*
 527  * DWC2 to USB API interface
 528  */
 529 /* Direction: In ; Request: Status */
 530 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 531                                            struct usb_device *dev, void *buffer,
 532                                            int txlen, struct devrequest *cmd)
 533 {
 534         uint32_t hprt0 = 0;
 535         uint32_t port_status = 0;
 536         uint32_t port_change = 0;
 537         int len = 0;
 538         int stat = 0;
 539
 540         switch (cmd->requesttype & ~USB_DIR_IN) {
 541         case 0:
 542                 *(uint16_t *)buffer = cpu_to_le16(1);
 543                 len = 2;
 544                 break;
 545         case USB_RECIP_INTERFACE:
 546         case USB_RECIP_ENDPOINT:
 547                 *(uint16_t *)buffer = cpu_to_le16(0);
 548                 len = 2;
 549                 break;
 550         case USB_TYPE_CLASS:
 551                 *(uint32_t *)buffer = cpu_to_le32(0);
 552                 len = 4;
 553                 break;
 554         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 555                 hprt0 = readl(&regs->hprt0);
 556                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 557                         port_status |= USB_PORT_STAT_CONNECTION;
 558                 if (hprt0 & DWC2_HPRT0_PRTENA)
 559                         port_status |= USB_PORT_STAT_ENABLE;
 560                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 561                         port_status |= USB_PORT_STAT_SUSPEND;
 562                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 563                         port_status |= USB_PORT_STAT_OVERCURRENT;
 564                 if (hprt0 & DWC2_HPRT0_PRTRST)
 565                         port_status |= USB_PORT_STAT_RESET;
 566                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 567                         port_status |= USB_PORT_STAT_POWER;
 568
 569                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 570                         port_status |= USB_PORT_STAT_LOW_SPEED;
 571                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 572                          DWC2_HPRT0_PRTSPD_HIGH)
 573                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 574
 575                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 576                         port_change |= USB_PORT_STAT_C_ENABLE;
 577                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 578                         port_change |= USB_PORT_STAT_C_CONNECTION;
 579                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 580                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 581
 582                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 583                                         (port_change << 16));
 584                 len = 4;
 585                 break;
 586         default:
 587                 puts("unsupported root hub command\n");
 588                 stat = USB_ST_STALLED;
 589         }
 590
 591         dev->act_len = min(len, txlen);
 592         dev->status = stat;
 593
 594         return stat;
 595 }
 596
 597 /* Direction: In ; Request: Descriptor */
 598 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 599                                                void *buffer, int txlen,
 600                                                struct devrequest *cmd)
 601 {
 602         unsigned char data[32];
 603         uint32_t dsc;
 604         int len = 0;
 605         int stat = 0;
 606         uint16_t wValue = cpu_to_le16(cmd->value);
 607         uint16_t wLength = cpu_to_le16(cmd->length);
 608
 609         switch (cmd->requesttype & ~USB_DIR_IN) {
 610         case 0:
 611                 switch (wValue & 0xff00) {
 612                 case 0x0100:    /* device descriptor */
 613                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 614                         memcpy(buffer, root_hub_dev_des, len);
 615                         break;
 616                 case 0x0200:    /* configuration descriptor */
 617                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 618                         memcpy(buffer, root_hub_config_des, len);
 619                         break;
 620                 case 0x0300:    /* string descriptors */
 621                         switch (wValue & 0xff) {
 622                         case 0x00:
 623                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 624                                            (int)wLength);
 625                                 memcpy(buffer, root_hub_str_index0, len);
 626                                 break;
 627                         case 0x01:
 628                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 629                                            (int)wLength);
 630                                 memcpy(buffer, root_hub_str_index1, len);
 631                                 break;
 632                         }
 633                         break;
 634                 default:
 635                         stat = USB_ST_STALLED;
 636                 }
 637                 break;
 638
 639         case USB_TYPE_CLASS:
 640                 /* Root port config, set 1 port and nothing else. */
 641                 dsc = 0x00000001;
 642
 643                 data[0] = 9;            /* min length; */
 644                 data[1] = 0x29;
 645                 data[2] = dsc & RH_A_NDP;
 646                 data[3] = 0;
 647                 if (dsc & RH_A_PSM)
 648                         data[3] |= 0x1;
 649                 if (dsc & RH_A_NOCP)
 650                         data[3] |= 0x10;
 651                 else if (dsc & RH_A_OCPM)
 652                         data[3] |= 0x8;
 653
 654                 /* corresponds to data[4-7] */
 655                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 656                 data[7] = dsc & RH_B_DR;
 657                 if (data[2] < 7) {
 658                         data[8] = 0xff;
 659                 } else {
 660                         data[0] += 2;
 661                         data[8] = (dsc & RH_B_DR) >> 8;
 662                         data[9] = 0xff;
 663                         data[10] = data[9];
 664                 }
 665
 666                 len = min3(txlen, (int)data[0], (int)wLength);
 667                 memcpy(buffer, data, len);
 668                 break;
 669         default:
 670                 puts("unsupported root hub command\n");
 671                 stat = USB_ST_STALLED;
 672         }
 673
 674         dev->act_len = min(len, txlen);
 675         dev->status = stat;
 676
 677         return stat;
 678 }
 679
 680 /* Direction: In ; Request: Configuration */
 681 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 682                                                   void *buffer, int txlen,
 683                                                   struct devrequest *cmd)
 684 {
 685         int len = 0;
 686         int stat = 0;
 687
 688         switch (cmd->requesttype & ~USB_DIR_IN) {
 689         case 0:
 690                 *(uint8_t *)buffer = 0x01;
 691                 len = 1;
 692                 break;
 693         default:
 694                 puts("unsupported root hub command\n");
 695                 stat = USB_ST_STALLED;
 696         }
 697
 698         dev->act_len = min(len, txlen);
 699         dev->status = stat;
 700
 701         return stat;
 702 }
 703
 704 /* Direction: In */
 705 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 706                                     struct usb_device *dev, void *buffer,
 707                                     int txlen, struct devrequest *cmd)
 708 {
 709         switch (cmd->request) {
 710         case USB_REQ_GET_STATUS:
 711                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 712                                                        txlen, cmd);
 713         case USB_REQ_GET_DESCRIPTOR:
 714                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 715                                                            txlen, cmd);
 716         case USB_REQ_GET_CONFIGURATION:
 717                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 718                                                               txlen, cmd);
 719         default:
 720                 puts("unsupported root hub command\n");
 721                 return USB_ST_STALLED;
 722         }
 723 }
 724
 725 /* Direction: Out */
 726 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 727                                      struct usb_device *dev,
 728                                      void *buffer, int txlen,
 729                                      struct devrequest *cmd)
 730 {
 731         struct dwc2_core_regs *regs = priv->regs;
 732         int len = 0;
 733         int stat = 0;
 734         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 735         uint16_t wValue = cpu_to_le16(cmd->value);
 736
 737         switch (bmrtype_breq & ~USB_DIR_IN) {
 738         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 739         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 740                 break;
 741
 742         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 743                 switch (wValue) {
 744                 case USB_PORT_FEAT_C_CONNECTION:
 745                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 746                         break;
 747                 }
 748                 break;
 749
 750         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 751                 switch (wValue) {
 752                 case USB_PORT_FEAT_SUSPEND:
 753                         break;
 754
 755                 case USB_PORT_FEAT_RESET:
 756                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 757                                         DWC2_HPRT0_PRTCONNDET |
 758                                         DWC2_HPRT0_PRTENCHNG |
 759                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 760                                         DWC2_HPRT0_PRTRST);
 761                         mdelay(50);
 762                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 763                         break;
 764
 765                 case USB_PORT_FEAT_POWER:
 766                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 767                                         DWC2_HPRT0_PRTCONNDET |
 768                                         DWC2_HPRT0_PRTENCHNG |
 769                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 770                                         DWC2_HPRT0_PRTRST);
 771                         break;
 772
 773                 case USB_PORT_FEAT_ENABLE:
 774                         break;
 775                 }
 776                 break;
 777         case (USB_REQ_SET_ADDRESS << 8):
 778                 priv->root_hub_devnum = wValue;
 779                 break;
 780         case (USB_REQ_SET_CONFIGURATION << 8):
 781                 break;
 782         default:
 783                 puts("unsupported root hub command\n");
 784                 stat = USB_ST_STALLED;
 785         }
 786
 787         len = min(len, txlen);
 788
 789         dev->act_len = len;
 790         dev->status = stat;
 791
 792         return stat;
 793 }
 794
 795 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 796                                  unsigned long pipe, void *buffer, int txlen,
 797                                  struct devrequest *cmd)
 798 {
 799         int stat = 0;
 800
 801         if (usb_pipeint(pipe)) {
 802                 puts("Root-Hub submit IRQ: NOT implemented\n");
 803                 return 0;
 804         }
 805
 806         if (cmd->requesttype & USB_DIR_IN)
 807                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 808         else
 809                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 810
 811         mdelay(1);
 812
 813         return stat;
 814 }
 815
 816 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
 817 {
 818         int ret;
 819         uint32_t hcint, hctsiz;
 820
 821         ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
 822                                 2000, false);
 823         if (ret)
 824                 return ret;
 825
 826         hcint = readl(&hc_regs->hcint);
 827         hctsiz = readl(&hc_regs->hctsiz);
 828         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 829                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 830         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 831
 832         debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
 833               *toggle);
 834
 835         if (hcint & DWC2_HCINT_XFERCOMP)
 836                 return 0;
 837
 838         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 839                 return -EAGAIN;
 840
 841         debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 842         return -EINVAL;
 843 }
 844
 845 static int dwc2_eptype[] = {
 846         DWC2_HCCHAR_EPTYPE_ISOC,
 847         DWC2_HCCHAR_EPTYPE_INTR,
 848         DWC2_HCCHAR_EPTYPE_CONTROL,
 849         DWC2_HCCHAR_EPTYPE_BULK,
 850 };
 851
 852 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
 853                           u8 *pid, int in, void *buffer, int num_packets,
 854                           int xfer_len, int *actual_len, int odd_frame)
 855 {
 856         int ret = 0;
 857         uint32_t sub;
 858
 859         debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 860               *pid, xfer_len, num_packets);
 861
 862         writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 863                (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 864                (*pid << DWC2_HCTSIZ_PID_OFFSET),
 865                &hc_regs->hctsiz);
 866
 867         if (xfer_len) {
 868                 if (in) {
 869                         invalidate_dcache_range(
 870                                         (uintptr_t)aligned_buffer,
 871                                         (uintptr_t)aligned_buffer +
 872                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 873                 } else {
 874                         memcpy(aligned_buffer, buffer, xfer_len);
 875                         flush_dcache_range(
 876                                         (uintptr_t)aligned_buffer,
 877                                         (uintptr_t)aligned_buffer +
 878                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 879                 }
 880         }
 881
 882         writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
 883
 884         /* Clear old interrupt conditions for this host channel. */
 885         writel(0x3fff, &hc_regs->hcint);
 886
 887         /* Set host channel enable after all other setup is complete. */
 888         clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 889                         DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
 890                         DWC2_HCCHAR_ODDFRM,
 891                         (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 892                         (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
 893                         DWC2_HCCHAR_CHEN);
 894
 895         ret = wait_for_chhltd(hc_regs, &sub, pid);
 896         if (ret < 0)
 897                 return ret;
 898
 899         if (in) {
 900                 xfer_len -= sub;
 901
 902                 invalidate_dcache_range((unsigned long)aligned_buffer,
 903                                         (unsigned long)aligned_buffer +
 904                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 905
 906                 memcpy(buffer, aligned_buffer, xfer_len);
 907         }
 908         *actual_len = xfer_len;
 909
 910         return ret;
 911 }
 912
 913 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 914               unsigned long pipe, u8 *pid, int in, void *buffer, int len)
 915 {
 916         struct dwc2_core_regs *regs = priv->regs;
 917         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 918         struct dwc2_host_regs *host_regs = &regs->host_regs;
 919         int devnum = usb_pipedevice(pipe);
 920         int ep = usb_pipeendpoint(pipe);
 921         int max = usb_maxpacket(dev, pipe);
 922         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 923         int done = 0;
 924         int ret = 0;
 925         int do_split = 0;
 926         int complete_split = 0;
 927         uint32_t xfer_len;
 928         uint32_t num_packets;
 929         int stop_transfer = 0;
 930         uint32_t max_xfer_len;
 931         int ssplit_frame_num = 0;
 932
 933         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 934               in, len);
 935
 936         max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
 937         if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 938                 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
 939         if (max_xfer_len > DWC2_DATA_BUF_SIZE)
 940                 max_xfer_len = DWC2_DATA_BUF_SIZE;
 941
 942         /* Make sure that max_xfer_len is a multiple of max packet size. */
 943         num_packets = max_xfer_len / max;
 944         max_xfer_len = num_packets * max;
 945
 946         /* Initialize channel */
 947         dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 948                         eptype, max);
 949
 950         /* Check if the target is a FS/LS device behind a HS hub */
 951         if (dev->speed != USB_SPEED_HIGH) {
 952                 uint8_t hub_addr;
 953                 uint8_t hub_port;
 954                 uint32_t hprt0 = readl(&regs->hprt0);
 955                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 956                      DWC2_HPRT0_PRTSPD_HIGH) {
 957                         usb_find_usb2_hub_address_port(dev, &hub_addr,
 958                                                        &hub_port);
 959                         dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
 960
 961                         do_split = 1;
 962                         num_packets = 1;
 963                         max_xfer_len = max;
 964                 }
 965         }
 966
 967         do {
 968                 int actual_len = 0;
 969                 uint32_t hcint;
 970                 int odd_frame = 0;
 971                 xfer_len = len - done;
 972
 973                 if (xfer_len > max_xfer_len)
 974                         xfer_len = max_xfer_len;
 975                 else if (xfer_len > max)
 976                         num_packets = (xfer_len + max - 1) / max;
 977                 else
 978                         num_packets = 1;
 979
 980                 if (complete_split)
 981                         setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 982                 else if (do_split)
 983                         clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 984
 985                 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
 986                         int uframe_num = readl(&host_regs->hfnum);
 987                         if (!(uframe_num & 0x1))
 988                                 odd_frame = 1;
 989                 }
 990
 991                 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 992                                      in, (char *)buffer + done, num_packets,
 993                                      xfer_len, &actual_len, odd_frame);
 994
 995                 hcint = readl(&hc_regs->hcint);
 996                 if (complete_split) {
 997                         stop_transfer = 0;
 998                         if (hcint & DWC2_HCINT_NYET) {
 999                                 ret = 0;
1000                                 int frame_num = DWC2_HFNUM_MAX_FRNUM &
1001                                                 readl(&host_regs->hfnum);
1002                                 if (((frame_num - ssplit_frame_num) &
1003                                     DWC2_HFNUM_MAX_FRNUM) > 4)
1004                                         ret = -EAGAIN;
1005                         } else
1006                                 complete_split = 0;
1007                 } else if (do_split) {
1008                         if (hcint & DWC2_HCINT_ACK) {
1009                                 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
1010                                                    readl(&host_regs->hfnum);
1011                                 ret = 0;
1012                                 complete_split = 1;
1013                         }
1014                 }
1015
1016                 if (ret)
1017                         break;
1018
1019                 if (actual_len < xfer_len)
1020                         stop_transfer = 1;
1021
1022                 done += actual_len;
1023
1024         /* Transactions are done when when either all data is transferred or
1025          * there is a short transfer. In case of a SPLIT make sure the CSPLIT
1026          * is executed.
1027          */
1028         } while (((done < len) && !stop_transfer) || complete_split);
1029
1030         writel(0, &hc_regs->hcintmsk);
1031         writel(0xFFFFFFFF, &hc_regs->hcint);
1032
1033         dev->status = 0;
1034         dev->act_len = done;
1035
1036         return ret;
1037 }
1038
1039 /* U-Boot USB transmission interface */
1040 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
1041                      unsigned long pipe, void *buffer, int len)
1042 {
1043         int devnum = usb_pipedevice(pipe);
1044         int ep = usb_pipeendpoint(pipe);
1045         u8* pid;
1046
1047         if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
1048                 dev->status = 0;
1049                 return -EINVAL;
1050         }
1051
1052         if (usb_pipein(pipe))
1053                 pid = &priv->in_data_toggle[devnum][ep];
1054         else
1055                 pid = &priv->out_data_toggle[devnum][ep];
1056
1057         return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1058 }
1059
1060 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1061                                unsigned long pipe, void *buffer, int len,
1062                                struct devrequest *setup)
1063 {
1064         int devnum = usb_pipedevice(pipe);
1065         int ret, act_len;
1066         u8 pid;
1067         /* For CONTROL endpoint pid should start with DATA1 */
1068         int status_direction;
1069
1070         if (devnum == priv->root_hub_devnum) {
1071                 dev->status = 0;
1072                 dev->speed = USB_SPEED_HIGH;
1073                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1074                                              setup);
1075         }
1076
1077         /* SETUP stage */
1078         pid = DWC2_HC_PID_SETUP;
1079         do {
1080                 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1081         } while (ret == -EAGAIN);
1082         if (ret)
1083                 return ret;
1084
1085         /* DATA stage */
1086         act_len = 0;
1087         if (buffer) {
1088                 pid = DWC2_HC_PID_DATA1;
1089                 do {
1090                         ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1091                                         buffer, len);
1092                         act_len += dev->act_len;
1093                         buffer += dev->act_len;
1094                         len -= dev->act_len;
1095                 } while (ret == -EAGAIN);
1096                 if (ret)
1097                         return ret;
1098                 status_direction = usb_pipeout(pipe);
1099         } else {
1100                 /* No-data CONTROL always ends with an IN transaction */
1101                 status_direction = 1;
1102         }
1103
1104         /* STATUS stage */
1105         pid = DWC2_HC_PID_DATA1;
1106         do {
1107                 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1108                                 priv->status_buffer, 0);
1109         } while (ret == -EAGAIN);
1110         if (ret)
1111                 return ret;
1112
1113         dev->act_len = act_len;
1114
1115         return 0;
1116 }
1117
1118 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1119                     unsigned long pipe, void *buffer, int len, int interval,
1120                     bool nonblock)
1121 {
1122         unsigned long timeout;
1123         int ret;
1124
1125         /* FIXME: what is interval? */
1126
1127         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1128         for (;;) {
1129                 if (get_timer(0) > timeout) {
1130                         dev_err(dev, "Timeout poll on interrupt endpoint\n");
1131                         return -ETIMEDOUT;
1132                 }
1133                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1134                 if ((ret != -EAGAIN) || nonblock)
1135                         return ret;
1136         }
1137 }
1138
1139 static int dwc2_reset(struct udevice *dev)
1140 {
1141         int ret;
1142         struct dwc2_priv *priv = dev_get_priv(dev);
1143
1144         ret = reset_get_bulk(dev, &priv->resets);
1145         if (ret) {
1146                 dev_warn(dev, "Can't get reset: %d\n", ret);
1147                 /* Return 0 if error due to !CONFIG_DM_RESET and reset
1148                  * DT property is not present.
1149                  */
1150                 if (ret == -ENOENT || ret == -ENOTSUPP)
1151                         return 0;
1152                 else
1153                         return ret;
1154         }
1155
1156         /* force reset to clear all IP register */
1157         reset_assert_bulk(&priv->resets);
1158         ret = reset_deassert_bulk(&priv->resets);
1159         if (ret) {
1160                 reset_release_bulk(&priv->resets);
1161                 dev_err(dev, "Failed to reset: %d\n", ret);
1162                 return ret;
1163         }
1164
1165         return 0;
1166 }
1167
1168 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1169 {
1170         struct dwc2_core_regs *regs = priv->regs;
1171         uint32_t snpsid;
1172         int i, j;
1173         int ret;
1174
1175         ret = dwc2_reset(dev);
1176         if (ret)
1177                 return ret;
1178
1179         snpsid = readl(&regs->gsnpsid);
1180         dev_info(dev, "Core Release: %x.%03x\n",
1181                  snpsid >> 12 & 0xf, snpsid & 0xfff);
1182
1183         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1184             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1185                 dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
1186                          snpsid);
1187                 return -ENODEV;
1188         }
1189
1190 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1191         priv->ext_vbus = 1;
1192 #else
1193         priv->ext_vbus = 0;
1194 #endif
1195
1196         dwc_otg_core_init(priv);
1197         dwc_otg_core_host_init(dev, regs);
1198
1199         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1200                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1201                         DWC2_HPRT0_PRTOVRCURRCHNG,
1202                         DWC2_HPRT0_PRTRST);
1203         mdelay(50);
1204         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1205                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1206                      DWC2_HPRT0_PRTRST);
1207
1208         for (i = 0; i < MAX_DEVICE; i++) {
1209                 for (j = 0; j < MAX_ENDPOINT; j++) {
1210                         priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1211                         priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1212                 }
1213         }
1214
1215         /*
1216          * Add a 1 second delay here. This gives the host controller
1217          * a bit time before the comminucation with the USB devices
1218          * is started (the bus is scanned) and  fixes the USB detection
1219          * problems with some problematic USB keys.
1220          */
1221         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1222                 mdelay(1000);
1223
1224         printf("USB DWC2\n");
1225
1226         return 0;
1227 }
1228
1229 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1230 {
1231         /* Put everything in reset. */
1232         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1233                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1234                         DWC2_HPRT0_PRTOVRCURRCHNG,
1235                         DWC2_HPRT0_PRTRST);
1236 }
1237
1238 #if !CONFIG_IS_ENABLED(DM_USB)
1239 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1240                        int len, struct devrequest *setup)
1241 {
1242         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1243 }
1244
1245 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1246                     int len)
1247 {
1248         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1249 }
1250
1251 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1252                    int len, int interval, bool nonblock)
1253 {
1254         return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
1255                                nonblock);
1256 }
1257
1258 /* U-Boot USB control interface */
1259 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1260 {
1261         struct dwc2_priv *priv = &local;
1262
1263         memset(priv, '\0', sizeof(*priv));
1264         priv->root_hub_devnum = 0;
1265         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1266         priv->aligned_buffer = aligned_buffer_addr;
1267         priv->status_buffer = status_buffer_addr;
1268
1269         /* board-dependant init */
1270         if (board_usb_init(index, USB_INIT_HOST))
1271                 return -1;
1272
1273         return dwc2_init_common(NULL, priv);
1274 }
1275
1276 int usb_lowlevel_stop(int index)
1277 {
1278         dwc2_uninit_common(local.regs);
1279
1280         return 0;
1281 }
1282 #endif
1283
1284 #if CONFIG_IS_ENABLED(DM_USB)
1285 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1286                                    unsigned long pipe, void *buffer, int length,
1287                                    struct devrequest *setup)
1288 {
1289         struct dwc2_priv *priv = dev_get_priv(dev);
1290
1291         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1292               dev->name, udev, udev->dev->name, udev->portnr);
1293
1294         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1295 }
1296
1297 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1298                                 unsigned long pipe, void *buffer, int length)
1299 {
1300         struct dwc2_priv *priv = dev_get_priv(dev);
1301
1302         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1303
1304         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1305 }
1306
1307 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1308                                unsigned long pipe, void *buffer, int length,
1309                                int interval, bool nonblock)
1310 {
1311         struct dwc2_priv *priv = dev_get_priv(dev);
1312
1313         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1314
1315         return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
1316                                nonblock);
1317 }
1318
1319 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1320 {
1321         struct dwc2_priv *priv = dev_get_priv(dev);
1322         fdt_addr_t addr;
1323
1324         addr = dev_read_addr(dev);
1325         if (addr == FDT_ADDR_T_NONE)
1326                 return -EINVAL;
1327         priv->regs = (struct dwc2_core_regs *)addr;
1328
1329         priv->oc_disable = dev_read_bool(dev, "disable-over-current");
1330         priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
1331
1332         return 0;
1333 }
1334
1335 static int dwc2_setup_phy(struct udevice *dev)
1336 {
1337         struct dwc2_priv *priv = dev_get_priv(dev);
1338         int ret;
1339
1340         ret = generic_phy_get_by_index(dev, 0, &priv->phy);
1341         if (ret) {
1342                 if (ret == -ENOENT)
1343                         return 0; /* no PHY, nothing to do */
1344                 dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
1345                 return ret;
1346         }
1347
1348         ret = generic_phy_init(&priv->phy);
1349         if (ret) {
1350                 dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
1351                 return ret;
1352         }
1353
1354         ret = generic_phy_power_on(&priv->phy);
1355         if (ret) {
1356                 dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
1357                 generic_phy_exit(&priv->phy);
1358                 return ret;
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int dwc2_shutdown_phy(struct udevice *dev)
1365 {
1366         struct dwc2_priv *priv = dev_get_priv(dev);
1367         int ret;
1368
1369         /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
1370         if (!generic_phy_valid(&priv->phy))
1371                 return 0; /* no PHY, nothing to do */
1372
1373         ret = generic_phy_power_off(&priv->phy);
1374         if (ret) {
1375                 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1376                 return ret;
1377         }
1378
1379         ret = generic_phy_exit(&priv->phy);
1380         if (ret) {
1381                 dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
1382                 return ret;
1383         }
1384
1385         return 0;
1386 }
1387
1388 static int dwc2_clk_init(struct udevice *dev)
1389 {
1390         struct dwc2_priv *priv = dev_get_priv(dev);
1391         int ret;
1392
1393         ret = clk_get_bulk(dev, &priv->clks);
1394         if (ret == -ENOSYS || ret == -ENOENT)
1395                 return 0;
1396         if (ret)
1397                 return ret;
1398
1399         ret = clk_enable_bulk(&priv->clks);
1400         if (ret) {
1401                 clk_release_bulk(&priv->clks);
1402                 return ret;
1403         }
1404
1405         return 0;
1406 }
1407
1408 static int dwc2_usb_probe(struct udevice *dev)
1409 {
1410         struct dwc2_priv *priv = dev_get_priv(dev);
1411         struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1412         int ret;
1413
1414         bus_priv->desc_before_addr = true;
1415
1416         ret = dwc2_clk_init(dev);
1417         if (ret)
1418                 return ret;
1419
1420         ret = dwc2_setup_phy(dev);
1421         if (ret)
1422                 return ret;
1423
1424         return dwc2_init_common(dev, priv);
1425 }
1426
1427 static int dwc2_usb_remove(struct udevice *dev)
1428 {
1429         struct dwc2_priv *priv = dev_get_priv(dev);
1430         int ret;
1431
1432         ret = dwc_vbus_supply_exit(dev);
1433         if (ret)
1434                 return ret;
1435
1436         ret = dwc2_shutdown_phy(dev);
1437         if (ret) {
1438                 dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
1439                 return ret;
1440         }
1441
1442         dwc2_uninit_common(priv->regs);
1443
1444         reset_release_bulk(&priv->resets);
1445         clk_disable_bulk(&priv->clks);
1446         clk_release_bulk(&priv->clks);
1447
1448         return 0;
1449 }
1450
1451 struct dm_usb_ops dwc2_usb_ops = {
1452         .control = dwc2_submit_control_msg,
1453         .bulk = dwc2_submit_bulk_msg,
1454         .interrupt = dwc2_submit_int_msg,
1455 };
1456
1457 static const struct udevice_id dwc2_usb_ids[] = {
1458         { .compatible = "brcm,bcm2835-usb" },
1459         { .compatible = "brcm,bcm2708-usb" },
1460         { .compatible = "snps,dwc2" },
1461         { }
1462 };
1463
1464 U_BOOT_DRIVER(usb_dwc2) = {
1465         .name   = "dwc2_usb",
1466         .id     = UCLASS_USB,
1467         .of_match = dwc2_usb_ids,
1468         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1469         .probe  = dwc2_usb_probe,
1470         .remove = dwc2_usb_remove,
1471         .ops    = &dwc2_usb_ops,
1472         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1473         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1474 };
1475 #endif