drivers/usb/gadget/pxa25x_udc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
   4  *
   5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
   6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
   7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
   8  * Copyright (C) 2003 David Brownell
   9  * Copyright (C) 2003 Joshua Wise
  10  * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
  11  *
  12  * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
  13  */
  14
  15 #define CONFIG_USB_PXA25X_SMALL
  16 #define DRIVER_NAME "pxa25x_udc_linux"
  17 #define ARCH_HAS_PREFETCH
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <log.h>
  22 #include <asm/byteorder.h>
  23 #include <asm/system.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/unaligned.h>
  26 #include <dm/devres.h>
  27 #include <linux/bug.h>
  28 #include <linux/compat.h>
  29 #include <malloc.h>
  30 #include <asm/io.h>
  31 #include <asm/arch/pxa.h>
  32
  33 #include <linux/usb/ch9.h>
  34 #include <linux/usb/gadget.h>
  35 #include <asm/arch/pxa-regs.h>
  36
  37 #include "pxa25x_udc.h"
  38
  39 /*
  40  * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
  41  * series processors.  The UDC for the IXP 4xx series is very similar.
  42  * There are fifteen endpoints, in addition to ep0.
  43  *
  44  * Such controller drivers work with a gadget driver.  The gadget driver
  45  * returns descriptors, implements configuration and data protocols used
  46  * by the host to interact with this device, and allocates endpoints to
  47  * the different protocol interfaces.  The controller driver virtualizes
  48  * usb hardware so that the gadget drivers will be more portable.
  49  *
  50  * This UDC hardware wants to implement a bit too much USB protocol, so
  51  * it constrains the sorts of USB configuration change events that work.
  52  * The errata for these chips are misleading; some "fixed" bugs from
  53  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
  54  *
  55  * Note that the UDC hardware supports DMA (except on IXP) but that's
  56  * not used here.  IN-DMA (to host) is simple enough, when the data is
  57  * suitably aligned (16 bytes) ... the network stack doesn't do that,
  58  * other software can.  OUT-DMA is buggy in most chip versions, as well
  59  * as poorly designed (data toggle not automatic).  So this driver won't
  60  * bother using DMA.  (Mostly-working IN-DMA support was available in
  61  * kernels before 2.6.23, but was never enabled or well tested.)
  62  */
  63
  64 #define DRIVER_VERSION  "18-August-2012"
  65 #define DRIVER_DESC     "PXA 25x USB Device Controller driver"
  66
  67 static const char driver_name[] = "pxa25x_udc";
  68 static const char ep0name[] = "ep0";
  69
  70 /* Watchdog */
  71 static inline void start_watchdog(struct pxa25x_udc *udc)
  72 {
  73         debug("Started watchdog\n");
  74         udc->watchdog.base = get_timer(0);
  75         udc->watchdog.running = 1;
  76 }
  77
  78 static inline void stop_watchdog(struct pxa25x_udc *udc)
  79 {
  80         udc->watchdog.running = 0;
  81         debug("Stopped watchdog\n");
  82 }
  83
  84 static inline void test_watchdog(struct pxa25x_udc *udc)
  85 {
  86         if (!udc->watchdog.running)
  87                 return;
  88
  89         debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base),
  90                 udc->watchdog.period);
  91
  92         if (get_timer(udc->watchdog.base) >= udc->watchdog.period) {
  93                 stop_watchdog(udc);
  94                 udc->watchdog.function(udc);
  95         }
  96 }
  97
  98 static void udc_watchdog(struct pxa25x_udc *dev)
  99 {
 100         uint32_t udccs0 = readl(&dev->regs->udccs[0]);
 101
 102         debug("Fired up udc_watchdog\n");
 103
 104         local_irq_disable();
 105         if (dev->ep0state == EP0_STALL
 106                         && (udccs0 & UDCCS0_FST) == 0
 107                         && (udccs0 & UDCCS0_SST) == 0) {
 108                 writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]);
 109                 debug("ep0 re-stall\n");
 110                 start_watchdog(dev);
 111         }
 112         local_irq_enable();
 113 }
 114
 115 #ifdef DEBUG
 116
 117 static const char * const state_name[] = {
 118         "EP0_IDLE",
 119         "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
 120         "EP0_END_XFER", "EP0_STALL"
 121 };
 122
 123 static void
 124 dump_udccr(const char *label)
 125 {
 126         u32 udccr = readl(&UDC_REGS->udccr);
 127         debug("%s %02X =%s%s%s%s%s%s%s%s\n",
 128                 label, udccr,
 129                 (udccr & UDCCR_REM) ? " rem" : "",
 130                 (udccr & UDCCR_RSTIR) ? " rstir" : "",
 131                 (udccr & UDCCR_SRM) ? " srm" : "",
 132                 (udccr & UDCCR_SUSIR) ? " susir" : "",
 133                 (udccr & UDCCR_RESIR) ? " resir" : "",
 134                 (udccr & UDCCR_RSM) ? " rsm" : "",
 135                 (udccr & UDCCR_UDA) ? " uda" : "",
 136                 (udccr & UDCCR_UDE) ? " ude" : "");
 137 }
 138
 139 static void
 140 dump_udccs0(const char *label)
 141 {
 142         u32 udccs0 = readl(&UDC_REGS->udccs[0]);
 143
 144         debug("%s %s %02X =%s%s%s%s%s%s%s%s\n",
 145                 label, state_name[the_controller->ep0state], udccs0,
 146                 (udccs0 & UDCCS0_SA) ? " sa" : "",
 147                 (udccs0 & UDCCS0_RNE) ? " rne" : "",
 148                 (udccs0 & UDCCS0_FST) ? " fst" : "",
 149                 (udccs0 & UDCCS0_SST) ? " sst" : "",
 150                 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
 151                 (udccs0 & UDCCS0_FTF) ? " ftf" : "",
 152                 (udccs0 & UDCCS0_IPR) ? " ipr" : "",
 153                 (udccs0 & UDCCS0_OPR) ? " opr" : "");
 154 }
 155
 156 static void
 157 dump_state(struct pxa25x_udc *dev)
 158 {
 159         u32 tmp;
 160         unsigned i;
 161
 162         debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
 163                 state_name[dev->ep0state],
 164                 readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0),
 165                 readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0),
 166                 readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl));
 167         dump_udccr("udccr");
 168         if (dev->has_cfr) {
 169                 tmp = readl(&UDC_REGS->udccfr);
 170                 debug("udccfr %02X =%s%s\n", tmp,
 171                         (tmp & UDCCFR_AREN) ? " aren" : "",
 172                         (tmp & UDCCFR_ACM) ? " acm" : "");
 173         }
 174
 175         if (!dev->driver) {
 176                 debug("no gadget driver bound\n");
 177                 return;
 178         } else
 179                 debug("ep0 driver '%s'\n", "ether");
 180
 181         dump_udccs0("udccs0");
 182         debug("ep0 IN %lu/%lu, OUT %lu/%lu\n",
 183                 dev->stats.write.bytes, dev->stats.write.ops,
 184                 dev->stats.read.bytes, dev->stats.read.ops);
 185
 186         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
 187                 if (dev->ep[i].desc == NULL)
 188                         continue;
 189                 debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
 190         }
 191 }
 192
 193 #else /* DEBUG */
 194
 195 static inline void dump_udccr(const char *label) { }
 196 static inline void dump_udccs0(const char *label) { }
 197 static inline void dump_state(struct pxa25x_udc *dev) { }
 198
 199 #endif /* DEBUG */
 200
 201 /*
 202  * ---------------------------------------------------------------------------
 203  *      endpoint related parts of the api to the usb controller hardware,
 204  *      used by gadget driver; and the inner talker-to-hardware core.
 205  * ---------------------------------------------------------------------------
 206  */
 207
 208 static void pxa25x_ep_fifo_flush(struct usb_ep *ep);
 209 static void nuke(struct pxa25x_ep *, int status);
 210
 211 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
 212 static void pullup_off(void)
 213 {
 214         struct pxa2xx_udc_mach_info *mach = the_controller->mach;
 215
 216         if (mach->udc_command)
 217                 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
 218 }
 219
 220 static void pullup_on(void)
 221 {
 222         struct pxa2xx_udc_mach_info *mach = the_controller->mach;
 223
 224         if (mach->udc_command)
 225                 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
 226 }
 227
 228 static void pio_irq_enable(int bEndpointAddress)
 229 {
 230         bEndpointAddress &= 0xf;
 231         if (bEndpointAddress < 8) {
 232                 clrbits_le32(&the_controller->regs->uicr0,
 233                         1 << bEndpointAddress);
 234         } else {
 235                 bEndpointAddress -= 8;
 236                 clrbits_le32(&the_controller->regs->uicr1,
 237                         1 << bEndpointAddress);
 238         }
 239 }
 240
 241 static void pio_irq_disable(int bEndpointAddress)
 242 {
 243         bEndpointAddress &= 0xf;
 244         if (bEndpointAddress < 8) {
 245                 setbits_le32(&the_controller->regs->uicr0,
 246                         1 << bEndpointAddress);
 247         } else {
 248                 bEndpointAddress -= 8;
 249                 setbits_le32(&the_controller->regs->uicr1,
 250                         1 << bEndpointAddress);
 251         }
 252 }
 253
 254 static inline void udc_set_mask_UDCCR(int mask)
 255 {
 256         /*
 257          * The UDCCR reg contains mask and interrupt status bits,
 258          * so using '|=' isn't safe as it may ack an interrupt.
 259          */
 260         const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
 261
 262         mask &= mask_bits;
 263         clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
 264 }
 265
 266 static inline void udc_clear_mask_UDCCR(int mask)
 267 {
 268         const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
 269
 270         mask = ~mask & mask_bits;
 271         clrbits_le32(&the_controller->regs->udccr, ~mask);
 272 }
 273
 274 static inline void udc_ack_int_UDCCR(int mask)
 275 {
 276         const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
 277
 278         mask &= ~mask_bits;
 279         clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
 280 }
 281
 282 /*
 283  * endpoint enable/disable
 284  *
 285  * we need to verify the descriptors used to enable endpoints.  since pxa25x
 286  * endpoint configurations are fixed, and are pretty much always enabled,
 287  * there's not a lot to manage here.
 288  *
 289  * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
 290  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 291  * for a single interface (with only the default altsetting) and for gadget
 292  * drivers that don't halt endpoints (not reset by set_interface).  that also
 293  * means that if you use ISO, you must violate the USB spec rule that all
 294  * iso endpoints must be in non-default altsettings.
 295  */
 296 static int pxa25x_ep_enable(struct usb_ep *_ep,
 297                 const struct usb_endpoint_descriptor *desc)
 298 {
 299         struct pxa25x_ep *ep;
 300         struct pxa25x_udc *dev;
 301
 302         ep = container_of(_ep, struct pxa25x_ep, ep);
 303         if (!_ep || !desc || ep->desc || _ep->name == ep0name
 304                         || desc->bDescriptorType != USB_DT_ENDPOINT
 305                         || ep->bEndpointAddress != desc->bEndpointAddress
 306                         || ep->fifo_size <
 307                            le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
 308                 printf("%s, bad ep or descriptor\n", __func__);
 309                 return -EINVAL;
 310         }
 311
 312         /* xfer types must match, except that interrupt ~= bulk */
 313         if (ep->bmAttributes != desc->bmAttributes
 314                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 315                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 316                 printf("%s, %s type mismatch\n", __func__, _ep->name);
 317                 return -EINVAL;
 318         }
 319
 320         /* hardware _could_ do smaller, but driver doesn't */
 321         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 322                         && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))
 323                                                 != BULK_FIFO_SIZE)
 324                         || !get_unaligned(&desc->wMaxPacketSize)) {
 325                 printf("%s, bad %s maxpacket\n", __func__, _ep->name);
 326                 return -ERANGE;
 327         }
 328
 329         dev = ep->dev;
 330         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 331                 printf("%s, bogus device state\n", __func__);
 332                 return -ESHUTDOWN;
 333         }
 334
 335         ep->desc = desc;
 336         ep->stopped = 0;
 337         ep->pio_irqs = 0;
 338         ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
 339
 340         /* flush fifo (mostly for OUT buffers) */
 341         pxa25x_ep_fifo_flush(_ep);
 342
 343         /* ... reset halt state too, if we could ... */
 344
 345         debug("enabled %s\n", _ep->name);
 346         return 0;
 347 }
 348
 349 static int pxa25x_ep_disable(struct usb_ep *_ep)
 350 {
 351         struct pxa25x_ep *ep;
 352         unsigned long flags;
 353
 354         ep = container_of(_ep, struct pxa25x_ep, ep);
 355         if (!_ep || !ep->desc) {
 356                 printf("%s, %s not enabled\n", __func__,
 357                         _ep ? ep->ep.name : NULL);
 358                 return -EINVAL;
 359         }
 360         local_irq_save(flags);
 361
 362         nuke(ep, -ESHUTDOWN);
 363
 364         /* flush fifo (mostly for IN buffers) */
 365         pxa25x_ep_fifo_flush(_ep);
 366
 367         ep->desc = NULL;
 368         ep->stopped = 1;
 369
 370         local_irq_restore(flags);
 371         debug("%s disabled\n", _ep->name);
 372         return 0;
 373 }
 374
 375 /*-------------------------------------------------------------------------*/
 376
 377 /*
 378  * for the pxa25x, these can just wrap kmalloc/kfree.  gadget drivers
 379  * must still pass correctly initialized endpoints, since other controller
 380  * drivers may care about how it's currently set up (dma issues etc).
 381  */
 382
 383 /*
 384  *      pxa25x_ep_alloc_request - allocate a request data structure
 385  */
 386 static struct usb_request *
 387 pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 388 {
 389         struct pxa25x_request *req;
 390
 391         req = kzalloc(sizeof(*req), gfp_flags);
 392         if (!req)
 393                 return NULL;
 394
 395         INIT_LIST_HEAD(&req->queue);
 396         return &req->req;
 397 }
 398
 399
 400 /*
 401  *      pxa25x_ep_free_request - deallocate a request data structure
 402  */
 403 static void
 404 pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
 405 {
 406         struct pxa25x_request   *req;
 407
 408         req = container_of(_req, struct pxa25x_request, req);
 409         WARN_ON(!list_empty(&req->queue));
 410         kfree(req);
 411 }
 412
 413 /*-------------------------------------------------------------------------*/
 414
 415 /*
 416  *      done - retire a request; caller blocked irqs
 417  */
 418 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
 419 {
 420         unsigned stopped = ep->stopped;
 421
 422         list_del_init(&req->queue);
 423
 424         if (likely(req->req.status == -EINPROGRESS))
 425                 req->req.status = status;
 426         else
 427                 status = req->req.status;
 428
 429         if (status && status != -ESHUTDOWN)
 430                 debug("complete %s req %p stat %d len %u/%u\n",
 431                         ep->ep.name, &req->req, status,
 432                         req->req.actual, req->req.length);
 433
 434         /* don't modify queue heads during completion callback */
 435         ep->stopped = 1;
 436         req->req.complete(&ep->ep, &req->req);
 437         ep->stopped = stopped;
 438 }
 439
 440
 441 static inline void ep0_idle(struct pxa25x_udc *dev)
 442 {
 443         dev->ep0state = EP0_IDLE;
 444 }
 445
 446 static int
 447 write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max)
 448 {
 449         u8 *buf;
 450         unsigned length, count;
 451
 452         debug("%s(): uddr %p\n", __func__, uddr);
 453
 454         buf = req->req.buf + req->req.actual;
 455         prefetch(buf);
 456
 457         /* how big will this packet be? */
 458         length = min(req->req.length - req->req.actual, max);
 459         req->req.actual += length;
 460
 461         count = length;
 462         while (likely(count--))
 463                 writeb(*buf++, uddr);
 464
 465         return length;
 466 }
 467
 468 /*
 469  * write to an IN endpoint fifo, as many packets as possible.
 470  * irqs will use this to write the rest later.
 471  * caller guarantees at least one packet buffer is ready (or a zlp).
 472  */
 473 static int
 474 write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
 475 {
 476         unsigned max;
 477
 478         max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize));
 479         do {
 480                 unsigned count;
 481                 int is_last, is_short;
 482
 483                 count = write_packet(ep->reg_uddr, req, max);
 484
 485                 /* last packet is usually short (or a zlp) */
 486                 if (unlikely(count != max))
 487                         is_last = is_short = 1;
 488                 else {
 489                         if (likely(req->req.length != req->req.actual)
 490                                         || req->req.zero)
 491                                 is_last = 0;
 492                         else
 493                                 is_last = 1;
 494                         /* interrupt/iso maxpacket may not fill the fifo */
 495                         is_short = unlikely(max < ep->fifo_size);
 496                 }
 497
 498                 debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n",
 499                         ep->ep.name, count,
 500                         is_last ? "/L" : "", is_short ? "/S" : "",
 501                         req->req.length - req->req.actual, req);
 502
 503                 /*
 504                  * let loose that packet. maybe try writing another one,
 505                  * double buffering might work.  TSP, TPC, and TFS
 506                  * bit values are the same for all normal IN endpoints.
 507                  */
 508                 writel(UDCCS_BI_TPC, ep->reg_udccs);
 509                 if (is_short)
 510                         writel(UDCCS_BI_TSP, ep->reg_udccs);
 511
 512                 /* requests complete when all IN data is in the FIFO */
 513                 if (is_last) {
 514                         done(ep, req, 0);
 515                         if (list_empty(&ep->queue))
 516                                 pio_irq_disable(ep->bEndpointAddress);
 517                         return 1;
 518                 }
 519
 520                 /*
 521                  * TODO experiment: how robust can fifo mode tweaking be?
 522                  * double buffering is off in the default fifo mode, which
 523                  * prevents TFS from being set here.
 524                  */
 525
 526         } while (readl(ep->reg_udccs) & UDCCS_BI_TFS);
 527         return 0;
 528 }
 529
 530 /*
 531  * caller asserts req->pending (ep0 irq status nyet cleared); starts
 532  * ep0 data stage.  these chips want very simple state transitions.
 533  */
 534 static inline
 535 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
 536 {
 537         writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]);
 538         writel(USIR0_IR0, &dev->regs->usir0);
 539         dev->req_pending = 0;
 540         debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n",
 541                 __func__, tag, readl(&dev->regs->udccs[0]), flags,
 542                 readl(&dev->regs->usir1), readl(&dev->regs->usir0));
 543 }
 544
 545 static int
 546 write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
 547 {
 548         unsigned count;
 549         int is_short;
 550
 551         count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE);
 552         ep->dev->stats.write.bytes += count;
 553
 554         /* last packet "must be" short (or a zlp) */
 555         is_short = (count != EP0_FIFO_SIZE);
 556
 557         debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count,
 558                 req->req.length - req->req.actual, req);
 559
 560         if (unlikely(is_short)) {
 561                 if (ep->dev->req_pending)
 562                         ep0start(ep->dev, UDCCS0_IPR, "short IN");
 563                 else
 564                         writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]);
 565
 566                 count = req->req.length;
 567                 done(ep, req, 0);
 568                 ep0_idle(ep->dev);
 569
 570                 /*
 571                  * This seems to get rid of lost status irqs in some cases:
 572                  * host responds quickly, or next request involves config
 573                  * change automagic, or should have been hidden, or ...
 574                  *
 575                  * FIXME get rid of all udelays possible...
 576                  */
 577                 if (count >= EP0_FIFO_SIZE) {
 578                         count = 100;
 579                         do {
 580                                 if ((readl(&ep->dev->regs->udccs[0]) &
 581                                      UDCCS0_OPR) != 0) {
 582                                         /* clear OPR, generate ack */
 583                                         writel(UDCCS0_OPR,
 584                                                 &ep->dev->regs->udccs[0]);
 585                                         break;
 586                                 }
 587                                 count--;
 588                                 udelay(1);
 589                         } while (count);
 590                 }
 591         } else if (ep->dev->req_pending)
 592                 ep0start(ep->dev, 0, "IN");
 593
 594         return is_short;
 595 }
 596
 597
 598 /*
 599  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 600  * transfers and put them into the request.  caller should have made
 601  * sure there's at least one packet ready.
 602  *
 603  * returns true if the request completed because of short packet or the
 604  * request buffer having filled (and maybe overran till end-of-packet).
 605  */
 606 static int
 607 read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
 608 {
 609         u32 udccs;
 610         u8 *buf;
 611         unsigned bufferspace, count, is_short;
 612
 613         for (;;) {
 614                 /*
 615                  * make sure there's a packet in the FIFO.
 616                  * UDCCS_{BO,IO}_RPC are all the same bit value.
 617                  * UDCCS_{BO,IO}_RNE are all the same bit value.
 618                  */
 619                 udccs = readl(ep->reg_udccs);
 620                 if (unlikely((udccs & UDCCS_BO_RPC) == 0))
 621                         break;
 622                 buf = req->req.buf + req->req.actual;
 623                 prefetchw(buf);
 624                 bufferspace = req->req.length - req->req.actual;
 625
 626                 /* read all bytes from this packet */
 627                 if (likely(udccs & UDCCS_BO_RNE)) {
 628                         count = 1 + (0x0ff & readl(ep->reg_ubcr));
 629                         req->req.actual += min(count, bufferspace);
 630                 } else /* zlp */
 631                         count = 0;
 632                 is_short = (count < ep->ep.maxpacket);
 633                 debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
 634                         ep->ep.name, udccs, count,
 635                         is_short ? "/S" : "",
 636                         req, req->req.actual, req->req.length);
 637                 while (likely(count-- != 0)) {
 638                         u8 byte = readb(ep->reg_uddr);
 639
 640                         if (unlikely(bufferspace == 0)) {
 641                                 /*
 642                                  * this happens when the driver's buffer
 643                                  * is smaller than what the host sent.
 644                                  * discard the extra data.
 645                                  */
 646                                 if (req->req.status != -EOVERFLOW)
 647                                         printf("%s overflow %d\n",
 648                                                 ep->ep.name, count);
 649                                 req->req.status = -EOVERFLOW;
 650                         } else {
 651                                 *buf++ = byte;
 652                                 bufferspace--;
 653                         }
 654                 }
 655                 writel(UDCCS_BO_RPC, ep->reg_udccs);
 656                 /* RPC/RSP/RNE could now reflect the other packet buffer */
 657
 658                 /* iso is one request per packet */
 659                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 660                         if (udccs & UDCCS_IO_ROF)
 661                                 req->req.status = -EHOSTUNREACH;
 662                         /* more like "is_done" */
 663                         is_short = 1;
 664                 }
 665
 666                 /* completion */
 667                 if (is_short || req->req.actual == req->req.length) {
 668                         done(ep, req, 0);
 669                         if (list_empty(&ep->queue))
 670                                 pio_irq_disable(ep->bEndpointAddress);
 671                         return 1;
 672                 }
 673
 674                 /* finished that packet.  the next one may be waiting... */
 675         }
 676         return 0;
 677 }
 678
 679 /*
 680  * special ep0 version of the above.  no UBCR0 or double buffering; status
 681  * handshaking is magic.  most device protocols don't need control-OUT.
 682  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 683  * protocols do use them.
 684  */
 685 static int
 686 read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
 687 {
 688         u8 *buf, byte;
 689         unsigned bufferspace;
 690
 691         buf = req->req.buf + req->req.actual;
 692         bufferspace = req->req.length - req->req.actual;
 693
 694         while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) {
 695                 byte = (u8)readb(&ep->dev->regs->uddr0);
 696
 697                 if (unlikely(bufferspace == 0)) {
 698                         /*
 699                          * this happens when the driver's buffer
 700                          * is smaller than what the host sent.
 701                          * discard the extra data.
 702                          */
 703                         if (req->req.status != -EOVERFLOW)
 704                                 printf("%s overflow\n", ep->ep.name);
 705                         req->req.status = -EOVERFLOW;
 706                 } else {
 707                         *buf++ = byte;
 708                         req->req.actual++;
 709                         bufferspace--;
 710                 }
 711         }
 712
 713         writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]);
 714
 715         /* completion */
 716         if (req->req.actual >= req->req.length)
 717                 return 1;
 718
 719         /* finished that packet.  the next one may be waiting... */
 720         return 0;
 721 }
 722
 723 /*-------------------------------------------------------------------------*/
 724
 725 static int
 726 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 727 {
 728         struct pxa25x_request *req;
 729         struct pxa25x_ep *ep;
 730         struct pxa25x_udc *dev;
 731         unsigned long flags;
 732
 733         req = container_of(_req, struct pxa25x_request, req);
 734         if (unlikely(!_req || !_req->complete || !_req->buf
 735                         || !list_empty(&req->queue))) {
 736                 printf("%s, bad params\n", __func__);
 737                 return -EINVAL;
 738         }
 739
 740         ep = container_of(_ep, struct pxa25x_ep, ep);
 741         if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 742                 printf("%s, bad ep\n", __func__);
 743                 return -EINVAL;
 744         }
 745
 746         dev = ep->dev;
 747         if (unlikely(!dev->driver
 748                         || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 749                 printf("%s, bogus device state\n", __func__);
 750                 return -ESHUTDOWN;
 751         }
 752
 753         /*
 754          * iso is always one packet per request, that's the only way
 755          * we can report per-packet status.  that also helps with dma.
 756          */
 757         if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 758                         && req->req.length >
 759                         le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize))))
 760                 return -EMSGSIZE;
 761
 762         debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
 763                 _ep->name, _req, _req->length, _req->buf);
 764
 765         local_irq_save(flags);
 766
 767         _req->status = -EINPROGRESS;
 768         _req->actual = 0;
 769
 770         /* kickstart this i/o queue? */
 771         if (list_empty(&ep->queue) && !ep->stopped) {
 772                 if (ep->desc == NULL/* ep0 */) {
 773                         unsigned length = _req->length;
 774
 775                         switch (dev->ep0state) {
 776                         case EP0_IN_DATA_PHASE:
 777                                 dev->stats.write.ops++;
 778                                 if (write_ep0_fifo(ep, req))
 779                                         req = NULL;
 780                                 break;
 781
 782                         case EP0_OUT_DATA_PHASE:
 783                                 dev->stats.read.ops++;
 784                                 /* messy ... */
 785                                 if (dev->req_config) {
 786                                         debug("ep0 config ack%s\n",
 787                                                 dev->has_cfr ?  "" : " raced");
 788                                         if (dev->has_cfr)
 789                                                 writel(UDCCFR_AREN|UDCCFR_ACM
 790                                                         |UDCCFR_MB1,
 791                                                         &ep->dev->regs->udccfr);
 792                                         done(ep, req, 0);
 793                                         dev->ep0state = EP0_END_XFER;
 794                                         local_irq_restore(flags);
 795                                         return 0;
 796                                 }
 797                                 if (dev->req_pending)
 798                                         ep0start(dev, UDCCS0_IPR, "OUT");
 799                                 if (length == 0 ||
 800                                                 ((readl(
 801                                                 &ep->dev->regs->udccs[0])
 802                                                 & UDCCS0_RNE) != 0
 803                                                 && read_ep0_fifo(ep, req))) {
 804                                         ep0_idle(dev);
 805                                         done(ep, req, 0);
 806                                         req = NULL;
 807                                 }
 808                                 break;
 809
 810                         default:
 811                                 printf("ep0 i/o, odd state %d\n",
 812                                         dev->ep0state);
 813                                 local_irq_restore(flags);
 814                                 return -EL2HLT;
 815                         }
 816                 /* can the FIFO can satisfy the request immediately? */
 817                 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
 818                         if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0
 819                                         && write_fifo(ep, req))
 820                                 req = NULL;
 821                 } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0
 822                                 && read_fifo(ep, req)) {
 823                         req = NULL;
 824                 }
 825
 826                 if (likely(req && ep->desc))
 827                         pio_irq_enable(ep->bEndpointAddress);
 828         }
 829
 830         /* pio or dma irq handler advances the queue. */
 831         if (likely(req != NULL))
 832                 list_add_tail(&req->queue, &ep->queue);
 833         local_irq_restore(flags);
 834
 835         return 0;
 836 }
 837
 838
 839 /*
 840  *      nuke - dequeue ALL requests
 841  */
 842 static void nuke(struct pxa25x_ep *ep, int status)
 843 {
 844         struct pxa25x_request *req;
 845
 846         /* called with irqs blocked */
 847         while (!list_empty(&ep->queue)) {
 848                 req = list_entry(ep->queue.next,
 849                                 struct pxa25x_request,
 850                                 queue);
 851                 done(ep, req, status);
 852         }
 853         if (ep->desc)
 854                 pio_irq_disable(ep->bEndpointAddress);
 855 }
 856
 857
 858 /* dequeue JUST ONE request */
 859 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 860 {
 861         struct pxa25x_ep *ep;
 862         struct pxa25x_request *req;
 863         unsigned long flags;
 864
 865         ep = container_of(_ep, struct pxa25x_ep, ep);
 866         if (!_ep || ep->ep.name == ep0name)
 867                 return -EINVAL;
 868
 869         local_irq_save(flags);
 870
 871         /* make sure it's actually queued on this endpoint */
 872         list_for_each_entry(req, &ep->queue, queue) {
 873                 if (&req->req == _req)
 874                         break;
 875         }
 876         if (&req->req != _req) {
 877                 local_irq_restore(flags);
 878                 return -EINVAL;
 879         }
 880
 881         done(ep, req, -ECONNRESET);
 882
 883         local_irq_restore(flags);
 884         return 0;
 885 }
 886
 887 /*-------------------------------------------------------------------------*/
 888
 889 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
 890 {
 891         struct pxa25x_ep *ep;
 892         unsigned long flags;
 893
 894         ep = container_of(_ep, struct pxa25x_ep, ep);
 895         if (unlikely(!_ep
 896                         || (!ep->desc && ep->ep.name != ep0name))
 897                         || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 898                 printf("%s, bad ep\n", __func__);
 899                 return -EINVAL;
 900         }
 901         if (value == 0) {
 902                 /*
 903                  * this path (reset toggle+halt) is needed to implement
 904                  * SET_INTERFACE on normal hardware.  but it can't be
 905                  * done from software on the PXA UDC, and the hardware
 906                  * forgets to do it as part of SET_INTERFACE automagic.
 907                  */
 908                 printf("only host can clear %s halt\n", _ep->name);
 909                 return -EROFS;
 910         }
 911
 912         local_irq_save(flags);
 913
 914         if ((ep->bEndpointAddress & USB_DIR_IN) != 0
 915                         && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0
 916                            || !list_empty(&ep->queue))) {
 917                 local_irq_restore(flags);
 918                 return -EAGAIN;
 919         }
 920
 921         /* FST bit is the same for control, bulk in, bulk out, interrupt in */
 922         writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs);
 923
 924         /* ep0 needs special care */
 925         if (!ep->desc) {
 926                 start_watchdog(ep->dev);
 927                 ep->dev->req_pending = 0;
 928                 ep->dev->ep0state = EP0_STALL;
 929
 930         /* and bulk/intr endpoints like dropping stalls too */
 931         } else {
 932                 unsigned i;
 933                 for (i = 0; i < 1000; i += 20) {
 934                         if (readl(ep->reg_udccs) & UDCCS_BI_SST)
 935                                 break;
 936                         udelay(20);
 937                 }
 938         }
 939         local_irq_restore(flags);
 940
 941         debug("%s halt\n", _ep->name);
 942         return 0;
 943 }
 944
 945 static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
 946 {
 947         struct pxa25x_ep        *ep;
 948
 949         ep = container_of(_ep, struct pxa25x_ep, ep);
 950         if (!_ep) {
 951                 printf("%s, bad ep\n", __func__);
 952                 return -ENODEV;
 953         }
 954         /* pxa can't report unclaimed bytes from IN fifos */
 955         if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
 956                 return -EOPNOTSUPP;
 957         if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
 958                         || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0)
 959                 return 0;
 960         else
 961                 return (readl(ep->reg_ubcr) & 0xfff) + 1;
 962 }
 963
 964 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
 965 {
 966         struct pxa25x_ep        *ep;
 967
 968         ep = container_of(_ep, struct pxa25x_ep, ep);
 969         if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
 970                 printf("%s, bad ep\n", __func__);
 971                 return;
 972         }
 973
 974         /* toggle and halt bits stay unchanged */
 975
 976         /* for OUT, just read and discard the FIFO contents. */
 977         if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
 978                 while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0)
 979                         (void)readb(ep->reg_uddr);
 980                 return;
 981         }
 982
 983         /* most IN status is the same, but ISO can't stall */
 984         writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
 985                 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
 986                         ? 0 : UDCCS_BI_SST), ep->reg_udccs);
 987 }
 988
 989
 990 static struct usb_ep_ops pxa25x_ep_ops = {
 991         .enable         = pxa25x_ep_enable,
 992         .disable        = pxa25x_ep_disable,
 993
 994         .alloc_request  = pxa25x_ep_alloc_request,
 995         .free_request   = pxa25x_ep_free_request,
 996
 997         .queue          = pxa25x_ep_queue,
 998         .dequeue        = pxa25x_ep_dequeue,
 999
1000         .set_halt       = pxa25x_ep_set_halt,
1001         .fifo_status    = pxa25x_ep_fifo_status,
1002         .fifo_flush     = pxa25x_ep_fifo_flush,
1003 };
1004
1005
1006 /* ---------------------------------------------------------------------------
1007  *      device-scoped parts of the api to the usb controller hardware
1008  * ---------------------------------------------------------------------------
1009  */
1010
1011 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
1012 {
1013         return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) |
1014                 (readl(&the_controller->regs->ufnrl) & 0xff);
1015 }
1016
1017 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
1018 {
1019         /* host may not have enabled remote wakeup */
1020         if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0)
1021                 return -EHOSTUNREACH;
1022         udc_set_mask_UDCCR(UDCCR_RSM);
1023         return 0;
1024 }
1025
1026 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
1027 static void udc_enable(struct pxa25x_udc *);
1028 static void udc_disable(struct pxa25x_udc *);
1029
1030 /*
1031  * We disable the UDC -- and its 48 MHz clock -- whenever it's not
1032  * in active use.
1033  */
1034 static int pullup(struct pxa25x_udc *udc)
1035 {
1036         if (udc->pullup)
1037                 pullup_on();
1038         else
1039                 pullup_off();
1040
1041
1042         int is_active = udc->pullup;
1043         if (is_active) {
1044                 if (!udc->active) {
1045                         udc->active = 1;
1046                         udc_enable(udc);
1047                 }
1048         } else {
1049                 if (udc->active) {
1050                         if (udc->gadget.speed != USB_SPEED_UNKNOWN)
1051                                 stop_activity(udc, udc->driver);
1052                         udc_disable(udc);
1053                         udc->active = 0;
1054                 }
1055
1056         }
1057         return 0;
1058 }
1059
1060 /* VBUS reporting logically comes from a transceiver */
1061 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1062 {
1063         struct pxa25x_udc *udc;
1064
1065         udc = container_of(_gadget, struct pxa25x_udc, gadget);
1066         printf("vbus %s\n", is_active ? "supplied" : "inactive");
1067         pullup(udc);
1068         return 0;
1069 }
1070
1071 /* drivers may have software control over D+ pullup */
1072 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
1073 {
1074         struct pxa25x_udc       *udc;
1075
1076         udc = container_of(_gadget, struct pxa25x_udc, gadget);
1077
1078         /* not all boards support pullup control */
1079         if (!udc->mach->udc_command)
1080                 return -EOPNOTSUPP;
1081
1082         udc->pullup = (is_active != 0);
1083         pullup(udc);
1084         return 0;
1085 }
1086
1087 /*
1088  * boards may consume current from VBUS, up to 100-500mA based on config.
1089  * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
1090  * violate USB specs.
1091  */
1092 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1093 {
1094         return -EOPNOTSUPP;
1095 }
1096
1097 static const struct usb_gadget_ops pxa25x_udc_ops = {
1098         .get_frame      = pxa25x_udc_get_frame,
1099         .wakeup         = pxa25x_udc_wakeup,
1100         .vbus_session   = pxa25x_udc_vbus_session,
1101         .pullup         = pxa25x_udc_pullup,
1102         .vbus_draw      = pxa25x_udc_vbus_draw,
1103 };
1104
1105 /*-------------------------------------------------------------------------*/
1106
1107 /*
1108  *      udc_disable - disable USB device controller
1109  */
1110 static void udc_disable(struct pxa25x_udc *dev)
1111 {
1112         /* block all irqs */
1113         udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1114         writel(0xff, &dev->regs->uicr0);
1115         writel(0xff, &dev->regs->uicr1);
1116         writel(UFNRH_SIM, &dev->regs->ufnrh);
1117
1118         /* if hardware supports it, disconnect from usb */
1119         pullup_off();
1120
1121         udc_clear_mask_UDCCR(UDCCR_UDE);
1122
1123         ep0_idle(dev);
1124         dev->gadget.speed = USB_SPEED_UNKNOWN;
1125 }
1126
1127 /*
1128  *      udc_reinit - initialize software state
1129  */
1130 static void udc_reinit(struct pxa25x_udc *dev)
1131 {
1132         u32 i;
1133
1134         /* device/ep0 records init */
1135         INIT_LIST_HEAD(&dev->gadget.ep_list);
1136         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1137         dev->ep0state = EP0_IDLE;
1138
1139         /* basic endpoint records init */
1140         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1141                 struct pxa25x_ep *ep = &dev->ep[i];
1142
1143                 if (i != 0)
1144                         list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
1145
1146                 ep->desc = NULL;
1147                 ep->stopped = 0;
1148                 INIT_LIST_HEAD(&ep->queue);
1149                 ep->pio_irqs = 0;
1150         }
1151
1152         /* the rest was statically initialized, and is read-only */
1153 }
1154
1155 /*
1156  * until it's enabled, this UDC should be completely invisible
1157  * to any USB host.
1158  */
1159 static void udc_enable(struct pxa25x_udc *dev)
1160 {
1161         debug("udc: enabling udc\n");
1162
1163         udc_clear_mask_UDCCR(UDCCR_UDE);
1164
1165         /*
1166          * Try to clear these bits before we enable the udc.
1167          * Do not touch reset ack bit, we would take care of it in
1168          * interrupt handle routine
1169          */
1170         udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR);
1171
1172         ep0_idle(dev);
1173         dev->gadget.speed = USB_SPEED_UNKNOWN;
1174         dev->stats.irqs = 0;
1175
1176         /*
1177          * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1178          * - enable UDC
1179          * - if RESET is already in progress, ack interrupt
1180          * - unmask reset interrupt
1181          */
1182         udc_set_mask_UDCCR(UDCCR_UDE);
1183         if (!(readl(&dev->regs->udccr) & UDCCR_UDA))
1184                 udc_ack_int_UDCCR(UDCCR_RSTIR);
1185
1186         if (dev->has_cfr /* UDC_RES2 is defined */) {
1187                 /*
1188                  * pxa255 (a0+) can avoid a set_config race that could
1189                  * prevent gadget drivers from configuring correctly
1190                  */
1191                 writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr);
1192         }
1193
1194         /* enable suspend/resume and reset irqs */
1195         udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1196
1197         /* enable ep0 irqs */
1198         clrbits_le32(&dev->regs->uicr0, UICR0_IM0);
1199
1200         /* if hardware supports it, pullup D+ and wait for reset */
1201         pullup_on();
1202 }
1203
1204 static inline void clear_ep_state(struct pxa25x_udc *dev)
1205 {
1206         unsigned i;
1207
1208         /*
1209          * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1210          * fifos, and pending transactions mustn't be continued in any case.
1211          */
1212         for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1213                 nuke(&dev->ep[i], -ECONNABORTED);
1214 }
1215
1216 static void handle_ep0(struct pxa25x_udc *dev)
1217 {
1218         u32 udccs0 = readl(&dev->regs->udccs[0]);
1219         struct pxa25x_ep *ep = &dev->ep[0];
1220         struct pxa25x_request *req;
1221         union {
1222                 struct usb_ctrlrequest  r;
1223                 u8                      raw[8];
1224                 u32                     word[2];
1225         } u;
1226
1227         if (list_empty(&ep->queue))
1228                 req = NULL;
1229         else
1230                 req = list_entry(ep->queue.next, struct pxa25x_request, queue);
1231
1232         /* clear stall status */
1233         if (udccs0 & UDCCS0_SST) {
1234                 nuke(ep, -EPIPE);
1235                 writel(UDCCS0_SST, &dev->regs->udccs[0]);
1236                 stop_watchdog(dev);
1237                 ep0_idle(dev);
1238         }
1239
1240         /* previous request unfinished?  non-error iff back-to-back ... */
1241         if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1242                 nuke(ep, 0);
1243                 stop_watchdog(dev);
1244                 ep0_idle(dev);
1245         }
1246
1247         switch (dev->ep0state) {
1248         case EP0_IDLE:
1249                 /* late-breaking status? */
1250                 udccs0 = readl(&dev->regs->udccs[0]);
1251
1252                 /* start control request? */
1253                 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1254                                 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1255                         int i;
1256
1257                         nuke(ep, -EPROTO);
1258
1259                         /* read SETUP packet */
1260                         for (i = 0; i < 8; i++) {
1261                                 if (unlikely(!(readl(&dev->regs->udccs[0]) &
1262                                                 UDCCS0_RNE))) {
1263 bad_setup:
1264                                         debug("SETUP %d!\n", i);
1265                                         goto stall;
1266                                 }
1267                                 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1268                         }
1269                         if (unlikely((readl(&dev->regs->udccs[0]) &
1270                                         UDCCS0_RNE) != 0))
1271                                 goto bad_setup;
1272
1273 got_setup:
1274                         debug("SETUP %02x.%02x v%04x i%04x l%04x\n",
1275                                 u.r.bRequestType, u.r.bRequest,
1276                                 le16_to_cpu(u.r.wValue),
1277                                 le16_to_cpu(u.r.wIndex),
1278                                 le16_to_cpu(u.r.wLength));
1279
1280                         /* cope with automagic for some standard requests. */
1281                         dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1282                                                 == USB_TYPE_STANDARD;
1283                         dev->req_config = 0;
1284                         dev->req_pending = 1;
1285                         switch (u.r.bRequest) {
1286                         /* hardware restricts gadget drivers here! */
1287                         case USB_REQ_SET_CONFIGURATION:
1288                                 debug("GOT SET_CONFIGURATION\n");
1289                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1290                                         /*
1291                                          * reflect hardware's automagic
1292                                          * up to the gadget driver.
1293                                          */
1294 config_change:
1295                                         dev->req_config = 1;
1296                                         clear_ep_state(dev);
1297                                         /*
1298                                          * if !has_cfr, there's no synch
1299                                          * else use AREN (later) not SA|OPR
1300                                          * USIR0_IR0 acts edge sensitive
1301                                          */
1302                                 }
1303                                 break;
1304                         /* ... and here, even more ... */
1305                         case USB_REQ_SET_INTERFACE:
1306                                 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1307                                         /*
1308                                          * udc hardware is broken by design:
1309                                          *  - altsetting may only be zero;
1310                                          *  - hw resets all interfaces' eps;
1311                                          *  - ep reset doesn't include halt(?).
1312                                          */
1313                                         printf("broken set_interface (%d/%d)\n",
1314                                                 le16_to_cpu(u.r.wIndex),
1315                                                 le16_to_cpu(u.r.wValue));
1316                                         goto config_change;
1317                                 }
1318                                 break;
1319                         /* hardware was supposed to hide this */
1320                         case USB_REQ_SET_ADDRESS:
1321                                 debug("GOT SET ADDRESS\n");
1322                                 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1323                                         ep0start(dev, 0, "address");
1324                                         return;
1325                                 }
1326                                 break;
1327                         }
1328
1329                         if (u.r.bRequestType & USB_DIR_IN)
1330                                 dev->ep0state = EP0_IN_DATA_PHASE;
1331                         else
1332                                 dev->ep0state = EP0_OUT_DATA_PHASE;
1333
1334                         i = dev->driver->setup(&dev->gadget, &u.r);
1335                         if (i < 0) {
1336                                 /* hardware automagic preventing STALL... */
1337                                 if (dev->req_config) {
1338                                         /*
1339                                          * hardware sometimes neglects to tell
1340                                          * tell us about config change events,
1341                                          * so later ones may fail...
1342                                          */
1343                                         printf("config change %02x fail %d?\n",
1344                                                 u.r.bRequest, i);
1345                                         return;
1346                                         /*
1347                                          * TODO experiment:  if has_cfr,
1348                                          * hardware didn't ACK; maybe we
1349                                          * could actually STALL!
1350                                          */
1351                                 }
1352                                 if (0) {
1353 stall:
1354                                         /* uninitialized when goto stall */
1355                                         i = 0;
1356                                 }
1357                                 debug("protocol STALL, "
1358                                         "%02x err %d\n",
1359                                         readl(&dev->regs->udccs[0]), i);
1360
1361                                 /*
1362                                  * the watchdog timer helps deal with cases
1363                                  * where udc seems to clear FST wrongly, and
1364                                  * then NAKs instead of STALLing.
1365                                  */
1366                                 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1367                                 start_watchdog(dev);
1368                                 dev->ep0state = EP0_STALL;
1369
1370                         /* deferred i/o == no response yet */
1371                         } else if (dev->req_pending) {
1372                                 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1373                                                 || dev->req_std || u.r.wLength))
1374                                         ep0start(dev, 0, "defer");
1375                                 else
1376                                         ep0start(dev, UDCCS0_IPR, "defer/IPR");
1377                         }
1378
1379                         /* expect at least one data or status stage irq */
1380                         return;
1381
1382                 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1383                                 == (UDCCS0_OPR|UDCCS0_SA))) {
1384                         unsigned i;
1385
1386                         /*
1387                          * pxa210/250 erratum 131 for B0/B1 says RNE lies.
1388                          * still observed on a pxa255 a0.
1389                          */
1390                         debug("e131\n");
1391                         nuke(ep, -EPROTO);
1392
1393                         /* read SETUP data, but don't trust it too much */
1394                         for (i = 0; i < 8; i++)
1395                                 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1396                         if ((u.r.bRequestType & USB_RECIP_MASK)
1397                                         > USB_RECIP_OTHER)
1398                                 goto stall;
1399                         if (u.word[0] == 0 && u.word[1] == 0)
1400                                 goto stall;
1401                         goto got_setup;
1402                 } else {
1403                         /*
1404                          * some random early IRQ:
1405                          * - we acked FST
1406                          * - IPR cleared
1407                          * - OPR got set, without SA (likely status stage)
1408                          */
1409                         debug("random IRQ %X %X\n", udccs0,
1410                                 readl(&dev->regs->udccs[0]));
1411                         writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR),
1412                                 &dev->regs->udccs[0]);
1413                 }
1414                 break;
1415         case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1416                 if (udccs0 & UDCCS0_OPR) {
1417                         debug("ep0in premature status\n");
1418                         if (req)
1419                                 done(ep, req, 0);
1420                         ep0_idle(dev);
1421                 } else /* irq was IPR clearing */ {
1422                         if (req) {
1423                                 debug("next ep0 in packet\n");
1424                                 /* this IN packet might finish the request */
1425                                 (void) write_ep0_fifo(ep, req);
1426                         } /* else IN token before response was written */
1427                 }
1428                 break;
1429         case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1430                 if (udccs0 & UDCCS0_OPR) {
1431                         if (req) {
1432                                 /* this OUT packet might finish the request */
1433                                 if (read_ep0_fifo(ep, req))
1434                                         done(ep, req, 0);
1435                                 /* else more OUT packets expected */
1436                         } /* else OUT token before read was issued */
1437                 } else /* irq was IPR clearing */ {
1438                         debug("ep0out premature status\n");
1439                         if (req)
1440                                 done(ep, req, 0);
1441                         ep0_idle(dev);
1442                 }
1443                 break;
1444         case EP0_END_XFER:
1445                 if (req)
1446                         done(ep, req, 0);
1447                 /*
1448                  * ack control-IN status (maybe in-zlp was skipped)
1449                  * also appears after some config change events.
1450                  */
1451                 if (udccs0 & UDCCS0_OPR)
1452                         writel(UDCCS0_OPR, &dev->regs->udccs[0]);
1453                 ep0_idle(dev);
1454                 break;
1455         case EP0_STALL:
1456                 writel(UDCCS0_FST, &dev->regs->udccs[0]);
1457                 break;
1458         }
1459
1460         writel(USIR0_IR0, &dev->regs->usir0);
1461 }
1462
1463 static void handle_ep(struct pxa25x_ep *ep)
1464 {
1465         struct pxa25x_request   *req;
1466         int                     is_in = ep->bEndpointAddress & USB_DIR_IN;
1467         int                     completed;
1468         u32                     udccs, tmp;
1469
1470         do {
1471                 completed = 0;
1472                 if (likely(!list_empty(&ep->queue)))
1473                         req = list_entry(ep->queue.next,
1474                                         struct pxa25x_request, queue);
1475                 else
1476                         req = NULL;
1477
1478                 /* TODO check FST handling */
1479
1480                 udccs = readl(ep->reg_udccs);
1481                 if (unlikely(is_in)) {  /* irq from TPC, SST, or (ISO) TUR */
1482                         tmp = UDCCS_BI_TUR;
1483                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1484                                 tmp |= UDCCS_BI_SST;
1485                         tmp &= udccs;
1486                         if (likely(tmp))
1487                                 writel(tmp, ep->reg_udccs);
1488                         if (req && likely((udccs & UDCCS_BI_TFS) != 0))
1489                                 completed = write_fifo(ep, req);
1490
1491                 } else {        /* irq from RPC (or for ISO, ROF) */
1492                         if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1493                                 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1494                         else
1495                                 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1496                         tmp &= udccs;
1497                         if (likely(tmp))
1498                                 writel(tmp, ep->reg_udccs);
1499
1500                         /* fifos can hold packets, ready for reading... */
1501                         if (likely(req))
1502                                 completed = read_fifo(ep, req);
1503                         else
1504                                 pio_irq_disable(ep->bEndpointAddress);
1505                 }
1506                 ep->pio_irqs++;
1507         } while (completed);
1508 }
1509
1510 /*
1511  *      pxa25x_udc_irq - interrupt handler
1512  *
1513  * avoid delays in ep0 processing. the control handshaking isn't always
1514  * under software control (pxa250c0 and the pxa255 are better), and delays
1515  * could cause usb protocol errors.
1516  */
1517 static struct pxa25x_udc memory;
1518 static int
1519 pxa25x_udc_irq(void)
1520 {
1521         struct pxa25x_udc *dev = &memory;
1522         int handled;
1523
1524         test_watchdog(dev);
1525
1526         dev->stats.irqs++;
1527         do {
1528                 u32 udccr = readl(&dev->regs->udccr);
1529
1530                 handled = 0;
1531
1532                 /* SUSpend Interrupt Request */
1533                 if (unlikely(udccr & UDCCR_SUSIR)) {
1534                         udc_ack_int_UDCCR(UDCCR_SUSIR);
1535                         handled = 1;
1536                         debug("USB suspend\n");
1537
1538                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
1539                                         && dev->driver
1540                                         && dev->driver->suspend)
1541                                 dev->driver->suspend(&dev->gadget);
1542                         ep0_idle(dev);
1543                 }
1544
1545                 /* RESume Interrupt Request */
1546                 if (unlikely(udccr & UDCCR_RESIR)) {
1547                         udc_ack_int_UDCCR(UDCCR_RESIR);
1548                         handled = 1;
1549                         debug("USB resume\n");
1550
1551                         if (dev->gadget.speed != USB_SPEED_UNKNOWN
1552                                         && dev->driver
1553                                         && dev->driver->resume)
1554                                 dev->driver->resume(&dev->gadget);
1555                 }
1556
1557                 /* ReSeT Interrupt Request - USB reset */
1558                 if (unlikely(udccr & UDCCR_RSTIR)) {
1559                         udc_ack_int_UDCCR(UDCCR_RSTIR);
1560                         handled = 1;
1561
1562                         if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) {
1563                                 debug("USB reset start\n");
1564
1565                                 /*
1566                                  * reset driver and endpoints,
1567                                  * in case that's not yet done
1568                                  */
1569                                 stop_activity(dev, dev->driver);
1570
1571                         } else {
1572                                 debug("USB reset end\n");
1573                                 dev->gadget.speed = USB_SPEED_FULL;
1574                                 memset(&dev->stats, 0, sizeof dev->stats);
1575                                 /* driver and endpoints are still reset */
1576                         }
1577
1578                 } else {
1579                         u32 uicr0 = readl(&dev->regs->uicr0);
1580                         u32 uicr1 = readl(&dev->regs->uicr1);
1581                         u32 usir0 = readl(&dev->regs->usir0);
1582                         u32 usir1 = readl(&dev->regs->usir1);
1583
1584                         usir0 = usir0 & ~uicr0;
1585                         usir1 = usir1 & ~uicr1;
1586                         int i;
1587
1588                         if (unlikely(!usir0 && !usir1))
1589                                 continue;
1590
1591                         debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0);
1592
1593                         /* control traffic */
1594                         if (usir0 & USIR0_IR0) {
1595                                 dev->ep[0].pio_irqs++;
1596                                 handle_ep0(dev);
1597                                 handled = 1;
1598                         }
1599
1600                         /* endpoint data transfers */
1601                         for (i = 0; i < 8; i++) {
1602                                 u32     tmp = 1 << i;
1603
1604                                 if (i && (usir0 & tmp)) {
1605                                         handle_ep(&dev->ep[i]);
1606                                         setbits_le32(&dev->regs->usir0, tmp);
1607                                         handled = 1;
1608                                 }
1609 #ifndef CONFIG_USB_PXA25X_SMALL
1610                                 if (usir1 & tmp) {
1611                                         handle_ep(&dev->ep[i+8]);
1612                                         setbits_le32(&dev->regs->usir1, tmp);
1613                                         handled = 1;
1614                                 }
1615 #endif
1616                         }
1617                 }
1618
1619                 /* we could also ask for 1 msec SOF (SIR) interrupts */
1620
1621         } while (handled);
1622         return IRQ_HANDLED;
1623 }
1624
1625 /*-------------------------------------------------------------------------*/
1626
1627 /*
1628  * this uses load-time allocation and initialization (instead of
1629  * doing it at run-time) to save code, eliminate fault paths, and
1630  * be more obviously correct.
1631  */
1632 static struct pxa25x_udc memory = {
1633         .regs = UDC_REGS,
1634
1635         .gadget = {
1636                 .ops            = &pxa25x_udc_ops,
1637                 .ep0            = &memory.ep[0].ep,
1638                 .name           = driver_name,
1639         },
1640
1641         /* control endpoint */
1642         .ep[0] = {
1643                 .ep = {
1644                         .name           = ep0name,
1645                         .ops            = &pxa25x_ep_ops,
1646                         .maxpacket      = EP0_FIFO_SIZE,
1647                 },
1648                 .dev            = &memory,
1649                 .reg_udccs      = &UDC_REGS->udccs[0],
1650                 .reg_uddr       = &UDC_REGS->uddr0,
1651         },
1652
1653         /* first group of endpoints */
1654         .ep[1] = {
1655                 .ep = {
1656                         .name           = "ep1in-bulk",
1657                         .ops            = &pxa25x_ep_ops,
1658                         .maxpacket      = BULK_FIFO_SIZE,
1659                 },
1660                 .dev            = &memory,
1661                 .fifo_size      = BULK_FIFO_SIZE,
1662                 .bEndpointAddress = USB_DIR_IN | 1,
1663                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1664                 .reg_udccs      = &UDC_REGS->udccs[1],
1665                 .reg_uddr       = &UDC_REGS->uddr1,
1666         },
1667         .ep[2] = {
1668                 .ep = {
1669                         .name           = "ep2out-bulk",
1670                         .ops            = &pxa25x_ep_ops,
1671                         .maxpacket      = BULK_FIFO_SIZE,
1672                 },
1673                 .dev            = &memory,
1674                 .fifo_size      = BULK_FIFO_SIZE,
1675                 .bEndpointAddress = 2,
1676                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1677                 .reg_udccs      = &UDC_REGS->udccs[2],
1678                 .reg_ubcr       = &UDC_REGS->ubcr2,
1679                 .reg_uddr       = &UDC_REGS->uddr2,
1680         },
1681 #ifndef CONFIG_USB_PXA25X_SMALL
1682         .ep[3] = {
1683                 .ep = {
1684                         .name           = "ep3in-iso",
1685                         .ops            = &pxa25x_ep_ops,
1686                         .maxpacket      = ISO_FIFO_SIZE,
1687                 },
1688                 .dev            = &memory,
1689                 .fifo_size      = ISO_FIFO_SIZE,
1690                 .bEndpointAddress = USB_DIR_IN | 3,
1691                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1692                 .reg_udccs      = &UDC_REGS->udccs[3],
1693                 .reg_uddr       = &UDC_REGS->uddr3,
1694         },
1695         .ep[4] = {
1696                 .ep = {
1697                         .name           = "ep4out-iso",
1698                         .ops            = &pxa25x_ep_ops,
1699                         .maxpacket      = ISO_FIFO_SIZE,
1700                 },
1701                 .dev            = &memory,
1702                 .fifo_size      = ISO_FIFO_SIZE,
1703                 .bEndpointAddress = 4,
1704                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1705                 .reg_udccs      = &UDC_REGS->udccs[4],
1706                 .reg_ubcr       = &UDC_REGS->ubcr4,
1707                 .reg_uddr       = &UDC_REGS->uddr4,
1708         },
1709         .ep[5] = {
1710                 .ep = {
1711                         .name           = "ep5in-int",
1712                         .ops            = &pxa25x_ep_ops,
1713                         .maxpacket      = INT_FIFO_SIZE,
1714                 },
1715                 .dev            = &memory,
1716                 .fifo_size      = INT_FIFO_SIZE,
1717                 .bEndpointAddress = USB_DIR_IN | 5,
1718                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
1719                 .reg_udccs      = &UDC_REGS->udccs[5],
1720                 .reg_uddr       = &UDC_REGS->uddr5,
1721         },
1722
1723         /* second group of endpoints */
1724         .ep[6] = {
1725                 .ep = {
1726                         .name           = "ep6in-bulk",
1727                         .ops            = &pxa25x_ep_ops,
1728                         .maxpacket      = BULK_FIFO_SIZE,
1729                 },
1730                 .dev            = &memory,
1731                 .fifo_size      = BULK_FIFO_SIZE,
1732                 .bEndpointAddress = USB_DIR_IN | 6,
1733                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1734                 .reg_udccs      = &UDC_REGS->udccs[6],
1735                 .reg_uddr       = &UDC_REGS->uddr6,
1736         },
1737         .ep[7] = {
1738                 .ep = {
1739                         .name           = "ep7out-bulk",
1740                         .ops            = &pxa25x_ep_ops,
1741                         .maxpacket      = BULK_FIFO_SIZE,
1742                 },
1743                 .dev            = &memory,
1744                 .fifo_size      = BULK_FIFO_SIZE,
1745                 .bEndpointAddress = 7,
1746                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1747                 .reg_udccs      = &UDC_REGS->udccs[7],
1748                 .reg_ubcr       = &UDC_REGS->ubcr7,
1749                 .reg_uddr       = &UDC_REGS->uddr7,
1750         },
1751         .ep[8] = {
1752                 .ep = {
1753                         .name           = "ep8in-iso",
1754                         .ops            = &pxa25x_ep_ops,
1755                         .maxpacket      = ISO_FIFO_SIZE,
1756                 },
1757                 .dev            = &memory,
1758                 .fifo_size      = ISO_FIFO_SIZE,
1759                 .bEndpointAddress = USB_DIR_IN | 8,
1760                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1761                 .reg_udccs      = &UDC_REGS->udccs[8],
1762                 .reg_uddr       = &UDC_REGS->uddr8,
1763         },
1764         .ep[9] = {
1765                 .ep = {
1766                         .name           = "ep9out-iso",
1767                         .ops            = &pxa25x_ep_ops,
1768                         .maxpacket      = ISO_FIFO_SIZE,
1769                 },
1770                 .dev            = &memory,
1771                 .fifo_size      = ISO_FIFO_SIZE,
1772                 .bEndpointAddress = 9,
1773                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1774                 .reg_udccs      = &UDC_REGS->udccs[9],
1775                 .reg_ubcr       = &UDC_REGS->ubcr9,
1776                 .reg_uddr       = &UDC_REGS->uddr9,
1777         },
1778         .ep[10] = {
1779                 .ep = {
1780                         .name           = "ep10in-int",
1781                         .ops            = &pxa25x_ep_ops,
1782                         .maxpacket      = INT_FIFO_SIZE,
1783                 },
1784                 .dev            = &memory,
1785                 .fifo_size      = INT_FIFO_SIZE,
1786                 .bEndpointAddress = USB_DIR_IN | 10,
1787                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
1788                 .reg_udccs      = &UDC_REGS->udccs[10],
1789                 .reg_uddr       = &UDC_REGS->uddr10,
1790         },
1791
1792         /* third group of endpoints */
1793         .ep[11] = {
1794                 .ep = {
1795                         .name           = "ep11in-bulk",
1796                         .ops            = &pxa25x_ep_ops,
1797                         .maxpacket      = BULK_FIFO_SIZE,
1798                 },
1799                 .dev            = &memory,
1800                 .fifo_size      = BULK_FIFO_SIZE,
1801                 .bEndpointAddress = USB_DIR_IN | 11,
1802                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1803                 .reg_udccs      = &UDC_REGS->udccs[11],
1804                 .reg_uddr       = &UDC_REGS->uddr11,
1805         },
1806         .ep[12] = {
1807                 .ep = {
1808                         .name           = "ep12out-bulk",
1809                         .ops            = &pxa25x_ep_ops,
1810                         .maxpacket      = BULK_FIFO_SIZE,
1811                 },
1812                 .dev            = &memory,
1813                 .fifo_size      = BULK_FIFO_SIZE,
1814                 .bEndpointAddress = 12,
1815                 .bmAttributes   = USB_ENDPOINT_XFER_BULK,
1816                 .reg_udccs      = &UDC_REGS->udccs[12],
1817                 .reg_ubcr       = &UDC_REGS->ubcr12,
1818                 .reg_uddr       = &UDC_REGS->uddr12,
1819         },
1820         .ep[13] = {
1821                 .ep = {
1822                         .name           = "ep13in-iso",
1823                         .ops            = &pxa25x_ep_ops,
1824                         .maxpacket      = ISO_FIFO_SIZE,
1825                 },
1826                 .dev            = &memory,
1827                 .fifo_size      = ISO_FIFO_SIZE,
1828                 .bEndpointAddress = USB_DIR_IN | 13,
1829                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1830                 .reg_udccs      = &UDC_REGS->udccs[13],
1831                 .reg_uddr       = &UDC_REGS->uddr13,
1832         },
1833         .ep[14] = {
1834                 .ep = {
1835                         .name           = "ep14out-iso",
1836                         .ops            = &pxa25x_ep_ops,
1837                         .maxpacket      = ISO_FIFO_SIZE,
1838                 },
1839                 .dev            = &memory,
1840                 .fifo_size      = ISO_FIFO_SIZE,
1841                 .bEndpointAddress = 14,
1842                 .bmAttributes   = USB_ENDPOINT_XFER_ISOC,
1843                 .reg_udccs      = &UDC_REGS->udccs[14],
1844                 .reg_ubcr       = &UDC_REGS->ubcr14,
1845                 .reg_uddr       = &UDC_REGS->uddr14,
1846         },
1847         .ep[15] = {
1848                 .ep = {
1849                         .name           = "ep15in-int",
1850                         .ops            = &pxa25x_ep_ops,
1851                         .maxpacket      = INT_FIFO_SIZE,
1852                 },
1853                 .dev            = &memory,
1854                 .fifo_size      = INT_FIFO_SIZE,
1855                 .bEndpointAddress = USB_DIR_IN | 15,
1856                 .bmAttributes   = USB_ENDPOINT_XFER_INT,
1857                 .reg_udccs      = &UDC_REGS->udccs[15],
1858                 .reg_uddr       = &UDC_REGS->uddr15,
1859         },
1860 #endif /* !CONFIG_USB_PXA25X_SMALL */
1861 };
1862
1863 static void udc_command(int cmd)
1864 {
1865         switch (cmd) {
1866         case PXA2XX_UDC_CMD_CONNECT:
1867                 setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1868                         GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1869
1870                 /* enable pullup */
1871                 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1872                         GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
1873
1874                 debug("Connected to USB\n");
1875                 break;
1876
1877         case PXA2XX_UDC_CMD_DISCONNECT:
1878                 /* disable pullup resistor */
1879                 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1880                         GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
1881
1882                 /* setup pin as input, line will float */
1883                 clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1884                         GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1885
1886                 debug("Disconnected from USB\n");
1887                 break;
1888         }
1889 }
1890
1891 static struct pxa2xx_udc_mach_info mach_info = {
1892         .udc_command = udc_command,
1893 };
1894
1895 /*
1896  * when a driver is successfully registered, it will receive
1897  * control requests including set_configuration(), which enables
1898  * non-control requests.  then usb traffic follows until a
1899  * disconnect is reported.  then a host may connect again, or
1900  * the driver might get unbound.
1901  */
1902 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1903 {
1904         struct pxa25x_udc *dev = &memory;
1905         int retval;
1906         uint32_t chiprev;
1907
1908         if (!driver
1909                         || driver->speed < USB_SPEED_FULL
1910                         || !driver->disconnect
1911                         || !driver->setup)
1912                 return -EINVAL;
1913         if (!dev)
1914                 return -ENODEV;
1915         if (dev->driver)
1916                 return -EBUSY;
1917
1918         /* Enable clock for usb controller */
1919         setbits_le32(CKEN, CKEN11_USB);
1920
1921         /* first hook up the driver ... */
1922         dev->driver = driver;
1923         dev->pullup = 1;
1924
1925         /* trigger chiprev-specific logic */
1926         switch ((chiprev = pxa_get_cpu_revision())) {
1927         case PXA255_A0:
1928                 dev->has_cfr = 1;
1929                 break;
1930         case PXA250_A0:
1931         case PXA250_A1:
1932                 /* A0/A1 "not released"; ep 13, 15 unusable */
1933                 /* fall through */
1934         case PXA250_B2: case PXA210_B2:
1935         case PXA250_B1: case PXA210_B1:
1936         case PXA250_B0: case PXA210_B0:
1937                 /* OUT-DMA is broken ... */
1938                 /* fall through */
1939         case PXA250_C0: case PXA210_C0:
1940                 break;
1941         default:
1942                 printf("%s: unrecognized processor: %08x\n",
1943                         DRIVER_NAME, chiprev);
1944                 return -ENODEV;
1945         }
1946
1947         the_controller = dev;
1948
1949         /* prepare watchdog timer */
1950         dev->watchdog.running = 0;
1951         dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
1952         dev->watchdog.function = udc_watchdog;
1953
1954         dev->mach = &mach_info;
1955
1956         udc_disable(dev);
1957         udc_reinit(dev);
1958
1959         dev->gadget.name = "pxa2xx_udc";
1960         retval = driver->bind(&dev->gadget);
1961         if (retval) {
1962                 printf("bind to driver %s --> error %d\n",
1963                                 DRIVER_NAME, retval);
1964                 dev->driver = NULL;
1965                 return retval;
1966         }
1967
1968         /*
1969          * ... then enable host detection and ep0; and we're ready
1970          * for set_configuration as well as eventual disconnect.
1971          */
1972         printf("registered gadget driver '%s'\n", DRIVER_NAME);
1973
1974         pullup(dev);
1975         dump_state(dev);
1976         return 0;
1977 }
1978
1979 static void
1980 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1981 {
1982         int i;
1983
1984         /* don't disconnect drivers more than once */
1985         if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1986                 driver = NULL;
1987         dev->gadget.speed = USB_SPEED_UNKNOWN;
1988
1989         /* prevent new request submissions, kill any outstanding requests  */
1990         for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1991                 struct pxa25x_ep *ep = &dev->ep[i];
1992
1993                 ep->stopped = 1;
1994                 nuke(ep, -ESHUTDOWN);
1995         }
1996         stop_watchdog(dev);
1997
1998         /* report disconnect; the driver is already quiesced */
1999         if (driver)
2000                 driver->disconnect(&dev->gadget);
2001
2002         /* re-init driver-visible data structures */
2003         udc_reinit(dev);
2004 }
2005
2006 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2007 {
2008         struct pxa25x_udc       *dev = the_controller;
2009
2010         if (!dev)
2011                 return -ENODEV;
2012         if (!driver || driver != dev->driver || !driver->unbind)
2013                 return -EINVAL;
2014
2015         local_irq_disable();
2016         dev->pullup = 0;
2017         pullup(dev);
2018         stop_activity(dev, driver);
2019         local_irq_enable();
2020
2021         driver->unbind(&dev->gadget);
2022         dev->driver = NULL;
2023
2024         printf("unregistered gadget driver '%s'\n", DRIVER_NAME);
2025         dump_state(dev);
2026
2027         the_controller = NULL;
2028
2029         clrbits_le32(CKEN, CKEN11_USB);
2030
2031         return 0;
2032 }
2033
2034 extern void udc_disconnect(void)
2035 {
2036         setbits_le32(CKEN, CKEN11_USB);
2037         udc_clear_mask_UDCCR(UDCCR_UDE);
2038         udc_command(PXA2XX_UDC_CMD_DISCONNECT);
2039         clrbits_le32(CKEN, CKEN11_USB);
2040 }
2041
2042 /*-------------------------------------------------------------------------*/
2043
2044 extern int
2045 usb_gadget_handle_interrupts(int index)
2046 {
2047         return pxa25x_udc_irq();
2048 }