1 // SPDX-License-Identifier: GPL-2.0+
3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
10 * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
12 * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
15 #define CONFIG_USB_PXA25X_SMALL
16 #define DRIVER_NAME "pxa25x_udc_linux"
17 #define ARCH_HAS_PREFETCH
22 #include <asm/byteorder.h>
23 #include <asm/system.h>
24 #include <asm/mach-types.h>
25 #include <asm/unaligned.h>
26 #include <dm/devres.h>
27 #include <linux/bug.h>
28 #include <linux/compat.h>
31 #include <asm/arch/pxa.h>
32 #include <linux/delay.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <asm/arch/pxa-regs.h>
38 #include "pxa25x_udc.h"
41 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
42 * series processors. The UDC for the IXP 4xx series is very similar.
43 * There are fifteen endpoints, in addition to ep0.
45 * Such controller drivers work with a gadget driver. The gadget driver
46 * returns descriptors, implements configuration and data protocols used
47 * by the host to interact with this device, and allocates endpoints to
48 * the different protocol interfaces. The controller driver virtualizes
49 * usb hardware so that the gadget drivers will be more portable.
51 * This UDC hardware wants to implement a bit too much USB protocol, so
52 * it constrains the sorts of USB configuration change events that work.
53 * The errata for these chips are misleading; some "fixed" bugs from
54 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
56 * Note that the UDC hardware supports DMA (except on IXP) but that's
57 * not used here. IN-DMA (to host) is simple enough, when the data is
58 * suitably aligned (16 bytes) ... the network stack doesn't do that,
59 * other software can. OUT-DMA is buggy in most chip versions, as well
60 * as poorly designed (data toggle not automatic). So this driver won't
61 * bother using DMA. (Mostly-working IN-DMA support was available in
62 * kernels before 2.6.23, but was never enabled or well tested.)
65 #define DRIVER_VERSION "18-August-2012"
66 #define DRIVER_DESC "PXA 25x USB Device Controller driver"
68 static const char driver_name[] = "pxa25x_udc";
69 static const char ep0name[] = "ep0";
72 static inline void start_watchdog(struct pxa25x_udc *udc)
74 debug("Started watchdog\n");
75 udc->watchdog.base = get_timer(0);
76 udc->watchdog.running = 1;
79 static inline void stop_watchdog(struct pxa25x_udc *udc)
81 udc->watchdog.running = 0;
82 debug("Stopped watchdog\n");
85 static inline void test_watchdog(struct pxa25x_udc *udc)
87 if (!udc->watchdog.running)
90 debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base),
91 udc->watchdog.period);
93 if (get_timer(udc->watchdog.base) >= udc->watchdog.period) {
95 udc->watchdog.function(udc);
99 static void udc_watchdog(struct pxa25x_udc *dev)
101 uint32_t udccs0 = readl(&dev->regs->udccs[0]);
103 debug("Fired up udc_watchdog\n");
106 if (dev->ep0state == EP0_STALL
107 && (udccs0 & UDCCS0_FST) == 0
108 && (udccs0 & UDCCS0_SST) == 0) {
109 writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]);
110 debug("ep0 re-stall\n");
118 static const char * const state_name[] = {
120 "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
121 "EP0_END_XFER", "EP0_STALL"
125 dump_udccr(const char *label)
127 u32 udccr = readl(&UDC_REGS->udccr);
128 debug("%s %02X =%s%s%s%s%s%s%s%s\n",
130 (udccr & UDCCR_REM) ? " rem" : "",
131 (udccr & UDCCR_RSTIR) ? " rstir" : "",
132 (udccr & UDCCR_SRM) ? " srm" : "",
133 (udccr & UDCCR_SUSIR) ? " susir" : "",
134 (udccr & UDCCR_RESIR) ? " resir" : "",
135 (udccr & UDCCR_RSM) ? " rsm" : "",
136 (udccr & UDCCR_UDA) ? " uda" : "",
137 (udccr & UDCCR_UDE) ? " ude" : "");
141 dump_udccs0(const char *label)
143 u32 udccs0 = readl(&UDC_REGS->udccs[0]);
145 debug("%s %s %02X =%s%s%s%s%s%s%s%s\n",
146 label, state_name[the_controller->ep0state], udccs0,
147 (udccs0 & UDCCS0_SA) ? " sa" : "",
148 (udccs0 & UDCCS0_RNE) ? " rne" : "",
149 (udccs0 & UDCCS0_FST) ? " fst" : "",
150 (udccs0 & UDCCS0_SST) ? " sst" : "",
151 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
152 (udccs0 & UDCCS0_FTF) ? " ftf" : "",
153 (udccs0 & UDCCS0_IPR) ? " ipr" : "",
154 (udccs0 & UDCCS0_OPR) ? " opr" : "");
158 dump_state(struct pxa25x_udc *dev)
163 debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
164 state_name[dev->ep0state],
165 readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0),
166 readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0),
167 readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl));
170 tmp = readl(&UDC_REGS->udccfr);
171 debug("udccfr %02X =%s%s\n", tmp,
172 (tmp & UDCCFR_AREN) ? " aren" : "",
173 (tmp & UDCCFR_ACM) ? " acm" : "");
177 debug("no gadget driver bound\n");
180 debug("ep0 driver '%s'\n", "ether");
182 dump_udccs0("udccs0");
183 debug("ep0 IN %lu/%lu, OUT %lu/%lu\n",
184 dev->stats.write.bytes, dev->stats.write.ops,
185 dev->stats.read.bytes, dev->stats.read.ops);
187 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
188 if (dev->ep[i].desc == NULL)
190 debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
196 static inline void dump_udccr(const char *label) { }
197 static inline void dump_udccs0(const char *label) { }
198 static inline void dump_state(struct pxa25x_udc *dev) { }
203 * ---------------------------------------------------------------------------
204 * endpoint related parts of the api to the usb controller hardware,
205 * used by gadget driver; and the inner talker-to-hardware core.
206 * ---------------------------------------------------------------------------
209 static void pxa25x_ep_fifo_flush(struct usb_ep *ep);
210 static void nuke(struct pxa25x_ep *, int status);
212 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
213 static void pullup_off(void)
215 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
217 if (mach->udc_command)
218 mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
221 static void pullup_on(void)
223 struct pxa2xx_udc_mach_info *mach = the_controller->mach;
225 if (mach->udc_command)
226 mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
229 static void pio_irq_enable(int bEndpointAddress)
231 bEndpointAddress &= 0xf;
232 if (bEndpointAddress < 8) {
233 clrbits_le32(&the_controller->regs->uicr0,
234 1 << bEndpointAddress);
236 bEndpointAddress -= 8;
237 clrbits_le32(&the_controller->regs->uicr1,
238 1 << bEndpointAddress);
242 static void pio_irq_disable(int bEndpointAddress)
244 bEndpointAddress &= 0xf;
245 if (bEndpointAddress < 8) {
246 setbits_le32(&the_controller->regs->uicr0,
247 1 << bEndpointAddress);
249 bEndpointAddress -= 8;
250 setbits_le32(&the_controller->regs->uicr1,
251 1 << bEndpointAddress);
255 static inline void udc_set_mask_UDCCR(int mask)
258 * The UDCCR reg contains mask and interrupt status bits,
259 * so using '|=' isn't safe as it may ack an interrupt.
261 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
264 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
267 static inline void udc_clear_mask_UDCCR(int mask)
269 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
271 mask = ~mask & mask_bits;
272 clrbits_le32(&the_controller->regs->udccr, ~mask);
275 static inline void udc_ack_int_UDCCR(int mask)
277 const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
280 clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
284 * endpoint enable/disable
286 * we need to verify the descriptors used to enable endpoints. since pxa25x
287 * endpoint configurations are fixed, and are pretty much always enabled,
288 * there's not a lot to manage here.
290 * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
291 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
292 * for a single interface (with only the default altsetting) and for gadget
293 * drivers that don't halt endpoints (not reset by set_interface). that also
294 * means that if you use ISO, you must violate the USB spec rule that all
295 * iso endpoints must be in non-default altsettings.
297 static int pxa25x_ep_enable(struct usb_ep *_ep,
298 const struct usb_endpoint_descriptor *desc)
300 struct pxa25x_ep *ep;
301 struct pxa25x_udc *dev;
303 ep = container_of(_ep, struct pxa25x_ep, ep);
304 if (!_ep || !desc || ep->desc || _ep->name == ep0name
305 || desc->bDescriptorType != USB_DT_ENDPOINT
306 || ep->bEndpointAddress != desc->bEndpointAddress
308 le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
309 printf("%s, bad ep or descriptor\n", __func__);
313 /* xfer types must match, except that interrupt ~= bulk */
314 if (ep->bmAttributes != desc->bmAttributes
315 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
316 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
317 printf("%s, %s type mismatch\n", __func__, _ep->name);
321 /* hardware _could_ do smaller, but driver doesn't */
322 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
323 && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))
325 || !get_unaligned(&desc->wMaxPacketSize)) {
326 printf("%s, bad %s maxpacket\n", __func__, _ep->name);
331 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
332 printf("%s, bogus device state\n", __func__);
339 ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
341 /* flush fifo (mostly for OUT buffers) */
342 pxa25x_ep_fifo_flush(_ep);
344 /* ... reset halt state too, if we could ... */
346 debug("enabled %s\n", _ep->name);
350 static int pxa25x_ep_disable(struct usb_ep *_ep)
352 struct pxa25x_ep *ep;
355 ep = container_of(_ep, struct pxa25x_ep, ep);
356 if (!_ep || !ep->desc) {
357 printf("%s, %s not enabled\n", __func__,
358 _ep ? ep->ep.name : NULL);
361 local_irq_save(flags);
363 nuke(ep, -ESHUTDOWN);
365 /* flush fifo (mostly for IN buffers) */
366 pxa25x_ep_fifo_flush(_ep);
371 local_irq_restore(flags);
372 debug("%s disabled\n", _ep->name);
376 /*-------------------------------------------------------------------------*/
379 * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers
380 * must still pass correctly initialized endpoints, since other controller
381 * drivers may care about how it's currently set up (dma issues etc).
385 * pxa25x_ep_alloc_request - allocate a request data structure
387 static struct usb_request *
388 pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
390 struct pxa25x_request *req;
392 req = kzalloc(sizeof(*req), gfp_flags);
396 INIT_LIST_HEAD(&req->queue);
402 * pxa25x_ep_free_request - deallocate a request data structure
405 pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
407 struct pxa25x_request *req;
409 req = container_of(_req, struct pxa25x_request, req);
410 WARN_ON(!list_empty(&req->queue));
414 /*-------------------------------------------------------------------------*/
417 * done - retire a request; caller blocked irqs
419 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
421 unsigned stopped = ep->stopped;
423 list_del_init(&req->queue);
425 if (likely(req->req.status == -EINPROGRESS))
426 req->req.status = status;
428 status = req->req.status;
430 if (status && status != -ESHUTDOWN)
431 debug("complete %s req %p stat %d len %u/%u\n",
432 ep->ep.name, &req->req, status,
433 req->req.actual, req->req.length);
435 /* don't modify queue heads during completion callback */
437 req->req.complete(&ep->ep, &req->req);
438 ep->stopped = stopped;
442 static inline void ep0_idle(struct pxa25x_udc *dev)
444 dev->ep0state = EP0_IDLE;
448 write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max)
451 unsigned length, count;
453 debug("%s(): uddr %p\n", __func__, uddr);
455 buf = req->req.buf + req->req.actual;
458 /* how big will this packet be? */
459 length = min(req->req.length - req->req.actual, max);
460 req->req.actual += length;
463 while (likely(count--))
464 writeb(*buf++, uddr);
470 * write to an IN endpoint fifo, as many packets as possible.
471 * irqs will use this to write the rest later.
472 * caller guarantees at least one packet buffer is ready (or a zlp).
475 write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
479 max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize));
482 int is_last, is_short;
484 count = write_packet(ep->reg_uddr, req, max);
486 /* last packet is usually short (or a zlp) */
487 if (unlikely(count != max))
488 is_last = is_short = 1;
490 if (likely(req->req.length != req->req.actual)
495 /* interrupt/iso maxpacket may not fill the fifo */
496 is_short = unlikely(max < ep->fifo_size);
499 debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n",
501 is_last ? "/L" : "", is_short ? "/S" : "",
502 req->req.length - req->req.actual, req);
505 * let loose that packet. maybe try writing another one,
506 * double buffering might work. TSP, TPC, and TFS
507 * bit values are the same for all normal IN endpoints.
509 writel(UDCCS_BI_TPC, ep->reg_udccs);
511 writel(UDCCS_BI_TSP, ep->reg_udccs);
513 /* requests complete when all IN data is in the FIFO */
516 if (list_empty(&ep->queue))
517 pio_irq_disable(ep->bEndpointAddress);
522 * TODO experiment: how robust can fifo mode tweaking be?
523 * double buffering is off in the default fifo mode, which
524 * prevents TFS from being set here.
527 } while (readl(ep->reg_udccs) & UDCCS_BI_TFS);
532 * caller asserts req->pending (ep0 irq status nyet cleared); starts
533 * ep0 data stage. these chips want very simple state transitions.
536 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
538 writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]);
539 writel(USIR0_IR0, &dev->regs->usir0);
540 dev->req_pending = 0;
541 debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n",
542 __func__, tag, readl(&dev->regs->udccs[0]), flags,
543 readl(&dev->regs->usir1), readl(&dev->regs->usir0));
547 write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
552 count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE);
553 ep->dev->stats.write.bytes += count;
555 /* last packet "must be" short (or a zlp) */
556 is_short = (count != EP0_FIFO_SIZE);
558 debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count,
559 req->req.length - req->req.actual, req);
561 if (unlikely(is_short)) {
562 if (ep->dev->req_pending)
563 ep0start(ep->dev, UDCCS0_IPR, "short IN");
565 writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]);
567 count = req->req.length;
572 * This seems to get rid of lost status irqs in some cases:
573 * host responds quickly, or next request involves config
574 * change automagic, or should have been hidden, or ...
576 * FIXME get rid of all udelays possible...
578 if (count >= EP0_FIFO_SIZE) {
581 if ((readl(&ep->dev->regs->udccs[0]) &
583 /* clear OPR, generate ack */
585 &ep->dev->regs->udccs[0]);
592 } else if (ep->dev->req_pending)
593 ep0start(ep->dev, 0, "IN");
600 * read_fifo - unload packet(s) from the fifo we use for usb OUT
601 * transfers and put them into the request. caller should have made
602 * sure there's at least one packet ready.
604 * returns true if the request completed because of short packet or the
605 * request buffer having filled (and maybe overran till end-of-packet).
608 read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
612 unsigned bufferspace, count, is_short;
616 * make sure there's a packet in the FIFO.
617 * UDCCS_{BO,IO}_RPC are all the same bit value.
618 * UDCCS_{BO,IO}_RNE are all the same bit value.
620 udccs = readl(ep->reg_udccs);
621 if (unlikely((udccs & UDCCS_BO_RPC) == 0))
623 buf = req->req.buf + req->req.actual;
625 bufferspace = req->req.length - req->req.actual;
627 /* read all bytes from this packet */
628 if (likely(udccs & UDCCS_BO_RNE)) {
629 count = 1 + (0x0ff & readl(ep->reg_ubcr));
630 req->req.actual += min(count, bufferspace);
633 is_short = (count < ep->ep.maxpacket);
634 debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
635 ep->ep.name, udccs, count,
636 is_short ? "/S" : "",
637 req, req->req.actual, req->req.length);
638 while (likely(count-- != 0)) {
639 u8 byte = readb(ep->reg_uddr);
641 if (unlikely(bufferspace == 0)) {
643 * this happens when the driver's buffer
644 * is smaller than what the host sent.
645 * discard the extra data.
647 if (req->req.status != -EOVERFLOW)
648 printf("%s overflow %d\n",
650 req->req.status = -EOVERFLOW;
656 writel(UDCCS_BO_RPC, ep->reg_udccs);
657 /* RPC/RSP/RNE could now reflect the other packet buffer */
659 /* iso is one request per packet */
660 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
661 if (udccs & UDCCS_IO_ROF)
662 req->req.status = -EHOSTUNREACH;
663 /* more like "is_done" */
668 if (is_short || req->req.actual == req->req.length) {
670 if (list_empty(&ep->queue))
671 pio_irq_disable(ep->bEndpointAddress);
675 /* finished that packet. the next one may be waiting... */
681 * special ep0 version of the above. no UBCR0 or double buffering; status
682 * handshaking is magic. most device protocols don't need control-OUT.
683 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
684 * protocols do use them.
687 read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
690 unsigned bufferspace;
692 buf = req->req.buf + req->req.actual;
693 bufferspace = req->req.length - req->req.actual;
695 while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) {
696 byte = (u8)readb(&ep->dev->regs->uddr0);
698 if (unlikely(bufferspace == 0)) {
700 * this happens when the driver's buffer
701 * is smaller than what the host sent.
702 * discard the extra data.
704 if (req->req.status != -EOVERFLOW)
705 printf("%s overflow\n", ep->ep.name);
706 req->req.status = -EOVERFLOW;
714 writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]);
717 if (req->req.actual >= req->req.length)
720 /* finished that packet. the next one may be waiting... */
724 /*-------------------------------------------------------------------------*/
727 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
729 struct pxa25x_request *req;
730 struct pxa25x_ep *ep;
731 struct pxa25x_udc *dev;
734 req = container_of(_req, struct pxa25x_request, req);
735 if (unlikely(!_req || !_req->complete || !_req->buf
736 || !list_empty(&req->queue))) {
737 printf("%s, bad params\n", __func__);
741 ep = container_of(_ep, struct pxa25x_ep, ep);
742 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
743 printf("%s, bad ep\n", __func__);
748 if (unlikely(!dev->driver
749 || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
750 printf("%s, bogus device state\n", __func__);
755 * iso is always one packet per request, that's the only way
756 * we can report per-packet status. that also helps with dma.
758 if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
760 le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize))))
763 debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
764 _ep->name, _req, _req->length, _req->buf);
766 local_irq_save(flags);
768 _req->status = -EINPROGRESS;
771 /* kickstart this i/o queue? */
772 if (list_empty(&ep->queue) && !ep->stopped) {
773 if (ep->desc == NULL/* ep0 */) {
774 unsigned length = _req->length;
776 switch (dev->ep0state) {
777 case EP0_IN_DATA_PHASE:
778 dev->stats.write.ops++;
779 if (write_ep0_fifo(ep, req))
783 case EP0_OUT_DATA_PHASE:
784 dev->stats.read.ops++;
786 if (dev->req_config) {
787 debug("ep0 config ack%s\n",
788 dev->has_cfr ? "" : " raced");
790 writel(UDCCFR_AREN|UDCCFR_ACM
792 &ep->dev->regs->udccfr);
794 dev->ep0state = EP0_END_XFER;
795 local_irq_restore(flags);
798 if (dev->req_pending)
799 ep0start(dev, UDCCS0_IPR, "OUT");
802 &ep->dev->regs->udccs[0])
804 && read_ep0_fifo(ep, req))) {
812 printf("ep0 i/o, odd state %d\n",
814 local_irq_restore(flags);
817 /* can the FIFO can satisfy the request immediately? */
818 } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
819 if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0
820 && write_fifo(ep, req))
822 } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0
823 && read_fifo(ep, req)) {
827 if (likely(req && ep->desc))
828 pio_irq_enable(ep->bEndpointAddress);
831 /* pio or dma irq handler advances the queue. */
832 if (likely(req != NULL))
833 list_add_tail(&req->queue, &ep->queue);
834 local_irq_restore(flags);
841 * nuke - dequeue ALL requests
843 static void nuke(struct pxa25x_ep *ep, int status)
845 struct pxa25x_request *req;
847 /* called with irqs blocked */
848 while (!list_empty(&ep->queue)) {
849 req = list_entry(ep->queue.next,
850 struct pxa25x_request,
852 done(ep, req, status);
855 pio_irq_disable(ep->bEndpointAddress);
859 /* dequeue JUST ONE request */
860 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
862 struct pxa25x_ep *ep;
863 struct pxa25x_request *req;
866 ep = container_of(_ep, struct pxa25x_ep, ep);
867 if (!_ep || ep->ep.name == ep0name)
870 local_irq_save(flags);
872 /* make sure it's actually queued on this endpoint */
873 list_for_each_entry(req, &ep->queue, queue) {
874 if (&req->req == _req)
877 if (&req->req != _req) {
878 local_irq_restore(flags);
882 done(ep, req, -ECONNRESET);
884 local_irq_restore(flags);
888 /*-------------------------------------------------------------------------*/
890 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
892 struct pxa25x_ep *ep;
895 ep = container_of(_ep, struct pxa25x_ep, ep);
897 || (!ep->desc && ep->ep.name != ep0name))
898 || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
899 printf("%s, bad ep\n", __func__);
904 * this path (reset toggle+halt) is needed to implement
905 * SET_INTERFACE on normal hardware. but it can't be
906 * done from software on the PXA UDC, and the hardware
907 * forgets to do it as part of SET_INTERFACE automagic.
909 printf("only host can clear %s halt\n", _ep->name);
913 local_irq_save(flags);
915 if ((ep->bEndpointAddress & USB_DIR_IN) != 0
916 && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0
917 || !list_empty(&ep->queue))) {
918 local_irq_restore(flags);
922 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
923 writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs);
925 /* ep0 needs special care */
927 start_watchdog(ep->dev);
928 ep->dev->req_pending = 0;
929 ep->dev->ep0state = EP0_STALL;
931 /* and bulk/intr endpoints like dropping stalls too */
934 for (i = 0; i < 1000; i += 20) {
935 if (readl(ep->reg_udccs) & UDCCS_BI_SST)
940 local_irq_restore(flags);
942 debug("%s halt\n", _ep->name);
946 static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
948 struct pxa25x_ep *ep;
950 ep = container_of(_ep, struct pxa25x_ep, ep);
952 printf("%s, bad ep\n", __func__);
955 /* pxa can't report unclaimed bytes from IN fifos */
956 if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
958 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
959 || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0)
962 return (readl(ep->reg_ubcr) & 0xfff) + 1;
965 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
967 struct pxa25x_ep *ep;
969 ep = container_of(_ep, struct pxa25x_ep, ep);
970 if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
971 printf("%s, bad ep\n", __func__);
975 /* toggle and halt bits stay unchanged */
977 /* for OUT, just read and discard the FIFO contents. */
978 if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
979 while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0)
980 (void)readb(ep->reg_uddr);
984 /* most IN status is the same, but ISO can't stall */
985 writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
986 | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
987 ? 0 : UDCCS_BI_SST), ep->reg_udccs);
991 static struct usb_ep_ops pxa25x_ep_ops = {
992 .enable = pxa25x_ep_enable,
993 .disable = pxa25x_ep_disable,
995 .alloc_request = pxa25x_ep_alloc_request,
996 .free_request = pxa25x_ep_free_request,
998 .queue = pxa25x_ep_queue,
999 .dequeue = pxa25x_ep_dequeue,
1001 .set_halt = pxa25x_ep_set_halt,
1002 .fifo_status = pxa25x_ep_fifo_status,
1003 .fifo_flush = pxa25x_ep_fifo_flush,
1007 /* ---------------------------------------------------------------------------
1008 * device-scoped parts of the api to the usb controller hardware
1009 * ---------------------------------------------------------------------------
1012 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
1014 return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) |
1015 (readl(&the_controller->regs->ufnrl) & 0xff);
1018 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
1020 /* host may not have enabled remote wakeup */
1021 if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0)
1022 return -EHOSTUNREACH;
1023 udc_set_mask_UDCCR(UDCCR_RSM);
1027 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
1028 static void udc_enable(struct pxa25x_udc *);
1029 static void udc_disable(struct pxa25x_udc *);
1032 * We disable the UDC -- and its 48 MHz clock -- whenever it's not
1035 static int pullup(struct pxa25x_udc *udc)
1043 int is_active = udc->pullup;
1051 if (udc->gadget.speed != USB_SPEED_UNKNOWN)
1052 stop_activity(udc, udc->driver);
1061 /* VBUS reporting logically comes from a transceiver */
1062 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1064 struct pxa25x_udc *udc;
1066 udc = container_of(_gadget, struct pxa25x_udc, gadget);
1067 printf("vbus %s\n", is_active ? "supplied" : "inactive");
1072 /* drivers may have software control over D+ pullup */
1073 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
1075 struct pxa25x_udc *udc;
1077 udc = container_of(_gadget, struct pxa25x_udc, gadget);
1079 /* not all boards support pullup control */
1080 if (!udc->mach->udc_command)
1083 udc->pullup = (is_active != 0);
1089 * boards may consume current from VBUS, up to 100-500mA based on config.
1090 * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
1091 * violate USB specs.
1093 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1098 static const struct usb_gadget_ops pxa25x_udc_ops = {
1099 .get_frame = pxa25x_udc_get_frame,
1100 .wakeup = pxa25x_udc_wakeup,
1101 .vbus_session = pxa25x_udc_vbus_session,
1102 .pullup = pxa25x_udc_pullup,
1103 .vbus_draw = pxa25x_udc_vbus_draw,
1106 /*-------------------------------------------------------------------------*/
1109 * udc_disable - disable USB device controller
1111 static void udc_disable(struct pxa25x_udc *dev)
1113 /* block all irqs */
1114 udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
1115 writel(0xff, &dev->regs->uicr0);
1116 writel(0xff, &dev->regs->uicr1);
1117 writel(UFNRH_SIM, &dev->regs->ufnrh);
1119 /* if hardware supports it, disconnect from usb */
1122 udc_clear_mask_UDCCR(UDCCR_UDE);
1125 dev->gadget.speed = USB_SPEED_UNKNOWN;
1129 * udc_reinit - initialize software state
1131 static void udc_reinit(struct pxa25x_udc *dev)
1135 /* device/ep0 records init */
1136 INIT_LIST_HEAD(&dev->gadget.ep_list);
1137 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1138 dev->ep0state = EP0_IDLE;
1140 /* basic endpoint records init */
1141 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1142 struct pxa25x_ep *ep = &dev->ep[i];
1145 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
1149 INIT_LIST_HEAD(&ep->queue);
1153 /* the rest was statically initialized, and is read-only */
1157 * until it's enabled, this UDC should be completely invisible
1160 static void udc_enable(struct pxa25x_udc *dev)
1162 debug("udc: enabling udc\n");
1164 udc_clear_mask_UDCCR(UDCCR_UDE);
1167 * Try to clear these bits before we enable the udc.
1168 * Do not touch reset ack bit, we would take care of it in
1169 * interrupt handle routine
1171 udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR);
1174 dev->gadget.speed = USB_SPEED_UNKNOWN;
1175 dev->stats.irqs = 0;
1178 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1180 * - if RESET is already in progress, ack interrupt
1181 * - unmask reset interrupt
1183 udc_set_mask_UDCCR(UDCCR_UDE);
1184 if (!(readl(&dev->regs->udccr) & UDCCR_UDA))
1185 udc_ack_int_UDCCR(UDCCR_RSTIR);
1187 if (dev->has_cfr /* UDC_RES2 is defined */) {
1189 * pxa255 (a0+) can avoid a set_config race that could
1190 * prevent gadget drivers from configuring correctly
1192 writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr);
1195 /* enable suspend/resume and reset irqs */
1196 udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
1198 /* enable ep0 irqs */
1199 clrbits_le32(&dev->regs->uicr0, UICR0_IM0);
1201 /* if hardware supports it, pullup D+ and wait for reset */
1205 static inline void clear_ep_state(struct pxa25x_udc *dev)
1210 * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1211 * fifos, and pending transactions mustn't be continued in any case.
1213 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1214 nuke(&dev->ep[i], -ECONNABORTED);
1217 static void handle_ep0(struct pxa25x_udc *dev)
1219 u32 udccs0 = readl(&dev->regs->udccs[0]);
1220 struct pxa25x_ep *ep = &dev->ep[0];
1221 struct pxa25x_request *req;
1223 struct usb_ctrlrequest r;
1228 if (list_empty(&ep->queue))
1231 req = list_entry(ep->queue.next, struct pxa25x_request, queue);
1233 /* clear stall status */
1234 if (udccs0 & UDCCS0_SST) {
1236 writel(UDCCS0_SST, &dev->regs->udccs[0]);
1241 /* previous request unfinished? non-error iff back-to-back ... */
1242 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1248 switch (dev->ep0state) {
1250 /* late-breaking status? */
1251 udccs0 = readl(&dev->regs->udccs[0]);
1253 /* start control request? */
1254 if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1255 == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1260 /* read SETUP packet */
1261 for (i = 0; i < 8; i++) {
1262 if (unlikely(!(readl(&dev->regs->udccs[0]) &
1265 debug("SETUP %d!\n", i);
1268 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1270 if (unlikely((readl(&dev->regs->udccs[0]) &
1275 debug("SETUP %02x.%02x v%04x i%04x l%04x\n",
1276 u.r.bRequestType, u.r.bRequest,
1277 le16_to_cpu(u.r.wValue),
1278 le16_to_cpu(u.r.wIndex),
1279 le16_to_cpu(u.r.wLength));
1281 /* cope with automagic for some standard requests. */
1282 dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1283 == USB_TYPE_STANDARD;
1284 dev->req_config = 0;
1285 dev->req_pending = 1;
1286 switch (u.r.bRequest) {
1287 /* hardware restricts gadget drivers here! */
1288 case USB_REQ_SET_CONFIGURATION:
1289 debug("GOT SET_CONFIGURATION\n");
1290 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1292 * reflect hardware's automagic
1293 * up to the gadget driver.
1296 dev->req_config = 1;
1297 clear_ep_state(dev);
1299 * if !has_cfr, there's no synch
1300 * else use AREN (later) not SA|OPR
1301 * USIR0_IR0 acts edge sensitive
1305 /* ... and here, even more ... */
1306 case USB_REQ_SET_INTERFACE:
1307 if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1309 * udc hardware is broken by design:
1310 * - altsetting may only be zero;
1311 * - hw resets all interfaces' eps;
1312 * - ep reset doesn't include halt(?).
1314 printf("broken set_interface (%d/%d)\n",
1315 le16_to_cpu(u.r.wIndex),
1316 le16_to_cpu(u.r.wValue));
1320 /* hardware was supposed to hide this */
1321 case USB_REQ_SET_ADDRESS:
1322 debug("GOT SET ADDRESS\n");
1323 if (u.r.bRequestType == USB_RECIP_DEVICE) {
1324 ep0start(dev, 0, "address");
1330 if (u.r.bRequestType & USB_DIR_IN)
1331 dev->ep0state = EP0_IN_DATA_PHASE;
1333 dev->ep0state = EP0_OUT_DATA_PHASE;
1335 i = dev->driver->setup(&dev->gadget, &u.r);
1337 /* hardware automagic preventing STALL... */
1338 if (dev->req_config) {
1340 * hardware sometimes neglects to tell
1341 * tell us about config change events,
1342 * so later ones may fail...
1344 printf("config change %02x fail %d?\n",
1348 * TODO experiment: if has_cfr,
1349 * hardware didn't ACK; maybe we
1350 * could actually STALL!
1355 /* uninitialized when goto stall */
1358 debug("protocol STALL, "
1360 readl(&dev->regs->udccs[0]), i);
1363 * the watchdog timer helps deal with cases
1364 * where udc seems to clear FST wrongly, and
1365 * then NAKs instead of STALLing.
1367 ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1368 start_watchdog(dev);
1369 dev->ep0state = EP0_STALL;
1371 /* deferred i/o == no response yet */
1372 } else if (dev->req_pending) {
1373 if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1374 || dev->req_std || u.r.wLength))
1375 ep0start(dev, 0, "defer");
1377 ep0start(dev, UDCCS0_IPR, "defer/IPR");
1380 /* expect at least one data or status stage irq */
1383 } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1384 == (UDCCS0_OPR|UDCCS0_SA))) {
1388 * pxa210/250 erratum 131 for B0/B1 says RNE lies.
1389 * still observed on a pxa255 a0.
1394 /* read SETUP data, but don't trust it too much */
1395 for (i = 0; i < 8; i++)
1396 u.raw[i] = (u8)readb(&dev->regs->uddr0);
1397 if ((u.r.bRequestType & USB_RECIP_MASK)
1400 if (u.word[0] == 0 && u.word[1] == 0)
1405 * some random early IRQ:
1408 * - OPR got set, without SA (likely status stage)
1410 debug("random IRQ %X %X\n", udccs0,
1411 readl(&dev->regs->udccs[0]));
1412 writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR),
1413 &dev->regs->udccs[0]);
1416 case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
1417 if (udccs0 & UDCCS0_OPR) {
1418 debug("ep0in premature status\n");
1422 } else /* irq was IPR clearing */ {
1424 debug("next ep0 in packet\n");
1425 /* this IN packet might finish the request */
1426 (void) write_ep0_fifo(ep, req);
1427 } /* else IN token before response was written */
1430 case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
1431 if (udccs0 & UDCCS0_OPR) {
1433 /* this OUT packet might finish the request */
1434 if (read_ep0_fifo(ep, req))
1436 /* else more OUT packets expected */
1437 } /* else OUT token before read was issued */
1438 } else /* irq was IPR clearing */ {
1439 debug("ep0out premature status\n");
1449 * ack control-IN status (maybe in-zlp was skipped)
1450 * also appears after some config change events.
1452 if (udccs0 & UDCCS0_OPR)
1453 writel(UDCCS0_OPR, &dev->regs->udccs[0]);
1457 writel(UDCCS0_FST, &dev->regs->udccs[0]);
1461 writel(USIR0_IR0, &dev->regs->usir0);
1464 static void handle_ep(struct pxa25x_ep *ep)
1466 struct pxa25x_request *req;
1467 int is_in = ep->bEndpointAddress & USB_DIR_IN;
1473 if (likely(!list_empty(&ep->queue)))
1474 req = list_entry(ep->queue.next,
1475 struct pxa25x_request, queue);
1479 /* TODO check FST handling */
1481 udccs = readl(ep->reg_udccs);
1482 if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
1484 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1485 tmp |= UDCCS_BI_SST;
1488 writel(tmp, ep->reg_udccs);
1489 if (req && likely((udccs & UDCCS_BI_TFS) != 0))
1490 completed = write_fifo(ep, req);
1492 } else { /* irq from RPC (or for ISO, ROF) */
1493 if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1494 tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1496 tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1499 writel(tmp, ep->reg_udccs);
1501 /* fifos can hold packets, ready for reading... */
1503 completed = read_fifo(ep, req);
1505 pio_irq_disable(ep->bEndpointAddress);
1508 } while (completed);
1512 * pxa25x_udc_irq - interrupt handler
1514 * avoid delays in ep0 processing. the control handshaking isn't always
1515 * under software control (pxa250c0 and the pxa255 are better), and delays
1516 * could cause usb protocol errors.
1518 static struct pxa25x_udc memory;
1520 pxa25x_udc_irq(void)
1522 struct pxa25x_udc *dev = &memory;
1529 u32 udccr = readl(&dev->regs->udccr);
1533 /* SUSpend Interrupt Request */
1534 if (unlikely(udccr & UDCCR_SUSIR)) {
1535 udc_ack_int_UDCCR(UDCCR_SUSIR);
1537 debug("USB suspend\n");
1539 if (dev->gadget.speed != USB_SPEED_UNKNOWN
1541 && dev->driver->suspend)
1542 dev->driver->suspend(&dev->gadget);
1546 /* RESume Interrupt Request */
1547 if (unlikely(udccr & UDCCR_RESIR)) {
1548 udc_ack_int_UDCCR(UDCCR_RESIR);
1550 debug("USB resume\n");
1552 if (dev->gadget.speed != USB_SPEED_UNKNOWN
1554 && dev->driver->resume)
1555 dev->driver->resume(&dev->gadget);
1558 /* ReSeT Interrupt Request - USB reset */
1559 if (unlikely(udccr & UDCCR_RSTIR)) {
1560 udc_ack_int_UDCCR(UDCCR_RSTIR);
1563 if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) {
1564 debug("USB reset start\n");
1567 * reset driver and endpoints,
1568 * in case that's not yet done
1570 stop_activity(dev, dev->driver);
1573 debug("USB reset end\n");
1574 dev->gadget.speed = USB_SPEED_FULL;
1575 memset(&dev->stats, 0, sizeof dev->stats);
1576 /* driver and endpoints are still reset */
1580 u32 uicr0 = readl(&dev->regs->uicr0);
1581 u32 uicr1 = readl(&dev->regs->uicr1);
1582 u32 usir0 = readl(&dev->regs->usir0);
1583 u32 usir1 = readl(&dev->regs->usir1);
1585 usir0 = usir0 & ~uicr0;
1586 usir1 = usir1 & ~uicr1;
1589 if (unlikely(!usir0 && !usir1))
1592 debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0);
1594 /* control traffic */
1595 if (usir0 & USIR0_IR0) {
1596 dev->ep[0].pio_irqs++;
1601 /* endpoint data transfers */
1602 for (i = 0; i < 8; i++) {
1605 if (i && (usir0 & tmp)) {
1606 handle_ep(&dev->ep[i]);
1607 setbits_le32(&dev->regs->usir0, tmp);
1610 #ifndef CONFIG_USB_PXA25X_SMALL
1612 handle_ep(&dev->ep[i+8]);
1613 setbits_le32(&dev->regs->usir1, tmp);
1620 /* we could also ask for 1 msec SOF (SIR) interrupts */
1626 /*-------------------------------------------------------------------------*/
1629 * this uses load-time allocation and initialization (instead of
1630 * doing it at run-time) to save code, eliminate fault paths, and
1631 * be more obviously correct.
1633 static struct pxa25x_udc memory = {
1637 .ops = &pxa25x_udc_ops,
1638 .ep0 = &memory.ep[0].ep,
1639 .name = driver_name,
1642 /* control endpoint */
1646 .ops = &pxa25x_ep_ops,
1647 .maxpacket = EP0_FIFO_SIZE,
1650 .reg_udccs = &UDC_REGS->udccs[0],
1651 .reg_uddr = &UDC_REGS->uddr0,
1654 /* first group of endpoints */
1657 .name = "ep1in-bulk",
1658 .ops = &pxa25x_ep_ops,
1659 .maxpacket = BULK_FIFO_SIZE,
1662 .fifo_size = BULK_FIFO_SIZE,
1663 .bEndpointAddress = USB_DIR_IN | 1,
1664 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1665 .reg_udccs = &UDC_REGS->udccs[1],
1666 .reg_uddr = &UDC_REGS->uddr1,
1670 .name = "ep2out-bulk",
1671 .ops = &pxa25x_ep_ops,
1672 .maxpacket = BULK_FIFO_SIZE,
1675 .fifo_size = BULK_FIFO_SIZE,
1676 .bEndpointAddress = 2,
1677 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1678 .reg_udccs = &UDC_REGS->udccs[2],
1679 .reg_ubcr = &UDC_REGS->ubcr2,
1680 .reg_uddr = &UDC_REGS->uddr2,
1682 #ifndef CONFIG_USB_PXA25X_SMALL
1685 .name = "ep3in-iso",
1686 .ops = &pxa25x_ep_ops,
1687 .maxpacket = ISO_FIFO_SIZE,
1690 .fifo_size = ISO_FIFO_SIZE,
1691 .bEndpointAddress = USB_DIR_IN | 3,
1692 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1693 .reg_udccs = &UDC_REGS->udccs[3],
1694 .reg_uddr = &UDC_REGS->uddr3,
1698 .name = "ep4out-iso",
1699 .ops = &pxa25x_ep_ops,
1700 .maxpacket = ISO_FIFO_SIZE,
1703 .fifo_size = ISO_FIFO_SIZE,
1704 .bEndpointAddress = 4,
1705 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1706 .reg_udccs = &UDC_REGS->udccs[4],
1707 .reg_ubcr = &UDC_REGS->ubcr4,
1708 .reg_uddr = &UDC_REGS->uddr4,
1712 .name = "ep5in-int",
1713 .ops = &pxa25x_ep_ops,
1714 .maxpacket = INT_FIFO_SIZE,
1717 .fifo_size = INT_FIFO_SIZE,
1718 .bEndpointAddress = USB_DIR_IN | 5,
1719 .bmAttributes = USB_ENDPOINT_XFER_INT,
1720 .reg_udccs = &UDC_REGS->udccs[5],
1721 .reg_uddr = &UDC_REGS->uddr5,
1724 /* second group of endpoints */
1727 .name = "ep6in-bulk",
1728 .ops = &pxa25x_ep_ops,
1729 .maxpacket = BULK_FIFO_SIZE,
1732 .fifo_size = BULK_FIFO_SIZE,
1733 .bEndpointAddress = USB_DIR_IN | 6,
1734 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1735 .reg_udccs = &UDC_REGS->udccs[6],
1736 .reg_uddr = &UDC_REGS->uddr6,
1740 .name = "ep7out-bulk",
1741 .ops = &pxa25x_ep_ops,
1742 .maxpacket = BULK_FIFO_SIZE,
1745 .fifo_size = BULK_FIFO_SIZE,
1746 .bEndpointAddress = 7,
1747 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1748 .reg_udccs = &UDC_REGS->udccs[7],
1749 .reg_ubcr = &UDC_REGS->ubcr7,
1750 .reg_uddr = &UDC_REGS->uddr7,
1754 .name = "ep8in-iso",
1755 .ops = &pxa25x_ep_ops,
1756 .maxpacket = ISO_FIFO_SIZE,
1759 .fifo_size = ISO_FIFO_SIZE,
1760 .bEndpointAddress = USB_DIR_IN | 8,
1761 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1762 .reg_udccs = &UDC_REGS->udccs[8],
1763 .reg_uddr = &UDC_REGS->uddr8,
1767 .name = "ep9out-iso",
1768 .ops = &pxa25x_ep_ops,
1769 .maxpacket = ISO_FIFO_SIZE,
1772 .fifo_size = ISO_FIFO_SIZE,
1773 .bEndpointAddress = 9,
1774 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1775 .reg_udccs = &UDC_REGS->udccs[9],
1776 .reg_ubcr = &UDC_REGS->ubcr9,
1777 .reg_uddr = &UDC_REGS->uddr9,
1781 .name = "ep10in-int",
1782 .ops = &pxa25x_ep_ops,
1783 .maxpacket = INT_FIFO_SIZE,
1786 .fifo_size = INT_FIFO_SIZE,
1787 .bEndpointAddress = USB_DIR_IN | 10,
1788 .bmAttributes = USB_ENDPOINT_XFER_INT,
1789 .reg_udccs = &UDC_REGS->udccs[10],
1790 .reg_uddr = &UDC_REGS->uddr10,
1793 /* third group of endpoints */
1796 .name = "ep11in-bulk",
1797 .ops = &pxa25x_ep_ops,
1798 .maxpacket = BULK_FIFO_SIZE,
1801 .fifo_size = BULK_FIFO_SIZE,
1802 .bEndpointAddress = USB_DIR_IN | 11,
1803 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1804 .reg_udccs = &UDC_REGS->udccs[11],
1805 .reg_uddr = &UDC_REGS->uddr11,
1809 .name = "ep12out-bulk",
1810 .ops = &pxa25x_ep_ops,
1811 .maxpacket = BULK_FIFO_SIZE,
1814 .fifo_size = BULK_FIFO_SIZE,
1815 .bEndpointAddress = 12,
1816 .bmAttributes = USB_ENDPOINT_XFER_BULK,
1817 .reg_udccs = &UDC_REGS->udccs[12],
1818 .reg_ubcr = &UDC_REGS->ubcr12,
1819 .reg_uddr = &UDC_REGS->uddr12,
1823 .name = "ep13in-iso",
1824 .ops = &pxa25x_ep_ops,
1825 .maxpacket = ISO_FIFO_SIZE,
1828 .fifo_size = ISO_FIFO_SIZE,
1829 .bEndpointAddress = USB_DIR_IN | 13,
1830 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1831 .reg_udccs = &UDC_REGS->udccs[13],
1832 .reg_uddr = &UDC_REGS->uddr13,
1836 .name = "ep14out-iso",
1837 .ops = &pxa25x_ep_ops,
1838 .maxpacket = ISO_FIFO_SIZE,
1841 .fifo_size = ISO_FIFO_SIZE,
1842 .bEndpointAddress = 14,
1843 .bmAttributes = USB_ENDPOINT_XFER_ISOC,
1844 .reg_udccs = &UDC_REGS->udccs[14],
1845 .reg_ubcr = &UDC_REGS->ubcr14,
1846 .reg_uddr = &UDC_REGS->uddr14,
1850 .name = "ep15in-int",
1851 .ops = &pxa25x_ep_ops,
1852 .maxpacket = INT_FIFO_SIZE,
1855 .fifo_size = INT_FIFO_SIZE,
1856 .bEndpointAddress = USB_DIR_IN | 15,
1857 .bmAttributes = USB_ENDPOINT_XFER_INT,
1858 .reg_udccs = &UDC_REGS->udccs[15],
1859 .reg_uddr = &UDC_REGS->uddr15,
1861 #endif /* !CONFIG_USB_PXA25X_SMALL */
1864 static void udc_command(int cmd)
1867 case PXA2XX_UDC_CMD_CONNECT:
1868 setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1869 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1872 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1873 GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
1875 debug("Connected to USB\n");
1878 case PXA2XX_UDC_CMD_DISCONNECT:
1879 /* disable pullup resistor */
1880 writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
1881 GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
1883 /* setup pin as input, line will float */
1884 clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
1885 GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
1887 debug("Disconnected from USB\n");
1892 static struct pxa2xx_udc_mach_info mach_info = {
1893 .udc_command = udc_command,
1897 * when a driver is successfully registered, it will receive
1898 * control requests including set_configuration(), which enables
1899 * non-control requests. then usb traffic follows until a
1900 * disconnect is reported. then a host may connect again, or
1901 * the driver might get unbound.
1903 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1905 struct pxa25x_udc *dev = &memory;
1910 || driver->speed < USB_SPEED_FULL
1911 || !driver->disconnect
1919 /* Enable clock for usb controller */
1920 setbits_le32(CKEN, CKEN11_USB);
1922 /* first hook up the driver ... */
1923 dev->driver = driver;
1926 /* trigger chiprev-specific logic */
1927 switch ((chiprev = pxa_get_cpu_revision())) {
1933 /* A0/A1 "not released"; ep 13, 15 unusable */
1935 case PXA250_B2: case PXA210_B2:
1936 case PXA250_B1: case PXA210_B1:
1937 case PXA250_B0: case PXA210_B0:
1938 /* OUT-DMA is broken ... */
1940 case PXA250_C0: case PXA210_C0:
1943 printf("%s: unrecognized processor: %08x\n",
1944 DRIVER_NAME, chiprev);
1948 the_controller = dev;
1950 /* prepare watchdog timer */
1951 dev->watchdog.running = 0;
1952 dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
1953 dev->watchdog.function = udc_watchdog;
1955 dev->mach = &mach_info;
1960 dev->gadget.name = "pxa2xx_udc";
1961 retval = driver->bind(&dev->gadget);
1963 printf("bind to driver %s --> error %d\n",
1964 DRIVER_NAME, retval);
1970 * ... then enable host detection and ep0; and we're ready
1971 * for set_configuration as well as eventual disconnect.
1973 printf("registered gadget driver '%s'\n", DRIVER_NAME);
1981 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1985 /* don't disconnect drivers more than once */
1986 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1988 dev->gadget.speed = USB_SPEED_UNKNOWN;
1990 /* prevent new request submissions, kill any outstanding requests */
1991 for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1992 struct pxa25x_ep *ep = &dev->ep[i];
1995 nuke(ep, -ESHUTDOWN);
1999 /* report disconnect; the driver is already quiesced */
2001 driver->disconnect(&dev->gadget);
2003 /* re-init driver-visible data structures */
2007 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2009 struct pxa25x_udc *dev = the_controller;
2013 if (!driver || driver != dev->driver || !driver->unbind)
2016 local_irq_disable();
2019 stop_activity(dev, driver);
2022 driver->unbind(&dev->gadget);
2025 printf("unregistered gadget driver '%s'\n", DRIVER_NAME);
2028 the_controller = NULL;
2030 clrbits_le32(CKEN, CKEN11_USB);
2035 extern void udc_disconnect(void)
2037 setbits_le32(CKEN, CKEN11_USB);
2038 udc_clear_mask_UDCCR(UDCCR_UDE);
2039 udc_command(PXA2XX_UDC_CMD_DISCONNECT);
2040 clrbits_le32(CKEN, CKEN11_USB);
2043 /*-------------------------------------------------------------------------*/
2046 usb_gadget_handle_interrupts(int index)
2048 return pxa25x_udc_irq();