drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
   4  * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
   5  *
   6  * Copyright (C) 2009 for Samsung Electronics
   7  *
   8  * BSP Support for Samsung's UDC driver
   9  * available at:
  10  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  11  *
  12  * State machine bugfixes:
  13  * Marek Szyprowski <m.szyprowski@samsung.com>
  14  *
  15  * Ported to u-boot:
  16  * Marek Szyprowski <m.szyprowski@samsung.com>
  17  * Lukasz Majewski <l.majewski@samsumg.com>
  18  */
  19
  20 #include <common.h>
  21 #include <cpu_func.h>
  22
  23 static u8 clear_feature_num;
  24 int clear_feature_flag;
  25
  26 /* Bulk-Only Mass Storage Reset (class-specific request) */
  27 #define GET_MAX_LUN_REQUEST     0xFE
  28 #define BOT_RESET_REQUEST       0xFF
  29
  30 static inline void dwc2_udc_ep0_zlp(struct dwc2_udc *dev)
  31 {
  32         u32 ep_ctrl;
  33
  34         writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), &reg->in_endp[EP0_CON].diepdma);
  35         writel(DIEPT_SIZ_PKT_CNT(1), &reg->in_endp[EP0_CON].dieptsiz);
  36
  37         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  38         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  39                &reg->in_endp[EP0_CON].diepctl);
  40
  41         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  42                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  43         dev->ep0state = WAIT_FOR_IN_COMPLETE;
  44 }
  45
  46 static void dwc2_udc_pre_setup(void)
  47 {
  48         u32 ep_ctrl;
  49
  50         debug_cond(DEBUG_IN_EP,
  51                    "%s : Prepare Setup packets.\n", __func__);
  52
  53         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  54                &reg->out_endp[EP0_CON].doeptsiz);
  55         writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), &reg->out_endp[EP0_CON].doepdma);
  56
  57         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  58         writel(ep_ctrl|DEPCTL_EPENA, &reg->out_endp[EP0_CON].doepctl);
  59
  60         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  61                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  62         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  63                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  64
  65 }
  66
  67 static inline void dwc2_ep0_complete_out(void)
  68 {
  69         u32 ep_ctrl;
  70
  71         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  72                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  73         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  74                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  75
  76         debug_cond(DEBUG_IN_EP,
  77                 "%s : Prepare Complete Out packet.\n", __func__);
  78
  79         writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest),
  80                &reg->out_endp[EP0_CON].doeptsiz);
  81         writel(phys_to_bus((unsigned long)usb_ctrl_dma_addr), &reg->out_endp[EP0_CON].doepdma);
  82
  83         ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  84         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
  85                &reg->out_endp[EP0_CON].doepctl);
  86
  87         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DIEPCTL0 = 0x%x\n",
  88                 __func__, readl(&reg->in_endp[EP0_CON].diepctl));
  89         debug_cond(DEBUG_EP0 != 0, "%s:EP0 ZLP DOEPCTL0 = 0x%x\n",
  90                 __func__, readl(&reg->out_endp[EP0_CON].doepctl));
  91
  92 }
  93
  94
  95 static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req)
  96 {
  97         u32 *buf, ctrl;
  98         u32 length, pktcnt;
  99         u32 ep_num = ep_index(ep);
 100
 101         buf = req->req.buf + req->req.actual;
 102         length = min_t(u32, req->req.length - req->req.actual,
 103                        ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket);
 104
 105         ep->len = length;
 106         ep->dma_buf = buf;
 107
 108         if (ep_num == EP0_CON || length == 0)
 109                 pktcnt = 1;
 110         else
 111                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 112
 113         ctrl =  readl(&reg->out_endp[ep_num].doepctl);
 114
 115         invalidate_dcache_range((unsigned long) ep->dma_buf,
 116                                 (unsigned long) ep->dma_buf +
 117                                 ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
 118
 119         writel(phys_to_bus((unsigned long)ep->dma_buf), &reg->out_endp[ep_num].doepdma);
 120         writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
 121                &reg->out_endp[ep_num].doeptsiz);
 122         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->out_endp[ep_num].doepctl);
 123
 124         debug_cond(DEBUG_OUT_EP != 0,
 125                    "%s: EP%d RX DMA start : DOEPDMA = 0x%x,"
 126                    "DOEPTSIZ = 0x%x, DOEPCTL = 0x%x\n"
 127                    "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 128                    __func__, ep_num,
 129                    readl(&reg->out_endp[ep_num].doepdma),
 130                    readl(&reg->out_endp[ep_num].doeptsiz),
 131                    readl(&reg->out_endp[ep_num].doepctl),
 132                    buf, pktcnt, length);
 133         return 0;
 134
 135 }
 136
 137 static int setdma_tx(struct dwc2_ep *ep, struct dwc2_request *req)
 138 {
 139         u32 *buf, ctrl = 0;
 140         u32 length, pktcnt;
 141         u32 ep_num = ep_index(ep);
 142
 143         buf = req->req.buf + req->req.actual;
 144         length = req->req.length - req->req.actual;
 145
 146         if (ep_num == EP0_CON)
 147                 length = min(length, (u32)ep_maxpacket(ep));
 148
 149         ep->len = length;
 150         ep->dma_buf = buf;
 151
 152         flush_dcache_range((unsigned long) ep->dma_buf,
 153                            (unsigned long) ep->dma_buf +
 154                            ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
 155
 156         if (length == 0)
 157                 pktcnt = 1;
 158         else
 159                 pktcnt = (length - 1)/(ep->ep.maxpacket) + 1;
 160
 161         /* Flush the endpoint's Tx FIFO */
 162         writel(TX_FIFO_NUMBER(ep->fifo_num), &reg->grstctl);
 163         writel(TX_FIFO_NUMBER(ep->fifo_num) | TX_FIFO_FLUSH, &reg->grstctl);
 164         while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
 165                 ;
 166
 167         writel(phys_to_bus((unsigned long)ep->dma_buf), &reg->in_endp[ep_num].diepdma);
 168         writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
 169                &reg->in_endp[ep_num].dieptsiz);
 170
 171         ctrl = readl(&reg->in_endp[ep_num].diepctl);
 172
 173         /* Write the FIFO number to be used for this endpoint */
 174         ctrl &= DIEPCTL_TX_FIFO_NUM_MASK;
 175         ctrl |= DIEPCTL_TX_FIFO_NUM(ep->fifo_num);
 176
 177         /* Clear reserved (Next EP) bits */
 178         ctrl = (ctrl&~(EP_MASK<<DEPCTL_NEXT_EP_BIT));
 179
 180         writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, &reg->in_endp[ep_num].diepctl);
 181
 182         debug_cond(DEBUG_IN_EP,
 183                 "%s:EP%d TX DMA start : DIEPDMA0 = 0x%x,"
 184                 "DIEPTSIZ0 = 0x%x, DIEPCTL0 = 0x%x\n"
 185                 "\tbuf = 0x%p, pktcnt = %d, xfersize = %d\n",
 186                 __func__, ep_num,
 187                 readl(&reg->in_endp[ep_num].diepdma),
 188                 readl(&reg->in_endp[ep_num].dieptsiz),
 189                 readl(&reg->in_endp[ep_num].diepctl),
 190                 buf, pktcnt, length);
 191
 192         return length;
 193 }
 194
 195 static void complete_rx(struct dwc2_udc *dev, u8 ep_num)
 196 {
 197         struct dwc2_ep *ep = &dev->ep[ep_num];
 198         struct dwc2_request *req = NULL;
 199         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 200
 201         if (list_empty(&ep->queue)) {
 202                 debug_cond(DEBUG_OUT_EP != 0,
 203                            "%s: RX DMA done : NULL REQ on OUT EP-%d\n",
 204                            __func__, ep_num);
 205                 return;
 206
 207         }
 208
 209         req = list_entry(ep->queue.next, struct dwc2_request, queue);
 210         ep_tsr = readl(&reg->out_endp[ep_num].doeptsiz);
 211
 212         if (ep_num == EP0_CON)
 213                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP0);
 214         else
 215                 xfer_size = (ep_tsr & DOEPT_SIZ_XFER_SIZE_MAX_EP);
 216
 217         xfer_size = ep->len - xfer_size;
 218
 219         /*
 220          * NOTE:
 221          *
 222          * Please be careful with proper buffer allocation for USB request,
 223          * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
 224          * with starting address, but also its size shall be a cache line
 225          * multiplication.
 226          *
 227          * This will prevent from corruption of data allocated immediatelly
 228          * before or after the buffer.
 229          *
 230          * For armv7, the cache_v7.c provides proper code to emit "ERROR"
 231          * message to warn users.
 232          */
 233         invalidate_dcache_range((unsigned long) ep->dma_buf,
 234                                 (unsigned long) ep->dma_buf +
 235                                 ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
 236
 237         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 238         is_short = !!(xfer_size % ep->ep.maxpacket);
 239
 240         debug_cond(DEBUG_OUT_EP != 0,
 241                    "%s: RX DMA done : ep = %d, rx bytes = %d/%d, "
 242                    "is_short = %d, DOEPTSIZ = 0x%x, remained bytes = %d\n",
 243                    __func__, ep_num, req->req.actual, req->req.length,
 244                    is_short, ep_tsr, req->req.length - req->req.actual);
 245
 246         if (is_short || req->req.actual == req->req.length) {
 247                 if (ep_num == EP0_CON && dev->ep0state == DATA_STATE_RECV) {
 248                         debug_cond(DEBUG_OUT_EP != 0, " => Send ZLP\n");
 249                         dwc2_udc_ep0_zlp(dev);
 250                         /* packet will be completed in complete_tx() */
 251                         dev->ep0state = WAIT_FOR_IN_COMPLETE;
 252                 } else {
 253                         done(ep, req, 0);
 254
 255                         if (!list_empty(&ep->queue)) {
 256                                 req = list_entry(ep->queue.next,
 257                                         struct dwc2_request, queue);
 258                                 debug_cond(DEBUG_OUT_EP != 0,
 259                                            "%s: Next Rx request start...\n",
 260                                            __func__);
 261                                 setdma_rx(ep, req);
 262                         }
 263                 }
 264         } else
 265                 setdma_rx(ep, req);
 266 }
 267
 268 static void complete_tx(struct dwc2_udc *dev, u8 ep_num)
 269 {
 270         struct dwc2_ep *ep = &dev->ep[ep_num];
 271         struct dwc2_request *req;
 272         u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
 273         u32 last;
 274
 275         if (dev->ep0state == WAIT_FOR_NULL_COMPLETE) {
 276                 dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 277                 dwc2_ep0_complete_out();
 278                 return;
 279         }
 280
 281         if (list_empty(&ep->queue)) {
 282                 debug_cond(DEBUG_IN_EP,
 283                         "%s: TX DMA done : NULL REQ on IN EP-%d\n",
 284                         __func__, ep_num);
 285                 return;
 286
 287         }
 288
 289         req = list_entry(ep->queue.next, struct dwc2_request, queue);
 290
 291         ep_tsr = readl(&reg->in_endp[ep_num].dieptsiz);
 292
 293         xfer_size = ep->len;
 294         is_short = (xfer_size < ep->ep.maxpacket);
 295         req->req.actual += min(xfer_size, req->req.length - req->req.actual);
 296
 297         debug_cond(DEBUG_IN_EP,
 298                 "%s: TX DMA done : ep = %d, tx bytes = %d/%d, "
 299                 "is_short = %d, DIEPTSIZ = 0x%x, remained bytes = %d\n",
 300                 __func__, ep_num, req->req.actual, req->req.length,
 301                 is_short, ep_tsr, req->req.length - req->req.actual);
 302
 303         if (ep_num == 0) {
 304                 if (dev->ep0state == DATA_STATE_XMIT) {
 305                         debug_cond(DEBUG_IN_EP,
 306                                 "%s: ep_num = %d, ep0stat =="
 307                                 "DATA_STATE_XMIT\n",
 308                                 __func__, ep_num);
 309                         last = write_fifo_ep0(ep, req);
 310                         if (last)
 311                                 dev->ep0state = WAIT_FOR_COMPLETE;
 312                 } else if (dev->ep0state == WAIT_FOR_IN_COMPLETE) {
 313                         debug_cond(DEBUG_IN_EP,
 314                                 "%s: ep_num = %d, completing request\n",
 315                                 __func__, ep_num);
 316                         done(ep, req, 0);
 317                         dev->ep0state = WAIT_FOR_SETUP;
 318                 } else if (dev->ep0state == WAIT_FOR_COMPLETE) {
 319                         debug_cond(DEBUG_IN_EP,
 320                                 "%s: ep_num = %d, completing request\n",
 321                                 __func__, ep_num);
 322                         done(ep, req, 0);
 323                         dev->ep0state = WAIT_FOR_OUT_COMPLETE;
 324                         dwc2_ep0_complete_out();
 325                 } else {
 326                         debug_cond(DEBUG_IN_EP,
 327                                 "%s: ep_num = %d, invalid ep state\n",
 328                                 __func__, ep_num);
 329                 }
 330                 return;
 331         }
 332
 333         if (req->req.actual == req->req.length)
 334                 done(ep, req, 0);
 335
 336         if (!list_empty(&ep->queue)) {
 337                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 338                 debug_cond(DEBUG_IN_EP,
 339                         "%s: Next Tx request start...\n", __func__);
 340                 setdma_tx(ep, req);
 341         }
 342 }
 343
 344 static inline void dwc2_udc_check_tx_queue(struct dwc2_udc *dev, u8 ep_num)
 345 {
 346         struct dwc2_ep *ep = &dev->ep[ep_num];
 347         struct dwc2_request *req;
 348
 349         debug_cond(DEBUG_IN_EP,
 350                 "%s: Check queue, ep_num = %d\n", __func__, ep_num);
 351
 352         if (!list_empty(&ep->queue)) {
 353                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 354                 debug_cond(DEBUG_IN_EP,
 355                         "%s: Next Tx request(0x%p) start...\n",
 356                         __func__, req);
 357
 358                 if (ep_is_in(ep))
 359                         setdma_tx(ep, req);
 360                 else
 361                         setdma_rx(ep, req);
 362         } else {
 363                 debug_cond(DEBUG_IN_EP,
 364                         "%s: NULL REQ on IN EP-%d\n", __func__, ep_num);
 365
 366                 return;
 367         }
 368
 369 }
 370
 371 static void process_ep_in_intr(struct dwc2_udc *dev)
 372 {
 373         u32 ep_intr, ep_intr_status;
 374         u8 ep_num = 0;
 375
 376         ep_intr = readl(&reg->daint);
 377         debug_cond(DEBUG_IN_EP,
 378                 "*** %s: EP In interrupt : DAINT = 0x%x\n", __func__, ep_intr);
 379
 380         ep_intr &= DAINT_MASK;
 381
 382         while (ep_intr) {
 383                 if (ep_intr & DAINT_IN_EP_INT(1)) {
 384                         ep_intr_status = readl(&reg->in_endp[ep_num].diepint);
 385                         debug_cond(DEBUG_IN_EP,
 386                                    "\tEP%d-IN : DIEPINT = 0x%x\n",
 387                                    ep_num, ep_intr_status);
 388
 389                         /* Interrupt Clear */
 390                         writel(ep_intr_status, &reg->in_endp[ep_num].diepint);
 391
 392                         if (ep_intr_status & TRANSFER_DONE) {
 393                                 complete_tx(dev, ep_num);
 394
 395                                 if (ep_num == 0) {
 396                                         if (dev->ep0state ==
 397                                             WAIT_FOR_IN_COMPLETE)
 398                                                 dev->ep0state = WAIT_FOR_SETUP;
 399
 400                                         if (dev->ep0state == WAIT_FOR_SETUP)
 401                                                 dwc2_udc_pre_setup();
 402
 403                                         /* continue transfer after
 404                                            set_clear_halt for DMA mode */
 405                                         if (clear_feature_flag == 1) {
 406                                                 dwc2_udc_check_tx_queue(dev,
 407                                                         clear_feature_num);
 408                                                 clear_feature_flag = 0;
 409                                         }
 410                                 }
 411                         }
 412                 }
 413                 ep_num++;
 414                 ep_intr >>= 1;
 415         }
 416 }
 417
 418 static void process_ep_out_intr(struct dwc2_udc *dev)
 419 {
 420         u32 ep_intr, ep_intr_status;
 421         u8 ep_num = 0;
 422
 423         ep_intr = readl(&reg->daint);
 424         debug_cond(DEBUG_OUT_EP != 0,
 425                    "*** %s: EP OUT interrupt : DAINT = 0x%x\n",
 426                    __func__, ep_intr);
 427
 428         ep_intr = (ep_intr >> DAINT_OUT_BIT) & DAINT_MASK;
 429
 430         while (ep_intr) {
 431                 if (ep_intr & 0x1) {
 432                         ep_intr_status = readl(&reg->out_endp[ep_num].doepint);
 433                         debug_cond(DEBUG_OUT_EP != 0,
 434                                    "\tEP%d-OUT : DOEPINT = 0x%x\n",
 435                                    ep_num, ep_intr_status);
 436
 437                         /* Interrupt Clear */
 438                         writel(ep_intr_status, &reg->out_endp[ep_num].doepint);
 439
 440                         if (ep_num == 0) {
 441                                 if (ep_intr_status & TRANSFER_DONE) {
 442                                         if (dev->ep0state !=
 443                                             WAIT_FOR_OUT_COMPLETE)
 444                                                 complete_rx(dev, ep_num);
 445                                         else {
 446                                                 dev->ep0state = WAIT_FOR_SETUP;
 447                                                 dwc2_udc_pre_setup();
 448                                         }
 449                                 }
 450
 451                                 if (ep_intr_status &
 452                                     CTRL_OUT_EP_SETUP_PHASE_DONE) {
 453                                         debug_cond(DEBUG_OUT_EP != 0,
 454                                                    "SETUP packet arrived\n");
 455                                         dwc2_handle_ep0(dev);
 456                                 }
 457                         } else {
 458                                 if (ep_intr_status & TRANSFER_DONE)
 459                                         complete_rx(dev, ep_num);
 460                         }
 461                 }
 462                 ep_num++;
 463                 ep_intr >>= 1;
 464         }
 465 }
 466
 467 /*
 468  *      usb client interrupt handler.
 469  */
 470 static int dwc2_udc_irq(int irq, void *_dev)
 471 {
 472         struct dwc2_udc *dev = _dev;
 473         u32 intr_status, gotgint;
 474         u32 usb_status, gintmsk;
 475         unsigned long flags = 0;
 476
 477         spin_lock_irqsave(&dev->lock, flags);
 478
 479         intr_status = readl(&reg->gintsts);
 480         gintmsk = readl(&reg->gintmsk);
 481
 482         debug_cond(DEBUG_ISR,
 483                   "\n*** %s : GINTSTS=0x%x(on state %s), GINTMSK : 0x%x,"
 484                   "DAINT : 0x%x, DAINTMSK : 0x%x\n",
 485                   __func__, intr_status, state_names[dev->ep0state], gintmsk,
 486                   readl(&reg->daint), readl(&reg->daintmsk));
 487
 488         if (!intr_status) {
 489                 spin_unlock_irqrestore(&dev->lock, flags);
 490                 return IRQ_HANDLED;
 491         }
 492
 493         if (intr_status & INT_ENUMDONE) {
 494                 debug_cond(DEBUG_ISR, "\tSpeed Detection interrupt\n");
 495
 496                 writel(INT_ENUMDONE, &reg->gintsts);
 497                 usb_status = (readl(&reg->dsts) & 0x6);
 498
 499                 if (usb_status & (USB_FULL_30_60MHZ | USB_FULL_48MHZ)) {
 500                         debug_cond(DEBUG_ISR,
 501                                    "\t\tFull Speed Detection\n");
 502                         set_max_pktsize(dev, USB_SPEED_FULL);
 503
 504                 } else {
 505                         debug_cond(DEBUG_ISR,
 506                                 "\t\tHigh Speed Detection : 0x%x\n",
 507                                 usb_status);
 508                         set_max_pktsize(dev, USB_SPEED_HIGH);
 509                 }
 510         }
 511
 512         if (intr_status & INT_EARLY_SUSPEND) {
 513                 debug_cond(DEBUG_ISR, "\tEarly suspend interrupt\n");
 514                 writel(INT_EARLY_SUSPEND, &reg->gintsts);
 515         }
 516
 517         if (intr_status & INT_SUSPEND) {
 518                 usb_status = readl(&reg->dsts);
 519                 debug_cond(DEBUG_ISR,
 520                         "\tSuspend interrupt :(DSTS):0x%x\n", usb_status);
 521                 writel(INT_SUSPEND, &reg->gintsts);
 522
 523                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 524                     && dev->driver) {
 525                         if (dev->driver->suspend)
 526                                 dev->driver->suspend(&dev->gadget);
 527                 }
 528         }
 529
 530         if (intr_status & INT_OTG) {
 531                 gotgint = readl(&reg->gotgint);
 532                 debug_cond(DEBUG_ISR,
 533                            "\tOTG interrupt: (GOTGINT):0x%x\n", gotgint);
 534
 535                 if (gotgint & GOTGINT_SES_END_DET) {
 536                         debug_cond(DEBUG_ISR, "\t\tSession End Detected\n");
 537                         /* Let gadget detect disconnected state */
 538                         if (dev->driver->disconnect) {
 539                                 spin_unlock_irqrestore(&dev->lock, flags);
 540                                 dev->driver->disconnect(&dev->gadget);
 541                                 spin_lock_irqsave(&dev->lock, flags);
 542                         }
 543                 }
 544                 writel(gotgint, &reg->gotgint);
 545         }
 546
 547         if (intr_status & INT_RESUME) {
 548                 debug_cond(DEBUG_ISR, "\tResume interrupt\n");
 549                 writel(INT_RESUME, &reg->gintsts);
 550
 551                 if (dev->gadget.speed != USB_SPEED_UNKNOWN
 552                     && dev->driver
 553                     && dev->driver->resume) {
 554
 555                         dev->driver->resume(&dev->gadget);
 556                 }
 557         }
 558
 559         if (intr_status & INT_RESET) {
 560                 usb_status = readl(&reg->gotgctl);
 561                 debug_cond(DEBUG_ISR,
 562                         "\tReset interrupt - (GOTGCTL):0x%x\n", usb_status);
 563                 writel(INT_RESET, &reg->gintsts);
 564
 565                 if ((usb_status & 0xc0000) == (0x3 << 18)) {
 566                         if (reset_available) {
 567                                 debug_cond(DEBUG_ISR,
 568                                         "\t\tOTG core got reset (%d)!!\n",
 569                                         reset_available);
 570                                 reconfig_usbd(dev);
 571                                 dev->ep0state = WAIT_FOR_SETUP;
 572                                 reset_available = 0;
 573                                 dwc2_udc_pre_setup();
 574                         } else
 575                                 reset_available = 1;
 576
 577                 } else {
 578                         reset_available = 1;
 579                         debug_cond(DEBUG_ISR,
 580                                    "\t\tRESET handling skipped\n");
 581                 }
 582         }
 583
 584         if (intr_status & INT_IN_EP)
 585                 process_ep_in_intr(dev);
 586
 587         if (intr_status & INT_OUT_EP)
 588                 process_ep_out_intr(dev);
 589
 590         spin_unlock_irqrestore(&dev->lock, flags);
 591
 592         return IRQ_HANDLED;
 593 }
 594
 595 /** Queue one request
 596  *  Kickstart transfer if needed
 597  */
 598 static int dwc2_queue(struct usb_ep *_ep, struct usb_request *_req,
 599                          gfp_t gfp_flags)
 600 {
 601         struct dwc2_request *req;
 602         struct dwc2_ep *ep;
 603         struct dwc2_udc *dev;
 604         unsigned long flags = 0;
 605         u32 ep_num, gintsts;
 606
 607         req = container_of(_req, struct dwc2_request, req);
 608         if (unlikely(!_req || !_req->complete || !_req->buf
 609                      || !list_empty(&req->queue))) {
 610
 611                 debug("%s: bad params\n", __func__);
 612                 return -EINVAL;
 613         }
 614
 615         ep = container_of(_ep, struct dwc2_ep, ep);
 616
 617         if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 618
 619                 debug("%s: bad ep: %s, %d, %p\n", __func__,
 620                       ep->ep.name, !ep->desc, _ep);
 621                 return -EINVAL;
 622         }
 623
 624         ep_num = ep_index(ep);
 625         dev = ep->dev;
 626         if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 627
 628                 debug("%s: bogus device state %p\n", __func__, dev->driver);
 629                 return -ESHUTDOWN;
 630         }
 631
 632         spin_lock_irqsave(&dev->lock, flags);
 633
 634         _req->status = -EINPROGRESS;
 635         _req->actual = 0;
 636
 637         /* kickstart this i/o queue? */
 638         debug("\n*** %s: %s-%s req = %p, len = %d, buf = %p"
 639                 "Q empty = %d, stopped = %d\n",
 640                 __func__, _ep->name, ep_is_in(ep) ? "in" : "out",
 641                 _req, _req->length, _req->buf,
 642                 list_empty(&ep->queue), ep->stopped);
 643
 644 #ifdef DEBUG
 645         {
 646                 int i, len = _req->length;
 647
 648                 printf("pkt = ");
 649                 if (len > 64)
 650                         len = 64;
 651                 for (i = 0; i < len; i++) {
 652                         printf("%02x", ((u8 *)_req->buf)[i]);
 653                         if ((i & 7) == 7)
 654                                 printf(" ");
 655                 }
 656                 printf("\n");
 657         }
 658 #endif
 659
 660         if (list_empty(&ep->queue) && !ep->stopped) {
 661
 662                 if (ep_num == 0) {
 663                         /* EP0 */
 664                         list_add_tail(&req->queue, &ep->queue);
 665                         dwc2_ep0_kick(dev, ep);
 666                         req = 0;
 667
 668                 } else if (ep_is_in(ep)) {
 669                         gintsts = readl(&reg->gintsts);
 670                         debug_cond(DEBUG_IN_EP,
 671                                    "%s: ep_is_in, DWC2_UDC_OTG_GINTSTS=0x%x\n",
 672                                    __func__, gintsts);
 673
 674                         setdma_tx(ep, req);
 675                 } else {
 676                         gintsts = readl(&reg->gintsts);
 677                         debug_cond(DEBUG_OUT_EP != 0,
 678                                    "%s:ep_is_out, DWC2_UDC_OTG_GINTSTS=0x%x\n",
 679                                    __func__, gintsts);
 680
 681                         setdma_rx(ep, req);
 682                 }
 683         }
 684
 685         /* pio or dma irq handler advances the queue. */
 686         if (likely(req != 0))
 687                 list_add_tail(&req->queue, &ep->queue);
 688
 689         spin_unlock_irqrestore(&dev->lock, flags);
 690
 691         return 0;
 692 }
 693
 694 /****************************************************************/
 695 /* End Point 0 related functions                                */
 696 /****************************************************************/
 697
 698 /* return:  0 = still running, 1 = completed, negative = errno */
 699 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req)
 700 {
 701         u32 max;
 702         unsigned count;
 703         int is_last;
 704
 705         max = ep_maxpacket(ep);
 706
 707         debug_cond(DEBUG_EP0 != 0, "%s: max = %d\n", __func__, max);
 708
 709         count = setdma_tx(ep, req);
 710
 711         /* last packet is usually short (or a zlp) */
 712         if (likely(count != max))
 713                 is_last = 1;
 714         else {
 715                 if (likely(req->req.length != req->req.actual + count)
 716                     || req->req.zero)
 717                         is_last = 0;
 718                 else
 719                         is_last = 1;
 720         }
 721
 722         debug_cond(DEBUG_EP0 != 0,
 723                    "%s: wrote %s %d bytes%s %d left %p\n", __func__,
 724                    ep->ep.name, count,
 725                    is_last ? "/L" : "",
 726                    req->req.length - req->req.actual - count, req);
 727
 728         /* requests complete when all IN data is in the FIFO */
 729         if (is_last) {
 730                 ep->dev->ep0state = WAIT_FOR_SETUP;
 731                 return 1;
 732         }
 733
 734         return 0;
 735 }
 736
 737 static int dwc2_fifo_read(struct dwc2_ep *ep, void *cp, int max)
 738 {
 739         invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
 740                                 ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
 741
 742         debug_cond(DEBUG_EP0 != 0,
 743                    "%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
 744                    max, ep_index(ep), cp);
 745
 746         return max;
 747 }
 748
 749 /**
 750  * udc_set_address - set the USB address for this device
 751  * @address:
 752  *
 753  * Called from control endpoint function
 754  * after it decodes a set address setup packet.
 755  */
 756 static void udc_set_address(struct dwc2_udc *dev, unsigned char address)
 757 {
 758         u32 ctrl = readl(&reg->dcfg);
 759         writel(DEVICE_ADDRESS(address) | ctrl, &reg->dcfg);
 760
 761         dwc2_udc_ep0_zlp(dev);
 762
 763         debug_cond(DEBUG_EP0 != 0,
 764                    "%s: USB OTG 2.0 Device address=%d, DCFG=0x%x\n",
 765                    __func__, address, readl(&reg->dcfg));
 766
 767         dev->usb_address = address;
 768 }
 769
 770 static inline void dwc2_udc_ep0_set_stall(struct dwc2_ep *ep)
 771 {
 772         struct dwc2_udc *dev;
 773         u32             ep_ctrl = 0;
 774
 775         dev = ep->dev;
 776         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 777
 778         /* set the disable and stall bits */
 779         if (ep_ctrl & DEPCTL_EPENA)
 780                 ep_ctrl |= DEPCTL_EPDIS;
 781
 782         ep_ctrl |= DEPCTL_STALL;
 783
 784         writel(ep_ctrl, &reg->in_endp[EP0_CON].diepctl);
 785
 786         debug_cond(DEBUG_EP0 != 0,
 787                    "%s: set ep%d stall, DIEPCTL0 = 0x%p\n",
 788                    __func__, ep_index(ep), &reg->in_endp[EP0_CON].diepctl);
 789         /*
 790          * The application can only set this bit, and the core clears it,
 791          * when a SETUP token is received for this endpoint
 792          */
 793         dev->ep0state = WAIT_FOR_SETUP;
 794
 795         dwc2_udc_pre_setup();
 796 }
 797
 798 static void dwc2_ep0_read(struct dwc2_udc *dev)
 799 {
 800         struct dwc2_request *req;
 801         struct dwc2_ep *ep = &dev->ep[0];
 802
 803         if (!list_empty(&ep->queue)) {
 804                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 805
 806         } else {
 807                 debug("%s: ---> BUG\n", __func__);
 808                 BUG();
 809                 return;
 810         }
 811
 812         debug_cond(DEBUG_EP0 != 0,
 813                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 814                    __func__, req, req->req.length, req->req.actual);
 815
 816         if (req->req.length == 0) {
 817                 /* zlp for Set_configuration, Set_interface,
 818                  * or Bulk-Only mass storge reset */
 819
 820                 ep->len = 0;
 821                 dwc2_udc_ep0_zlp(dev);
 822
 823                 debug_cond(DEBUG_EP0 != 0,
 824                            "%s: req.length = 0, bRequest = %d\n",
 825                            __func__, usb_ctrl->bRequest);
 826                 return;
 827         }
 828
 829         setdma_rx(ep, req);
 830 }
 831
 832 /*
 833  * DATA_STATE_XMIT
 834  */
 835 static int dwc2_ep0_write(struct dwc2_udc *dev)
 836 {
 837         struct dwc2_request *req;
 838         struct dwc2_ep *ep = &dev->ep[0];
 839         int ret, need_zlp = 0;
 840
 841         if (list_empty(&ep->queue))
 842                 req = 0;
 843         else
 844                 req = list_entry(ep->queue.next, struct dwc2_request, queue);
 845
 846         if (!req) {
 847                 debug_cond(DEBUG_EP0 != 0, "%s: NULL REQ\n", __func__);
 848                 return 0;
 849         }
 850
 851         debug_cond(DEBUG_EP0 != 0,
 852                    "%s: req = %p, req.length = 0x%x, req.actual = 0x%x\n",
 853                    __func__, req, req->req.length, req->req.actual);
 854
 855         if (req->req.length - req->req.actual == ep0_fifo_size) {
 856                 /* Next write will end with the packet size, */
 857                 /* so we need Zero-length-packet */
 858                 need_zlp = 1;
 859         }
 860
 861         ret = write_fifo_ep0(ep, req);
 862
 863         if ((ret == 1) && !need_zlp) {
 864                 /* Last packet */
 865                 dev->ep0state = WAIT_FOR_COMPLETE;
 866                 debug_cond(DEBUG_EP0 != 0,
 867                            "%s: finished, waiting for status\n", __func__);
 868
 869         } else {
 870                 dev->ep0state = DATA_STATE_XMIT;
 871                 debug_cond(DEBUG_EP0 != 0,
 872                            "%s: not finished\n", __func__);
 873         }
 874
 875         return 1;
 876 }
 877
 878 static int dwc2_udc_get_status(struct dwc2_udc *dev,
 879                 struct usb_ctrlrequest *crq)
 880 {
 881         u8 ep_num = crq->wIndex & 0x7F;
 882         u16 g_status = 0;
 883         u32 ep_ctrl;
 884
 885         debug_cond(DEBUG_SETUP != 0,
 886                    "%s: *** USB_REQ_GET_STATUS\n", __func__);
 887         printf("crq->brequest:0x%x\n", crq->bRequestType & USB_RECIP_MASK);
 888         switch (crq->bRequestType & USB_RECIP_MASK) {
 889         case USB_RECIP_INTERFACE:
 890                 g_status = 0;
 891                 debug_cond(DEBUG_SETUP != 0,
 892                            "\tGET_STATUS:USB_RECIP_INTERFACE, g_stauts = %d\n",
 893                            g_status);
 894                 break;
 895
 896         case USB_RECIP_DEVICE:
 897                 g_status = 0x1; /* Self powered */
 898                 debug_cond(DEBUG_SETUP != 0,
 899                            "\tGET_STATUS: USB_RECIP_DEVICE, g_stauts = %d\n",
 900                            g_status);
 901                 break;
 902
 903         case USB_RECIP_ENDPOINT:
 904                 if (crq->wLength > 2) {
 905                         debug_cond(DEBUG_SETUP != 0,
 906                                    "\tGET_STATUS:Not support EP or wLength\n");
 907                         return 1;
 908                 }
 909
 910                 g_status = dev->ep[ep_num].stopped;
 911                 debug_cond(DEBUG_SETUP != 0,
 912                            "\tGET_STATUS: USB_RECIP_ENDPOINT, g_stauts = %d\n",
 913                            g_status);
 914
 915                 break;
 916
 917         default:
 918                 return 1;
 919         }
 920
 921         memcpy(usb_ctrl, &g_status, sizeof(g_status));
 922
 923         flush_dcache_range((unsigned long) usb_ctrl,
 924                            (unsigned long) usb_ctrl +
 925                            ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
 926
 927         writel(phys_to_bus(usb_ctrl_dma_addr), &reg->in_endp[EP0_CON].diepdma);
 928         writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
 929                &reg->in_endp[EP0_CON].dieptsiz);
 930
 931         ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
 932         writel(ep_ctrl|DEPCTL_EPENA|DEPCTL_CNAK,
 933                &reg->in_endp[EP0_CON].diepctl);
 934         dev->ep0state = WAIT_FOR_NULL_COMPLETE;
 935
 936         return 0;
 937 }
 938
 939 static void dwc2_udc_set_nak(struct dwc2_ep *ep)
 940 {
 941         u8              ep_num;
 942         u32             ep_ctrl = 0;
 943
 944         ep_num = ep_index(ep);
 945         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 946
 947         if (ep_is_in(ep)) {
 948                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 949                 ep_ctrl |= DEPCTL_SNAK;
 950                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 951                 debug("%s: set NAK, DIEPCTL%d = 0x%x\n",
 952                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 953         } else {
 954                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 955                 ep_ctrl |= DEPCTL_SNAK;
 956                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 957                 debug("%s: set NAK, DOEPCTL%d = 0x%x\n",
 958                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 959         }
 960
 961         return;
 962 }
 963
 964
 965 static void dwc2_udc_ep_set_stall(struct dwc2_ep *ep)
 966 {
 967         u8              ep_num;
 968         u32             ep_ctrl = 0;
 969
 970         ep_num = ep_index(ep);
 971         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
 972
 973         if (ep_is_in(ep)) {
 974                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
 975
 976                 /* set the disable and stall bits */
 977                 if (ep_ctrl & DEPCTL_EPENA)
 978                         ep_ctrl |= DEPCTL_EPDIS;
 979
 980                 ep_ctrl |= DEPCTL_STALL;
 981
 982                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
 983                 debug("%s: set stall, DIEPCTL%d = 0x%x\n",
 984                       __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
 985
 986         } else {
 987                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
 988
 989                 /* set the stall bit */
 990                 ep_ctrl |= DEPCTL_STALL;
 991
 992                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
 993                 debug("%s: set stall, DOEPCTL%d = 0x%x\n",
 994                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
 995         }
 996
 997         return;
 998 }
 999
1000 static void dwc2_udc_ep_clear_stall(struct dwc2_ep *ep)
1001 {
1002         u8              ep_num;
1003         u32             ep_ctrl = 0;
1004
1005         ep_num = ep_index(ep);
1006         debug("%s: ep_num = %d, ep_type = %d\n", __func__, ep_num, ep->ep_type);
1007
1008         if (ep_is_in(ep)) {
1009                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1010
1011                 /* clear stall bit */
1012                 ep_ctrl &= ~DEPCTL_STALL;
1013
1014                 /*
1015                  * USB Spec 9.4.5: For endpoints using data toggle, regardless
1016                  * of whether an endpoint has the Halt feature set, a
1017                  * ClearFeature(ENDPOINT_HALT) request always results in the
1018                  * data toggle being reinitialized to DATA0.
1019                  */
1020                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1021                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1022                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1023                 }
1024
1025                 writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1026                 debug("%s: cleared stall, DIEPCTL%d = 0x%x\n",
1027                         __func__, ep_num, readl(&reg->in_endp[ep_num].diepctl));
1028
1029         } else {
1030                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1031
1032                 /* clear stall bit */
1033                 ep_ctrl &= ~DEPCTL_STALL;
1034
1035                 if (ep->bmAttributes == USB_ENDPOINT_XFER_INT
1036                     || ep->bmAttributes == USB_ENDPOINT_XFER_BULK) {
1037                         ep_ctrl |= DEPCTL_SETD0PID; /* DATA0 */
1038                 }
1039
1040                 writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1041                 debug("%s: cleared stall, DOEPCTL%d = 0x%x\n",
1042                       __func__, ep_num, readl(&reg->out_endp[ep_num].doepctl));
1043         }
1044
1045         return;
1046 }
1047
1048 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value)
1049 {
1050         struct dwc2_ep  *ep;
1051         struct dwc2_udc *dev;
1052         unsigned long   flags = 0;
1053         u8              ep_num;
1054
1055         ep = container_of(_ep, struct dwc2_ep, ep);
1056         ep_num = ep_index(ep);
1057
1058         if (unlikely(!_ep || !ep->desc || ep_num == EP0_CON ||
1059                      ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC)) {
1060                 debug("%s: %s bad ep or descriptor\n", __func__, ep->ep.name);
1061                 return -EINVAL;
1062         }
1063
1064         /* Attempt to halt IN ep will fail if any transfer requests
1065          * are still queue */
1066         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1067                 debug("%s: %s queue not empty, req = %p\n",
1068                         __func__, ep->ep.name,
1069                         list_entry(ep->queue.next, struct dwc2_request, queue));
1070
1071                 return -EAGAIN;
1072         }
1073
1074         dev = ep->dev;
1075         debug("%s: ep_num = %d, value = %d\n", __func__, ep_num, value);
1076
1077         spin_lock_irqsave(&dev->lock, flags);
1078
1079         if (value == 0) {
1080                 ep->stopped = 0;
1081                 dwc2_udc_ep_clear_stall(ep);
1082         } else {
1083                 if (ep_num == 0)
1084                         dev->ep0state = WAIT_FOR_SETUP;
1085
1086                 ep->stopped = 1;
1087                 dwc2_udc_ep_set_stall(ep);
1088         }
1089
1090         spin_unlock_irqrestore(&dev->lock, flags);
1091
1092         return 0;
1093 }
1094
1095 static void dwc2_udc_ep_activate(struct dwc2_ep *ep)
1096 {
1097         u8 ep_num;
1098         u32 ep_ctrl = 0, daintmsk = 0;
1099
1100         ep_num = ep_index(ep);
1101
1102         /* Read DEPCTLn register */
1103         if (ep_is_in(ep)) {
1104                 ep_ctrl = readl(&reg->in_endp[ep_num].diepctl);
1105                 daintmsk = 1 << ep_num;
1106         } else {
1107                 ep_ctrl = readl(&reg->out_endp[ep_num].doepctl);
1108                 daintmsk = (1 << ep_num) << DAINT_OUT_BIT;
1109         }
1110
1111         debug("%s: EPCTRL%d = 0x%x, ep_is_in = %d\n",
1112                 __func__, ep_num, ep_ctrl, ep_is_in(ep));
1113
1114         /* If the EP is already active don't change the EP Control
1115          * register. */
1116         if (!(ep_ctrl & DEPCTL_USBACTEP)) {
1117                 ep_ctrl = (ep_ctrl & ~DEPCTL_TYPE_MASK) |
1118                         (ep->bmAttributes << DEPCTL_TYPE_BIT);
1119                 ep_ctrl = (ep_ctrl & ~DEPCTL_MPS_MASK) |
1120                         (ep->ep.maxpacket << DEPCTL_MPS_BIT);
1121                 ep_ctrl |= (DEPCTL_SETD0PID | DEPCTL_USBACTEP | DEPCTL_SNAK);
1122
1123                 if (ep_is_in(ep)) {
1124                         writel(ep_ctrl, &reg->in_endp[ep_num].diepctl);
1125                         debug("%s: USB Ative EP%d, DIEPCTRL%d = 0x%x\n",
1126                               __func__, ep_num, ep_num,
1127                               readl(&reg->in_endp[ep_num].diepctl));
1128                 } else {
1129                         writel(ep_ctrl, &reg->out_endp[ep_num].doepctl);
1130                         debug("%s: USB Ative EP%d, DOEPCTRL%d = 0x%x\n",
1131                               __func__, ep_num, ep_num,
1132                               readl(&reg->out_endp[ep_num].doepctl));
1133                 }
1134         }
1135
1136         /* Unmask EP Interrtupt */
1137         writel(readl(&reg->daintmsk)|daintmsk, &reg->daintmsk);
1138         debug("%s: DAINTMSK = 0x%x\n", __func__, readl(&reg->daintmsk));
1139
1140 }
1141
1142 static int dwc2_udc_clear_feature(struct usb_ep *_ep)
1143 {
1144         struct dwc2_udc *dev;
1145         struct dwc2_ep  *ep;
1146         u8              ep_num;
1147
1148         ep = container_of(_ep, struct dwc2_ep, ep);
1149         ep_num = ep_index(ep);
1150
1151         dev = ep->dev;
1152         debug_cond(DEBUG_SETUP != 0,
1153                    "%s: ep_num = %d, is_in = %d, clear_feature_flag = %d\n",
1154                    __func__, ep_num, ep_is_in(ep), clear_feature_flag);
1155
1156         if (usb_ctrl->wLength != 0) {
1157                 debug_cond(DEBUG_SETUP != 0,
1158                            "\tCLEAR_FEATURE: wLength is not zero.....\n");
1159                 return 1;
1160         }
1161
1162         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1163         case USB_RECIP_DEVICE:
1164                 switch (usb_ctrl->wValue) {
1165                 case USB_DEVICE_REMOTE_WAKEUP:
1166                         debug_cond(DEBUG_SETUP != 0,
1167                                    "\tOFF:USB_DEVICE_REMOTE_WAKEUP\n");
1168                         break;
1169
1170                 case USB_DEVICE_TEST_MODE:
1171                         debug_cond(DEBUG_SETUP != 0,
1172                                    "\tCLEAR_FEATURE: USB_DEVICE_TEST_MODE\n");
1173                         /** @todo Add CLEAR_FEATURE for TEST modes. */
1174                         break;
1175                 }
1176
1177                 dwc2_udc_ep0_zlp(dev);
1178                 break;
1179
1180         case USB_RECIP_ENDPOINT:
1181                 debug_cond(DEBUG_SETUP != 0,
1182                            "\tCLEAR_FEATURE:USB_RECIP_ENDPOINT, wValue = %d\n",
1183                            usb_ctrl->wValue);
1184
1185                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1186                         if (ep_num == 0) {
1187                                 dwc2_udc_ep0_set_stall(ep);
1188                                 return 0;
1189                         }
1190
1191                         dwc2_udc_ep0_zlp(dev);
1192
1193                         dwc2_udc_ep_clear_stall(ep);
1194                         dwc2_udc_ep_activate(ep);
1195                         ep->stopped = 0;
1196
1197                         clear_feature_num = ep_num;
1198                         clear_feature_flag = 1;
1199                 }
1200                 break;
1201         }
1202
1203         return 0;
1204 }
1205
1206 static int dwc2_udc_set_feature(struct usb_ep *_ep)
1207 {
1208         struct dwc2_udc *dev;
1209         struct dwc2_ep  *ep;
1210         u8              ep_num;
1211
1212         ep = container_of(_ep, struct dwc2_ep, ep);
1213         ep_num = ep_index(ep);
1214         dev = ep->dev;
1215
1216         debug_cond(DEBUG_SETUP != 0,
1217                    "%s: *** USB_REQ_SET_FEATURE , ep_num = %d\n",
1218                     __func__, ep_num);
1219
1220         if (usb_ctrl->wLength != 0) {
1221                 debug_cond(DEBUG_SETUP != 0,
1222                            "\tSET_FEATURE: wLength is not zero.....\n");
1223                 return 1;
1224         }
1225
1226         switch (usb_ctrl->bRequestType & USB_RECIP_MASK) {
1227         case USB_RECIP_DEVICE:
1228                 switch (usb_ctrl->wValue) {
1229                 case USB_DEVICE_REMOTE_WAKEUP:
1230                         debug_cond(DEBUG_SETUP != 0,
1231                                    "\tSET_FEATURE:USB_DEVICE_REMOTE_WAKEUP\n");
1232                         break;
1233                 case USB_DEVICE_B_HNP_ENABLE:
1234                         debug_cond(DEBUG_SETUP != 0,
1235                                    "\tSET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
1236                         break;
1237
1238                 case USB_DEVICE_A_HNP_SUPPORT:
1239                         /* RH port supports HNP */
1240                         debug_cond(DEBUG_SETUP != 0,
1241                                    "\tSET_FEATURE:USB_DEVICE_A_HNP_SUPPORT\n");
1242                         break;
1243
1244                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
1245                         /* other RH port does */
1246                         debug_cond(DEBUG_SETUP != 0,
1247                                    "\tSET: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
1248                         break;
1249                 }
1250
1251                 dwc2_udc_ep0_zlp(dev);
1252                 return 0;
1253
1254         case USB_RECIP_INTERFACE:
1255                 debug_cond(DEBUG_SETUP != 0,
1256                            "\tSET_FEATURE: USB_RECIP_INTERFACE\n");
1257                 break;
1258
1259         case USB_RECIP_ENDPOINT:
1260                 debug_cond(DEBUG_SETUP != 0,
1261                            "\tSET_FEATURE: USB_RECIP_ENDPOINT\n");
1262                 if (usb_ctrl->wValue == USB_ENDPOINT_HALT) {
1263                         if (ep_num == 0) {
1264                                 dwc2_udc_ep0_set_stall(ep);
1265                                 return 0;
1266                         }
1267                         ep->stopped = 1;
1268                         dwc2_udc_ep_set_stall(ep);
1269                 }
1270
1271                 dwc2_udc_ep0_zlp(dev);
1272                 return 0;
1273         }
1274
1275         return 1;
1276 }
1277
1278 /*
1279  * WAIT_FOR_SETUP (OUT_PKT_RDY)
1280  */
1281 static void dwc2_ep0_setup(struct dwc2_udc *dev)
1282 {
1283         struct dwc2_ep *ep = &dev->ep[0];
1284         int i;
1285         u8 ep_num;
1286
1287         /* Nuke all previous transfers */
1288         nuke(ep, -EPROTO);
1289
1290         /* read control req from fifo (8 bytes) */
1291         dwc2_fifo_read(ep, usb_ctrl, 8);
1292
1293         debug_cond(DEBUG_SETUP != 0,
1294                    "%s: bRequestType = 0x%x(%s), bRequest = 0x%x"
1295                    "\twLength = 0x%x, wValue = 0x%x, wIndex= 0x%x\n",
1296                    __func__, usb_ctrl->bRequestType,
1297                    (usb_ctrl->bRequestType & USB_DIR_IN) ? "IN" : "OUT",
1298                    usb_ctrl->bRequest,
1299                    usb_ctrl->wLength, usb_ctrl->wValue, usb_ctrl->wIndex);
1300
1301 #ifdef DEBUG
1302         {
1303                 int i, len = sizeof(*usb_ctrl);
1304                 char *p = (char *)usb_ctrl;
1305
1306                 printf("pkt = ");
1307                 for (i = 0; i < len; i++) {
1308                         printf("%02x", ((u8 *)p)[i]);
1309                         if ((i & 7) == 7)
1310                                 printf(" ");
1311                 }
1312                 printf("\n");
1313         }
1314 #endif
1315
1316         if (usb_ctrl->bRequest == GET_MAX_LUN_REQUEST &&
1317             usb_ctrl->wLength != 1) {
1318                 debug_cond(DEBUG_SETUP != 0,
1319                            "\t%s:GET_MAX_LUN_REQUEST:invalid",
1320                            __func__);
1321                 debug_cond(DEBUG_SETUP != 0,
1322                            "wLength = %d, setup returned\n",
1323                            usb_ctrl->wLength);
1324
1325                 dwc2_udc_ep0_set_stall(ep);
1326                 dev->ep0state = WAIT_FOR_SETUP;
1327
1328                 return;
1329         } else if (usb_ctrl->bRequest == BOT_RESET_REQUEST &&
1330                  usb_ctrl->wLength != 0) {
1331                 /* Bulk-Only *mass storge reset of class-specific request */
1332                 debug_cond(DEBUG_SETUP != 0,
1333                            "%s:BOT Rest:invalid wLength =%d, setup returned\n",
1334                            __func__, usb_ctrl->wLength);
1335
1336                 dwc2_udc_ep0_set_stall(ep);
1337                 dev->ep0state = WAIT_FOR_SETUP;
1338
1339                 return;
1340         }
1341
1342         /* Set direction of EP0 */
1343         if (likely(usb_ctrl->bRequestType & USB_DIR_IN)) {
1344                 ep->bEndpointAddress |= USB_DIR_IN;
1345         } else {
1346                 ep->bEndpointAddress &= ~USB_DIR_IN;
1347         }
1348         /* cope with automagic for some standard requests. */
1349         dev->req_std = (usb_ctrl->bRequestType & USB_TYPE_MASK)
1350                 == USB_TYPE_STANDARD;
1351
1352         dev->req_pending = 1;
1353
1354         /* Handle some SETUP packets ourselves */
1355         if (dev->req_std) {
1356                 switch (usb_ctrl->bRequest) {
1357                 case USB_REQ_SET_ADDRESS:
1358                 debug_cond(DEBUG_SETUP != 0,
1359                            "%s: *** USB_REQ_SET_ADDRESS (%d)\n",
1360                            __func__, usb_ctrl->wValue);
1361                         if (usb_ctrl->bRequestType
1362                                 != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1363                                 break;
1364
1365                         udc_set_address(dev, usb_ctrl->wValue);
1366                         return;
1367
1368                 case USB_REQ_SET_CONFIGURATION:
1369                         debug_cond(DEBUG_SETUP != 0,
1370                                    "=====================================\n");
1371                         debug_cond(DEBUG_SETUP != 0,
1372                                    "%s: USB_REQ_SET_CONFIGURATION (%d)\n",
1373                                    __func__, usb_ctrl->wValue);
1374
1375                         if (usb_ctrl->bRequestType == USB_RECIP_DEVICE)
1376                                 reset_available = 1;
1377
1378                         break;
1379
1380                 case USB_REQ_GET_DESCRIPTOR:
1381                         debug_cond(DEBUG_SETUP != 0,
1382                                    "%s: *** USB_REQ_GET_DESCRIPTOR\n",
1383                                    __func__);
1384                         break;
1385
1386                 case USB_REQ_SET_INTERFACE:
1387                         debug_cond(DEBUG_SETUP != 0,
1388                                    "%s: *** USB_REQ_SET_INTERFACE (%d)\n",
1389                                    __func__, usb_ctrl->wValue);
1390
1391                         if (usb_ctrl->bRequestType == USB_RECIP_INTERFACE)
1392                                 reset_available = 1;
1393
1394                         break;
1395
1396                 case USB_REQ_GET_CONFIGURATION:
1397                         debug_cond(DEBUG_SETUP != 0,
1398                                    "%s: *** USB_REQ_GET_CONFIGURATION\n",
1399                                    __func__);
1400                         break;
1401
1402                 case USB_REQ_GET_STATUS:
1403                         if (!dwc2_udc_get_status(dev, usb_ctrl))
1404                                 return;
1405
1406                         break;
1407
1408                 case USB_REQ_CLEAR_FEATURE:
1409                         ep_num = usb_ctrl->wIndex & 0x7f;
1410
1411                         if (!dwc2_udc_clear_feature(&dev->ep[ep_num].ep))
1412                                 return;
1413
1414                         break;
1415
1416                 case USB_REQ_SET_FEATURE:
1417                         ep_num = usb_ctrl->wIndex & 0x7f;
1418
1419                         if (!dwc2_udc_set_feature(&dev->ep[ep_num].ep))
1420                                 return;
1421
1422                         break;
1423
1424                 default:
1425                         debug_cond(DEBUG_SETUP != 0,
1426                                    "%s: *** Default of usb_ctrl->bRequest=0x%x"
1427                                    "happened.\n", __func__, usb_ctrl->bRequest);
1428                         break;
1429                 }
1430         }
1431
1432
1433         if (likely(dev->driver)) {
1434                 /* device-2-host (IN) or no data setup command,
1435                  * process immediately */
1436                 debug_cond(DEBUG_SETUP != 0,
1437                            "%s:usb_ctrlreq will be passed to fsg_setup()\n",
1438                             __func__);
1439
1440                 spin_unlock(&dev->lock);
1441                 i = dev->driver->setup(&dev->gadget, usb_ctrl);
1442                 spin_lock(&dev->lock);
1443
1444                 if (i < 0) {
1445                         /* setup processing failed, force stall */
1446                         dwc2_udc_ep0_set_stall(ep);
1447                         dev->ep0state = WAIT_FOR_SETUP;
1448
1449                         debug_cond(DEBUG_SETUP != 0,
1450                                    "\tdev->driver->setup failed (%d),"
1451                                     " bRequest = %d\n",
1452                                 i, usb_ctrl->bRequest);
1453
1454
1455                 } else if (dev->req_pending) {
1456                         dev->req_pending = 0;
1457                         debug_cond(DEBUG_SETUP != 0,
1458                                    "\tdev->req_pending...\n");
1459                 }
1460
1461                 debug_cond(DEBUG_SETUP != 0,
1462                            "\tep0state = %s\n", state_names[dev->ep0state]);
1463
1464         }
1465 }
1466
1467 /*
1468  * handle ep0 interrupt
1469  */
1470 static void dwc2_handle_ep0(struct dwc2_udc *dev)
1471 {
1472         if (dev->ep0state == WAIT_FOR_SETUP) {
1473                 debug_cond(DEBUG_OUT_EP != 0,
1474                            "%s: WAIT_FOR_SETUP\n", __func__);
1475                 dwc2_ep0_setup(dev);
1476
1477         } else {
1478                 debug_cond(DEBUG_OUT_EP != 0,
1479                            "%s: strange state!!(state = %s)\n",
1480                         __func__, state_names[dev->ep0state]);
1481         }
1482 }
1483
1484 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep)
1485 {
1486         debug_cond(DEBUG_EP0 != 0,
1487                    "%s: ep_is_in = %d\n", __func__, ep_is_in(ep));
1488         if (ep_is_in(ep)) {
1489                 dev->ep0state = DATA_STATE_XMIT;
1490                 dwc2_ep0_write(dev);
1491
1492         } else {
1493                 dev->ep0state = DATA_STATE_RECV;
1494                 dwc2_ep0_read(dev);
1495         }
1496 }