drivers/usb/gadget/dwc2_udc_otg_phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/usb/gadget/dwc2_udc_otg.c
   4  * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
   5  *
   6  * Copyright (C) 2008 for Samsung Electronics
   7  *
   8  * BSP Support for Samsung's UDC driver
   9  * available at:
  10  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  11  *
  12  * State machine bugfixes:
  13  * Marek Szyprowski <m.szyprowski@samsung.com>
  14  *
  15  * Ported to u-boot:
  16  * Marek Szyprowski <m.szyprowski@samsung.com>
  17  * Lukasz Majewski <l.majewski@samsumg.com>
  18  */
  19
  20 #include <common.h>
  21 #include <linux/errno.h>
  22 #include <linux/list.h>
  23 #include <malloc.h>
  24
  25 #include <linux/usb/ch9.h>
  26 #include <linux/usb/gadget.h>
  27
  28 #include <asm/byteorder.h>
  29 #include <asm/unaligned.h>
  30 #include <asm/io.h>
  31
  32 #include <asm/mach-types.h>
  33
  34 #include "dwc2_udc_otg_regs.h"
  35 #include "dwc2_udc_otg_priv.h"
  36
  37 #include <usb/dwc2_udc.h>
  38
  39 void otg_phy_init(struct dwc2_udc *dev)
  40 {
  41         unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
  42         struct dwc2_usbotg_phy *phy =
  43                 (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
  44
  45         dev->pdata->phy_control(1);
  46
  47         /* USB PHY0 Enable */
  48         printf("USB PHY0 Enable\n");
  49
  50         /* Enable PHY */
  51         writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
  52
  53         if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
  54                 writel((readl(&phy->phypwr)
  55                         &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
  56                         &~FORCE_SUSPEND_0), &phy->phypwr);
  57         else /* C110 GONI */
  58                 writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
  59                         &~FORCE_SUSPEND_0), &phy->phypwr);
  60
  61         if (s5p_cpu_id == 0x4412)
  62                 writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
  63                         EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
  64                        &phy->phyclk); /* PLL 24Mhz */
  65         else
  66                 writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
  67                        CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
  68
  69         writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
  70                | PHY_SW_RST0, &phy->rstcon);
  71         udelay(10);
  72         writel(readl(&phy->rstcon)
  73                &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
  74         udelay(10);
  75 }
  76
  77 void otg_phy_off(struct dwc2_udc *dev)
  78 {
  79         unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
  80         struct dwc2_usbotg_phy *phy =
  81                 (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
  82
  83         /* reset controller just in case */
  84         writel(PHY_SW_RST0, &phy->rstcon);
  85         udelay(20);
  86         writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
  87         udelay(20);
  88
  89         writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
  90                | FORCE_SUSPEND_0, &phy->phypwr);
  91
  92         writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
  93
  94         writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
  95               &phy->phyclk);
  96
  97         udelay(10000);
  98
  99         dev->pdata->phy_control(0);
 100 }