drivers/usb/gadget/designware_udc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Based on drivers/usb/gadget/omap1510_udc.c
   4  * TI OMAP1510 USB bus interface driver
   5  *
   6  * (C) Copyright 2009
   7  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   8  */
   9
  10 #include <common.h>
  11 #include <serial.h>
  12 #include <asm/io.h>
  13
  14 #include <env.h>
  15 #include <usbdevice.h>
  16 #include "ep0.h"
  17 #include <usb/designware_udc.h>
  18 #include <usb/udc.h>
  19 #include <asm/arch/hardware.h>
  20
  21 #define UDC_INIT_MDELAY         80      /* Device settle delay */
  22
  23 /* Some kind of debugging output... */
  24 #ifndef DEBUG_DWUSBTTY
  25 #define UDCDBG(str)
  26 #define UDCDBGA(fmt, args...)
  27 #else
  28 #define UDCDBG(str) serial_printf(str "\n")
  29 #define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
  30 #endif
  31
  32 static struct urb *ep0_urb;
  33 static struct usb_device_instance *udc_device;
  34
  35 static struct plug_regs *const plug_regs_p =
  36     (struct plug_regs * const)CONFIG_SYS_PLUG_BASE;
  37 static struct udc_regs *const udc_regs_p =
  38     (struct udc_regs * const)CONFIG_SYS_USBD_BASE;
  39 static struct udc_endp_regs *const outep_regs_p =
  40     &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0];
  41 static struct udc_endp_regs *const inep_regs_p =
  42     &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0];
  43
  44 /*
  45  * udc_state_transition - Write the next packet to TxFIFO.
  46  * @initial:    Initial state.
  47  * @final:      Final state.
  48  *
  49  * Helper function to implement device state changes. The device states and
  50  * the events that transition between them are:
  51  *
  52  *                              STATE_ATTACHED
  53  *                              ||      /\
  54  *                              \/      ||
  55  *      DEVICE_HUB_CONFIGURED                   DEVICE_HUB_RESET
  56  *                              ||      /\
  57  *                              \/      ||
  58  *                              STATE_POWERED
  59  *                              ||      /\
  60  *                              \/      ||
  61  *      DEVICE_RESET                            DEVICE_POWER_INTERRUPTION
  62  *                              ||      /\
  63  *                              \/      ||
  64  *                              STATE_DEFAULT
  65  *                              ||      /\
  66  *                              \/      ||
  67  *      DEVICE_ADDRESS_ASSIGNED                 DEVICE_RESET
  68  *                              ||      /\
  69  *                              \/      ||
  70  *                              STATE_ADDRESSED
  71  *                              ||      /\
  72  *                              \/      ||
  73  *      DEVICE_CONFIGURED                       DEVICE_DE_CONFIGURED
  74  *                              ||      /\
  75  *                              \/      ||
  76  *                              STATE_CONFIGURED
  77  *
  78  * udc_state_transition transitions up (in the direction from STATE_ATTACHED
  79  * to STATE_CONFIGURED) from the specified initial state to the specified final
  80  * state, passing through each intermediate state on the way. If the initial
  81  * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
  82  * no state transitions will take place.
  83  *
  84  * udc_state_transition also transitions down (in the direction from
  85  * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
  86  * specified final state, passing through each intermediate state on the way.
  87  * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
  88  * state, then no state transitions will take place.
  89  *
  90  * This function must only be called with interrupts disabled.
  91  */
  92 static void udc_state_transition(usb_device_state_t initial,
  93                                  usb_device_state_t final)
  94 {
  95         if (initial < final) {
  96                 switch (initial) {
  97                 case STATE_ATTACHED:
  98                         usbd_device_event_irq(udc_device,
  99                                               DEVICE_HUB_CONFIGURED, 0);
 100                         if (final == STATE_POWERED)
 101                                 break;
 102                 case STATE_POWERED:
 103                         usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
 104                         if (final == STATE_DEFAULT)
 105                                 break;
 106                 case STATE_DEFAULT:
 107                         usbd_device_event_irq(udc_device,
 108                                               DEVICE_ADDRESS_ASSIGNED, 0);
 109                         if (final == STATE_ADDRESSED)
 110                                 break;
 111                 case STATE_ADDRESSED:
 112                         usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
 113                 case STATE_CONFIGURED:
 114                         break;
 115                 default:
 116                         break;
 117                 }
 118         } else if (initial > final) {
 119                 switch (initial) {
 120                 case STATE_CONFIGURED:
 121                         usbd_device_event_irq(udc_device,
 122                                               DEVICE_DE_CONFIGURED, 0);
 123                         if (final == STATE_ADDRESSED)
 124                                 break;
 125                 case STATE_ADDRESSED:
 126                         usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
 127                         if (final == STATE_DEFAULT)
 128                                 break;
 129                 case STATE_DEFAULT:
 130                         usbd_device_event_irq(udc_device,
 131                                               DEVICE_POWER_INTERRUPTION, 0);
 132                         if (final == STATE_POWERED)
 133                                 break;
 134                 case STATE_POWERED:
 135                         usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
 136                 case STATE_ATTACHED:
 137                         break;
 138                 default:
 139                         break;
 140                 }
 141         }
 142 }
 143
 144 /* Stall endpoint */
 145 static void udc_stall_ep(u32 ep_num)
 146 {
 147         writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
 148                &inep_regs_p[ep_num].endp_cntl);
 149
 150         writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
 151                &outep_regs_p[ep_num].endp_cntl);
 152 }
 153
 154 static void *get_fifo(int ep_num, int in)
 155 {
 156         u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE;
 157
 158         switch (ep_num) {
 159         case UDC_EP3:
 160                 fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn);
 161                 /* break intentionally left out */
 162
 163         case UDC_EP1:
 164                 fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn);
 165                 /* break intentionally left out */
 166
 167         case UDC_EP0:
 168         default:
 169                 if (in) {
 170                         fifo_ptr +=
 171                             readl(&outep_regs_p[2].endp_maxpacksize) >> 16;
 172                         /* break intentionally left out */
 173                 } else {
 174                         break;
 175                 }
 176
 177         case UDC_EP2:
 178                 fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16;
 179                 /* break intentionally left out */
 180         }
 181
 182         return (void *)fifo_ptr;
 183 }
 184
 185 static int usbgetpckfromfifo(int epNum, u8 *bufp, u32 len)
 186 {
 187         u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0);
 188         u32 i, nw, nb;
 189         u32 *wrdp;
 190         u8 *bytp;
 191         u32 tmp[128];
 192
 193         if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY)
 194                 return -1;
 195
 196         nw = len / sizeof(u32);
 197         nb = len % sizeof(u32);
 198
 199         /* use tmp buf if bufp is not word aligned */
 200         if ((int)bufp & 0x3)
 201                 wrdp = (u32 *)&tmp[0];
 202         else
 203                 wrdp = (u32 *)bufp;
 204
 205         for (i = 0; i < nw; i++) {
 206                 writel(readl(fifo_ptr), wrdp);
 207                 wrdp++;
 208         }
 209
 210         bytp = (u8 *)wrdp;
 211         for (i = 0; i < nb; i++) {
 212                 writeb(readb(fifo_ptr), bytp);
 213                 fifo_ptr++;
 214                 bytp++;
 215         }
 216         readl(&outep_regs_p[epNum].write_done);
 217
 218         /* copy back tmp buffer to bufp if bufp is not word aligned */
 219         if ((int)bufp & 0x3)
 220                 memcpy(bufp, tmp, len);
 221
 222         return 0;
 223 }
 224
 225 static void usbputpcktofifo(int epNum, u8 *bufp, u32 len)
 226 {
 227         u32 i, nw, nb;
 228         u32 *wrdp;
 229         u8 *bytp;
 230         u8 *fifo_ptr = get_fifo(epNum, 1);
 231
 232         nw = len / sizeof(int);
 233         nb = len % sizeof(int);
 234         wrdp = (u32 *)bufp;
 235         for (i = 0; i < nw; i++) {
 236                 writel(*wrdp, fifo_ptr);
 237                 wrdp++;
 238         }
 239
 240         bytp = (u8 *)wrdp;
 241         for (i = 0; i < nb; i++) {
 242                 writeb(*bytp, fifo_ptr);
 243                 fifo_ptr++;
 244                 bytp++;
 245         }
 246 }
 247
 248 /*
 249  * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO.
 250  * @endpoint:           Endpoint pointer.
 251  *
 252  * If the endpoint has an active tx_urb, then the next packet of data from the
 253  * URB is written to the tx FIFO.  The total amount of data in the urb is given
 254  * by urb->actual_length.  The maximum amount of data that can be sent in any
 255  * one packet is given by endpoint->tx_packetSize.  The number of data bytes
 256  * from this URB that have already been transmitted is given by endpoint->sent.
 257  * endpoint->last is updated by this routine with the number of data bytes
 258  * transmitted in this packet.
 259  *
 260  */
 261 static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance
 262                                        *endpoint)
 263 {
 264         struct urb *urb = endpoint->tx_urb;
 265         int align;
 266
 267         if (urb) {
 268                 u32 last;
 269
 270                 UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
 271                         urb->buffer, urb->buffer_length, urb->actual_length);
 272
 273                 last = min_t(u32, urb->actual_length - endpoint->sent,
 274                              endpoint->tx_packetSize);
 275
 276                 if (last) {
 277                         u8 *cp = urb->buffer + endpoint->sent;
 278
 279                         /*
 280                          * This ensures that USBD packet fifo is accessed
 281                          * - through word aligned pointer or
 282                          * - through non word aligned pointer but only
 283                          *   with a max length to make the next packet
 284                          *   word aligned
 285                          */
 286
 287                         align = ((ulong)cp % sizeof(int));
 288                         if (align)
 289                                 last = min(last, sizeof(int) - align);
 290
 291                         UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
 292                                 endpoint->sent, endpoint->tx_packetSize, last);
 293
 294                         usbputpcktofifo(endpoint->endpoint_address &
 295                                         USB_ENDPOINT_NUMBER_MASK, cp, last);
 296                 }
 297                 endpoint->last = last;
 298         }
 299 }
 300
 301 /*
 302  * Handle SETUP USB interrupt.
 303  * This function implements TRM Figure 14-14.
 304  */
 305 static void dw_udc_setup(struct usb_endpoint_instance *endpoint)
 306 {
 307         u8 *datap = (u8 *)&ep0_urb->device_request;
 308         int ep_addr = endpoint->endpoint_address;
 309
 310         UDCDBG("-> Entering device setup");
 311         usbgetpckfromfifo(ep_addr, datap, 8);
 312
 313         /* Try to process setup packet */
 314         if (ep0_recv_setup(ep0_urb)) {
 315                 /* Not a setup packet, stall next EP0 transaction */
 316                 udc_stall_ep(0);
 317                 UDCDBG("can't parse setup packet, still waiting for setup");
 318                 return;
 319         }
 320
 321         /* Check direction */
 322         if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK)
 323             == USB_REQ_HOST2DEVICE) {
 324                 UDCDBG("control write on EP0");
 325                 if (le16_to_cpu(ep0_urb->device_request.wLength)) {
 326                         /* Stall this request */
 327                         UDCDBG("Stalling unsupported EP0 control write data "
 328                                "stage.");
 329                         udc_stall_ep(0);
 330                 }
 331         } else {
 332
 333                 UDCDBG("control read on EP0");
 334                 /*
 335                  * The ep0_recv_setup function has already placed our response
 336                  * packet data in ep0_urb->buffer and the packet length in
 337                  * ep0_urb->actual_length.
 338                  */
 339                 endpoint->tx_urb = ep0_urb;
 340                 endpoint->sent = 0;
 341                 /*
 342                  * Write packet data to the FIFO.  dw_write_noniso_tx_fifo
 343                  * will update endpoint->last with the number of bytes written
 344                  * to the FIFO.
 345                  */
 346                 dw_write_noniso_tx_fifo(endpoint);
 347
 348                 writel(0x0, &inep_regs_p[ep_addr].write_done);
 349         }
 350
 351         udc_unset_nak(endpoint->endpoint_address);
 352
 353         UDCDBG("<- Leaving device setup");
 354 }
 355
 356 /*
 357  * Handle endpoint 0 RX interrupt
 358  */
 359 static void dw_udc_ep0_rx(struct usb_endpoint_instance *endpoint)
 360 {
 361         u8 dummy[64];
 362
 363         UDCDBG("RX on EP0");
 364
 365         /* Check direction */
 366         if ((ep0_urb->device_request.bmRequestType
 367              & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) {
 368                 /*
 369                  * This rx interrupt must be for a control write data
 370                  * stage packet.
 371                  *
 372                  * We don't support control write data stages.
 373                  * We should never end up here.
 374                  */
 375
 376                 UDCDBG("Stalling unexpected EP0 control write "
 377                        "data stage packet");
 378                 udc_stall_ep(0);
 379         } else {
 380                 /*
 381                  * This rx interrupt must be for a control read status
 382                  * stage packet.
 383                  */
 384                 UDCDBG("ACK on EP0 control read status stage packet");
 385                 u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff;
 386                 usbgetpckfromfifo(0, dummy, len);
 387         }
 388 }
 389
 390 /*
 391  * Handle endpoint 0 TX interrupt
 392  */
 393 static void dw_udc_ep0_tx(struct usb_endpoint_instance *endpoint)
 394 {
 395         struct usb_device_request *request = &ep0_urb->device_request;
 396         int ep_addr;
 397
 398         UDCDBG("TX on EP0");
 399
 400         /* Check direction */
 401         if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) ==
 402             USB_REQ_HOST2DEVICE) {
 403                 /*
 404                  * This tx interrupt must be for a control write status
 405                  * stage packet.
 406                  */
 407                 UDCDBG("ACK on EP0 control write status stage packet");
 408         } else {
 409                 /*
 410                  * This tx interrupt must be for a control read data
 411                  * stage packet.
 412                  */
 413                 int wLength = le16_to_cpu(request->wLength);
 414
 415                 /*
 416                  * Update our count of bytes sent so far in this
 417                  * transfer.
 418                  */
 419                 endpoint->sent += endpoint->last;
 420
 421                 /*
 422                  * We are finished with this transfer if we have sent
 423                  * all of the bytes in our tx urb (urb->actual_length)
 424                  * unless we need a zero-length terminating packet.  We
 425                  * need a zero-length terminating packet if we returned
 426                  * fewer bytes than were requested (wLength) by the host,
 427                  * and the number of bytes we returned is an exact
 428                  * multiple of the packet size endpoint->tx_packetSize.
 429                  */
 430                 if ((endpoint->sent == ep0_urb->actual_length) &&
 431                     ((ep0_urb->actual_length == wLength) ||
 432                      (endpoint->last != endpoint->tx_packetSize))) {
 433                         /* Done with control read data stage. */
 434                         UDCDBG("control read data stage complete");
 435                 } else {
 436                         /*
 437                          * We still have another packet of data to send
 438                          * in this control read data stage or else we
 439                          * need a zero-length terminating packet.
 440                          */
 441                         UDCDBG("ACK control read data stage packet");
 442                         dw_write_noniso_tx_fifo(endpoint);
 443
 444                         ep_addr = endpoint->endpoint_address;
 445                         writel(0x0, &inep_regs_p[ep_addr].write_done);
 446                 }
 447         }
 448 }
 449
 450 static struct usb_endpoint_instance *dw_find_ep(int ep)
 451 {
 452         int i;
 453
 454         for (i = 0; i < udc_device->bus->max_endpoints; i++) {
 455                 if ((udc_device->bus->endpoint_array[i].endpoint_address &
 456                      USB_ENDPOINT_NUMBER_MASK) == ep)
 457                         return &udc_device->bus->endpoint_array[i];
 458         }
 459         return NULL;
 460 }
 461
 462 /*
 463  * Handle RX transaction on non-ISO endpoint.
 464  * The ep argument is a physical endpoint number for a non-ISO IN endpoint
 465  * in the range 1 to 15.
 466  */
 467 static void dw_udc_epn_rx(int ep)
 468 {
 469         int nbytes = 0;
 470         struct urb *urb;
 471         struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
 472
 473         if (endpoint) {
 474                 urb = endpoint->rcv_urb;
 475
 476                 if (urb) {
 477                         u8 *cp = urb->buffer + urb->actual_length;
 478
 479                         nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) &
 480                             0xfff;
 481                         usbgetpckfromfifo(ep, cp, nbytes);
 482                         usbd_rcv_complete(endpoint, nbytes, 0);
 483                 }
 484         }
 485 }
 486
 487 /*
 488  * Handle TX transaction on non-ISO endpoint.
 489  * The ep argument is a physical endpoint number for a non-ISO IN endpoint
 490  * in the range 16 to 30.
 491  */
 492 static void dw_udc_epn_tx(int ep)
 493 {
 494         struct usb_endpoint_instance *endpoint = dw_find_ep(ep);
 495
 496         if (!endpoint)
 497                 return;
 498
 499         /*
 500          * We need to transmit a terminating zero-length packet now if
 501          * we have sent all of the data in this URB and the transfer
 502          * size was an exact multiple of the packet size.
 503          */
 504         if (endpoint->tx_urb &&
 505             (endpoint->last == endpoint->tx_packetSize) &&
 506             (endpoint->tx_urb->actual_length - endpoint->sent -
 507              endpoint->last == 0)) {
 508                 /* handle zero length packet here */
 509                 writel(0x0, &inep_regs_p[ep].write_done);
 510
 511         }
 512
 513         if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
 514                 /* retire the data that was just sent */
 515                 usbd_tx_complete(endpoint);
 516                 /*
 517                  * Check to see if we have more data ready to transmit
 518                  * now.
 519                  */
 520                 if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
 521                         /* write data to FIFO */
 522                         dw_write_noniso_tx_fifo(endpoint);
 523                         writel(0x0, &inep_regs_p[ep].write_done);
 524
 525                 } else if (endpoint->tx_urb
 526                            && (endpoint->tx_urb->actual_length == 0)) {
 527                         /* udc_set_nak(ep); */
 528                 }
 529         }
 530 }
 531
 532 /*
 533  * Start of public functions.
 534  */
 535
 536 /* Called to start packet transmission. */
 537 int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
 538 {
 539         udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK);
 540         return 0;
 541 }
 542
 543 /* Start to initialize h/w stuff */
 544 int udc_init(void)
 545 {
 546         int i;
 547         u32 plug_st;
 548
 549         udc_device = NULL;
 550
 551         UDCDBG("starting");
 552
 553         readl(&plug_regs_p->plug_pending);
 554
 555         for (i = 0; i < UDC_INIT_MDELAY; i++)
 556                 udelay(1000);
 557
 558         plug_st = readl(&plug_regs_p->plug_state);
 559         writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state);
 560
 561         writel(~0x0, &udc_regs_p->endp_int);
 562         writel(~0x0, &udc_regs_p->dev_int_mask);
 563         writel(~0x0, &udc_regs_p->endp_int_mask);
 564
 565 #ifndef CONFIG_USBD_HS
 566         writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
 567                DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
 568 #else
 569         writel(DEV_CONF_HS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
 570                         DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
 571 #endif
 572
 573         writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
 574
 575         /* Clear all interrupts pending */
 576         writel(DEV_INT_MSK, &udc_regs_p->dev_int);
 577
 578         return 0;
 579 }
 580
 581 int is_usbd_high_speed(void)
 582 {
 583         return (readl(&udc_regs_p->dev_stat) & DEV_STAT_ENUM) ? 0 : 1;
 584 }
 585
 586 /*
 587  * udc_setup_ep - setup endpoint
 588  * Associate a physical endpoint with endpoint_instance
 589  */
 590 void udc_setup_ep(struct usb_device_instance *device,
 591                   u32 ep, struct usb_endpoint_instance *endpoint)
 592 {
 593         UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address);
 594         int ep_addr;
 595         int ep_num, ep_type;
 596         int packet_size;
 597         int buffer_size;
 598         int attributes;
 599         char *tt;
 600         u32 endp_intmask;
 601
 602         if ((ep != 0) && (udc_device->device_state < STATE_ADDRESSED))
 603                 return;
 604
 605         tt = env_get("usbtty");
 606         if (!tt)
 607                 tt = "generic";
 608
 609         ep_addr = endpoint->endpoint_address;
 610         ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
 611
 612         if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
 613                 /* IN endpoint */
 614                 packet_size = endpoint->tx_packetSize;
 615                 buffer_size = packet_size * 2;
 616                 attributes = endpoint->tx_attributes;
 617         } else {
 618                 /* OUT endpoint */
 619                 packet_size = endpoint->rcv_packetSize;
 620                 buffer_size = packet_size * 2;
 621                 attributes = endpoint->rcv_attributes;
 622         }
 623
 624         switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) {
 625         case USB_ENDPOINT_XFER_CONTROL:
 626                 ep_type = ENDP_EPTYPE_CNTL;
 627                 break;
 628         case USB_ENDPOINT_XFER_BULK:
 629         default:
 630                 ep_type = ENDP_EPTYPE_BULK;
 631                 break;
 632         case USB_ENDPOINT_XFER_INT:
 633                 ep_type = ENDP_EPTYPE_INT;
 634                 break;
 635         case USB_ENDPOINT_XFER_ISOC:
 636                 ep_type = ENDP_EPTYPE_ISO;
 637                 break;
 638         }
 639
 640         struct udc_endp_regs *out_p = &outep_regs_p[ep_num];
 641         struct udc_endp_regs *in_p = &inep_regs_p[ep_num];
 642
 643         if (!ep_addr) {
 644                 /* Setup endpoint 0 */
 645                 buffer_size = packet_size;
 646
 647                 writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK,
 648                        &in_p->endp_cntl);
 649
 650                 writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK,
 651                        &out_p->endp_cntl);
 652
 653                 writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl);
 654
 655                 writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
 656
 657                 writel(packet_size, &in_p->endp_maxpacksize);
 658
 659                 writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl);
 660
 661                 writel(packet_size | ((buffer_size / sizeof(int)) << 16),
 662                        &out_p->endp_maxpacksize);
 663
 664         } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
 665                 /* Setup the IN endpoint */
 666                 writel(0x0, &in_p->endp_status);
 667                 writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl);
 668                 writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
 669                 writel(packet_size, &in_p->endp_maxpacksize);
 670
 671                 if (!strcmp(tt, "cdc_acm")) {
 672                         if (ep_type == ENDP_EPTYPE_INT) {
 673                                 /* Conf no. 1 Interface no. 0 */
 674                                 writel((packet_size << 19) |
 675                                        ENDP_EPDIR_IN | (1 << 7) |
 676                                        (0 << 11) | (ep_type << 5) | ep_num,
 677                                        &udc_regs_p->udc_endp_reg[ep_num]);
 678                         } else {
 679                                 /* Conf no. 1 Interface no. 1 */
 680                                 writel((packet_size << 19) |
 681                                        ENDP_EPDIR_IN | (1 << 7) |
 682                                        (1 << 11) | (ep_type << 5) | ep_num,
 683                                        &udc_regs_p->udc_endp_reg[ep_num]);
 684                         }
 685                 } else {
 686                         /* Conf no. 1 Interface no. 0 */
 687                         writel((packet_size << 19) |
 688                                ENDP_EPDIR_IN | (1 << 7) |
 689                                (0 << 11) | (ep_type << 5) | ep_num,
 690                                &udc_regs_p->udc_endp_reg[ep_num]);
 691                 }
 692
 693         } else {
 694                 /* Setup the OUT endpoint */
 695                 writel(0x0, &out_p->endp_status);
 696                 writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl);
 697                 writel(packet_size | ((buffer_size / sizeof(int)) << 16),
 698                        &out_p->endp_maxpacksize);
 699
 700                 if (!strcmp(tt, "cdc_acm")) {
 701                         writel((packet_size << 19) |
 702                                ENDP_EPDIR_OUT | (1 << 7) |
 703                                (1 << 11) | (ep_type << 5) | ep_num,
 704                                &udc_regs_p->udc_endp_reg[ep_num]);
 705                 } else {
 706                         writel((packet_size << 19) |
 707                                ENDP_EPDIR_OUT | (1 << 7) |
 708                                (0 << 11) | (ep_type << 5) | ep_num,
 709                                &udc_regs_p->udc_endp_reg[ep_num]);
 710                 }
 711
 712         }
 713
 714         endp_intmask = readl(&udc_regs_p->endp_int_mask);
 715         endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num);
 716         writel(endp_intmask, &udc_regs_p->endp_int_mask);
 717 }
 718
 719 /* Turn on the USB connection by enabling the pullup resistor */
 720 void udc_connect(void)
 721 {
 722         u32 plug_st, dev_cntl;
 723
 724         dev_cntl = readl(&udc_regs_p->dev_cntl);
 725         dev_cntl |= DEV_CNTL_SOFTDISCONNECT;
 726         writel(dev_cntl, &udc_regs_p->dev_cntl);
 727
 728         udelay(1000);
 729
 730         dev_cntl = readl(&udc_regs_p->dev_cntl);
 731         dev_cntl &= ~DEV_CNTL_SOFTDISCONNECT;
 732         writel(dev_cntl, &udc_regs_p->dev_cntl);
 733
 734         plug_st = readl(&plug_regs_p->plug_state);
 735         plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
 736         writel(plug_st, &plug_regs_p->plug_state);
 737 }
 738
 739 /* Turn off the USB connection by disabling the pullup resistor */
 740 void udc_disconnect(void)
 741 {
 742         u32 plug_st;
 743
 744         writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl);
 745
 746         plug_st = readl(&plug_regs_p->plug_state);
 747         plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
 748         writel(plug_st, &plug_regs_p->plug_state);
 749 }
 750
 751 /* Switch on the UDC */
 752 void udc_enable(struct usb_device_instance *device)
 753 {
 754         UDCDBGA("enable device %p, status %d", device, device->status);
 755
 756         /* Save the device structure pointer */
 757         udc_device = device;
 758
 759         /* Setup ep0 urb */
 760         if (!ep0_urb) {
 761                 ep0_urb =
 762                     usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array);
 763         } else {
 764                 serial_printf("udc_enable: ep0_urb already allocated %p\n",
 765                               ep0_urb);
 766         }
 767
 768         writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
 769 }
 770
 771 /**
 772  * udc_startup - allow udc code to do any additional startup
 773  */
 774 void udc_startup_events(struct usb_device_instance *device)
 775 {
 776         /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
 777         usbd_device_event_irq(device, DEVICE_INIT, 0);
 778
 779         /*
 780          * The DEVICE_CREATE event puts the USB device in the state
 781          * STATE_ATTACHED.
 782          */
 783         usbd_device_event_irq(device, DEVICE_CREATE, 0);
 784
 785         /*
 786          * Some USB controller driver implementations signal
 787          * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
 788          * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
 789          * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
 790          * The DW USB client controller has the capability to detect when the
 791          * USB cable is connected to a powered USB bus, so we will defer the
 792          * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
 793          */
 794
 795         udc_enable(device);
 796 }
 797
 798 /*
 799  * Plug detection interrupt handling
 800  */
 801 static void dw_udc_plug_irq(void)
 802 {
 803         if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) {
 804                 /*
 805                  * USB cable attached
 806                  * Turn off PHY reset bit (PLUG detect).
 807                  * Switch PHY opmode to normal operation (PLUG detect).
 808                  */
 809                 udc_connect();
 810                 writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
 811
 812                 UDCDBG("device attached and powered");
 813                 udc_state_transition(udc_device->device_state, STATE_POWERED);
 814         } else {
 815                 writel(~0x0, &udc_regs_p->dev_int_mask);
 816
 817                 UDCDBG("device detached or unpowered");
 818                 udc_state_transition(udc_device->device_state, STATE_ATTACHED);
 819         }
 820 }
 821
 822 /*
 823  * Device interrupt handling
 824  */
 825 static void dw_udc_dev_irq(void)
 826 {
 827         if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) {
 828                 writel(~0x0, &udc_regs_p->endp_int_mask);
 829
 830                 writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH,
 831                        &inep_regs_p[0].endp_cntl);
 832
 833                 writel(DEV_INT_USBRESET, &udc_regs_p->dev_int);
 834
 835                 /*
 836                  * This endpoint0 specific register can be programmed only
 837                  * after the phy clock is initialized
 838                  */
 839                 writel((EP0_MAX_PACKET_SIZE << 19) | ENDP_EPTYPE_CNTL,
 840                                 &udc_regs_p->udc_endp_reg[0]);
 841
 842                 UDCDBG("device reset in progess");
 843                 udc_state_transition(udc_device->device_state, STATE_DEFAULT);
 844         }
 845
 846         /* Device Enumeration completed */
 847         if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) {
 848                 writel(DEV_INT_ENUM, &udc_regs_p->dev_int);
 849
 850                 /* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */
 851                 writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001,
 852                        &udc_regs_p->endp_int_mask);
 853
 854                 UDCDBG("default -> addressed");
 855                 udc_state_transition(udc_device->device_state, STATE_ADDRESSED);
 856         }
 857
 858         /* The USB will be in SUSPEND in 3 ms */
 859         if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) {
 860                 writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int);
 861
 862                 UDCDBG("entering inactive state");
 863                 /* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */
 864         }
 865
 866         /* SetConfiguration command received */
 867         if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) {
 868                 writel(DEV_INT_SETCFG, &udc_regs_p->dev_int);
 869
 870                 UDCDBG("entering configured state");
 871                 udc_state_transition(udc_device->device_state,
 872                                      STATE_CONFIGURED);
 873         }
 874
 875         /* SetInterface command received */
 876         if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF)
 877                 writel(DEV_INT_SETINTF, &udc_regs_p->dev_int);
 878
 879         /* USB Suspend detected on cable */
 880         if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) {
 881                 writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int);
 882
 883                 UDCDBG("entering suspended state");
 884                 usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0);
 885         }
 886
 887         /* USB Start-Of-Frame detected on cable */
 888         if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF)
 889                 writel(DEV_INT_SOF, &udc_regs_p->dev_int);
 890 }
 891
 892 /*
 893  * Endpoint interrupt handling
 894  */
 895 static void dw_udc_endpoint_irq(void)
 896 {
 897         while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) {
 898
 899                 writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int);
 900
 901                 if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK)
 902                     == ENDP_STATUS_OUT_SETUP) {
 903                         dw_udc_setup(udc_device->bus->endpoint_array + 0);
 904                         writel(ENDP_STATUS_OUT_SETUP,
 905                                &outep_regs_p[0].endp_status);
 906
 907                 } else if ((readl(&outep_regs_p[0].endp_status) &
 908                             ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
 909                         dw_udc_ep0_rx(udc_device->bus->endpoint_array + 0);
 910                         writel(ENDP_STATUS_OUT_DATA,
 911                                &outep_regs_p[0].endp_status);
 912
 913                 } else if ((readl(&outep_regs_p[0].endp_status) &
 914                             ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
 915                         /* NONE received */
 916                 }
 917
 918                 writel(0x0, &outep_regs_p[0].endp_status);
 919         }
 920
 921         if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) {
 922                 dw_udc_ep0_tx(udc_device->bus->endpoint_array + 0);
 923
 924                 writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status);
 925                 writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int);
 926         }
 927
 928         if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) {
 929                 u32 epnum = 0;
 930                 u32 ep_int = readl(&udc_regs_p->endp_int) &
 931                     ENDP_INT_NONISOOUT_MSK;
 932
 933                 ep_int >>= 16;
 934                 while (0x0 == (ep_int & 0x1)) {
 935                         ep_int >>= 1;
 936                         epnum++;
 937                 }
 938
 939                 writel((1 << 16) << epnum, &udc_regs_p->endp_int);
 940
 941                 if ((readl(&outep_regs_p[epnum].endp_status) &
 942                      ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
 943
 944                         dw_udc_epn_rx(epnum);
 945                         writel(ENDP_STATUS_OUT_DATA,
 946                                &outep_regs_p[epnum].endp_status);
 947                 } else if ((readl(&outep_regs_p[epnum].endp_status) &
 948                             ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
 949                         writel(0x0, &outep_regs_p[epnum].endp_status);
 950                 }
 951         }
 952
 953         if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) {
 954                 u32 epnum = 0;
 955                 u32 ep_int = readl(&udc_regs_p->endp_int) &
 956                     ENDP_INT_NONISOIN_MSK;
 957
 958                 while (0x0 == (ep_int & 0x1)) {
 959                         ep_int >>= 1;
 960                         epnum++;
 961                 }
 962
 963                 if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) {
 964                         writel(ENDP_STATUS_IN,
 965                                &outep_regs_p[epnum].endp_status);
 966                         dw_udc_epn_tx(epnum);
 967
 968                         writel(ENDP_STATUS_IN,
 969                                &outep_regs_p[epnum].endp_status);
 970                 }
 971
 972                 writel((1 << epnum), &udc_regs_p->endp_int);
 973         }
 974 }
 975
 976 /*
 977  * UDC interrupts
 978  */
 979 void udc_irq(void)
 980 {
 981         /*
 982          * Loop while we have interrupts.
 983          * If we don't do this, the input chain
 984          * polling delay is likely to miss
 985          * host requests.
 986          */
 987         while (readl(&plug_regs_p->plug_pending))
 988                 dw_udc_plug_irq();
 989
 990         while (readl(&udc_regs_p->dev_int))
 991                 dw_udc_dev_irq();
 992
 993         if (readl(&udc_regs_p->endp_int))
 994                 dw_udc_endpoint_irq();
 995 }
 996
 997 /* Flow control */
 998 void udc_set_nak(int epid)
 999 {
1000         writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
1001                &inep_regs_p[epid].endp_cntl);
1002
1003         writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
1004                &outep_regs_p[epid].endp_cntl);
1005 }
1006
1007 void udc_unset_nak(int epid)
1008 {
1009         u32 val;
1010
1011         val = readl(&inep_regs_p[epid].endp_cntl);
1012         val &= ~ENDP_CNTL_SNAK;
1013         val |= ENDP_CNTL_CNAK;
1014         writel(val, &inep_regs_p[epid].endp_cntl);
1015
1016         val = readl(&outep_regs_p[epid].endp_cntl);
1017         val &= ~ENDP_CNTL_SNAK;
1018         val |= ENDP_CNTL_CNAK;
1019         writel(val, &outep_regs_p[epid].endp_cntl);
1020 }