1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * Patched for AX88772B by Antmicro Ltd <www.antmicro.com>
15 #include <linux/mii.h>
16 #include "usb_ether.h"
18 /* ASIX AX8817X based USB 2.0 Ethernet Devices */
20 #define AX_CMD_SET_SW_MII 0x06
21 #define AX_CMD_READ_MII_REG 0x07
22 #define AX_CMD_WRITE_MII_REG 0x08
23 #define AX_CMD_SET_HW_MII 0x0a
24 #define AX_CMD_READ_EEPROM 0x0b
25 #define AX_CMD_READ_RX_CTL 0x0f
26 #define AX_CMD_WRITE_RX_CTL 0x10
27 #define AX_CMD_WRITE_IPG0 0x12
28 #define AX_CMD_READ_NODE_ID 0x13
29 #define AX_CMD_WRITE_NODE_ID 0x14
30 #define AX_CMD_READ_PHY_ID 0x19
31 #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
32 #define AX_CMD_WRITE_GPIOS 0x1f
33 #define AX_CMD_SW_RESET 0x20
34 #define AX_CMD_SW_PHY_SELECT 0x22
36 #define AX_SWRESET_CLEAR 0x00
37 #define AX_SWRESET_PRTE 0x04
38 #define AX_SWRESET_PRL 0x08
39 #define AX_SWRESET_IPRL 0x20
40 #define AX_SWRESET_IPPD 0x40
42 #define AX88772_IPG0_DEFAULT 0x15
43 #define AX88772_IPG1_DEFAULT 0x0c
44 #define AX88772_IPG2_DEFAULT 0x12
46 /* AX88772 & AX88178 Medium Mode Register */
47 #define AX_MEDIUM_PF 0x0080
48 #define AX_MEDIUM_JFE 0x0040
49 #define AX_MEDIUM_TFC 0x0020
50 #define AX_MEDIUM_RFC 0x0010
51 #define AX_MEDIUM_ENCK 0x0008
52 #define AX_MEDIUM_AC 0x0004
53 #define AX_MEDIUM_FD 0x0002
54 #define AX_MEDIUM_GM 0x0001
55 #define AX_MEDIUM_SM 0x1000
56 #define AX_MEDIUM_SBP 0x0800
57 #define AX_MEDIUM_PS 0x0200
58 #define AX_MEDIUM_RE 0x0100
60 #define AX88178_MEDIUM_DEFAULT \
61 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
62 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
65 #define AX88772_MEDIUM_DEFAULT \
66 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
67 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
68 AX_MEDIUM_AC | AX_MEDIUM_RE)
70 /* AX88772 & AX88178 RX_CTL values */
71 #define AX_RX_CTL_SO 0x0080
72 #define AX_RX_CTL_AB 0x0008
74 #define AX_DEFAULT_RX_CTL \
75 (AX_RX_CTL_SO | AX_RX_CTL_AB)
78 #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
79 #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
80 #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
83 #define ASIX_BASE_NAME "asx"
84 #define USB_CTRL_SET_TIMEOUT 5000
85 #define USB_CTRL_GET_TIMEOUT 5000
86 #define USB_BULK_SEND_TIMEOUT 5000
87 #define USB_BULK_RECV_TIMEOUT 5000
89 #define AX_RX_URB_SIZE 2048
90 #define PHY_CONNECT_TIMEOUT 5000
92 /* asix_flags defines */
94 #define FLAG_TYPE_AX88172 (1U << 0)
95 #define FLAG_TYPE_AX88772 (1U << 1)
96 #define FLAG_TYPE_AX88772B (1U << 2)
97 #define FLAG_EEPROM_MAC (1U << 3) /* initial mac address in eeprom */
101 struct asix_private {
104 struct ueth_data ueth;
108 #ifndef CONFIG_DM_ETH
110 static int curr_eth_dev; /* index for name of next device detected */
114 * Asix infrastructure commands
116 static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
117 u16 size, void *data)
121 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
122 "size=%d\n", cmd, value, index, size);
124 len = usb_control_msg(
126 usb_sndctrlpipe(dev->pusb_dev, 0),
128 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
133 USB_CTRL_SET_TIMEOUT);
135 return len == size ? 0 : -1;
138 static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
139 u16 size, void *data)
143 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
144 cmd, value, index, size);
146 len = usb_control_msg(
148 usb_rcvctrlpipe(dev->pusb_dev, 0),
150 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
155 USB_CTRL_GET_TIMEOUT);
156 return len == size ? 0 : -1;
159 static inline int asix_set_sw_mii(struct ueth_data *dev)
163 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
165 debug("Failed to enable software MII access\n");
169 static inline int asix_set_hw_mii(struct ueth_data *dev)
173 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
175 debug("Failed to enable hardware MII access\n");
179 static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
181 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
183 asix_set_sw_mii(dev);
184 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
185 asix_set_hw_mii(dev);
187 debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
188 phy_id, loc, le16_to_cpu(*res));
190 return le16_to_cpu(*res);
194 asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
196 ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
197 *res = cpu_to_le16(val);
199 debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
201 asix_set_sw_mii(dev);
202 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
203 asix_set_hw_mii(dev);
207 * Asix "high level" commands
209 static int asix_sw_reset(struct ueth_data *dev, u8 flags)
213 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
215 debug("Failed to send software reset: %02x\n", ret);
222 static inline int asix_get_phy_addr(struct ueth_data *dev)
224 ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
226 int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
228 debug("asix_get_phy_addr()\n");
231 debug("Error reading PHYID register: %02x\n", ret);
234 debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
241 static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
245 debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
246 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
249 debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
255 static u16 asix_read_rx_ctl(struct ueth_data *dev)
257 ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
259 int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
262 debug("Error reading RX_CTL register: %02x\n", ret);
264 ret = le16_to_cpu(*v);
268 static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
272 debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
273 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
275 debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
281 static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
285 debug("asix_write_gpio() - value = 0x%04x\n", value);
286 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
288 debug("Failed to write GPIO value 0x%04x: %02x\n",
292 udelay(sleep * 1000);
297 static int asix_write_hwaddr_common(struct ueth_data *dev, uint8_t *enetaddr)
300 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
302 memcpy(buf, enetaddr, ETH_ALEN);
304 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
306 debug("Failed to set MAC address: %02x\n", ret);
316 * mii_nway_restart - restart NWay (autonegotiation) for this interface
318 * Returns 0 on success, negative on error.
320 static int mii_nway_restart(struct ueth_data *dev)
325 /* if autoneg is off, it's an error */
326 bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
328 if (bmcr & BMCR_ANENABLE) {
329 bmcr |= BMCR_ANRESTART;
330 asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
337 static int asix_read_mac_common(struct ueth_data *dev,
338 struct asix_private *priv, uint8_t *enetaddr)
340 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
343 if (priv->flags & FLAG_EEPROM_MAC) {
344 for (i = 0; i < (ETH_ALEN >> 1); i++) {
345 if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
346 0x04 + i, 0, 2, buf) < 0) {
347 debug("Failed to read SROM address 04h.\n");
350 memcpy(enetaddr + i * 2, buf, 2);
353 if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf)
355 debug("Failed to read MAC address.\n");
358 memcpy(enetaddr, buf, ETH_ALEN);
364 static int asix_basic_reset(struct ueth_data *dev)
369 if (asix_write_gpio(dev,
370 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
373 /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
374 embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
375 if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
376 embd_phy, 0, 0, NULL) < 0) {
377 debug("Select PHY #1 failed\n");
381 if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
384 if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
388 if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
391 if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
395 rx_ctl = asix_read_rx_ctl(dev);
396 debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
397 if (asix_write_rx_ctl(dev, 0x0000) < 0)
400 rx_ctl = asix_read_rx_ctl(dev);
401 debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
403 dev->phy_id = asix_get_phy_addr(dev);
405 debug("Failed to read phy id\n");
407 asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
408 asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
409 ADVERTISE_ALL | ADVERTISE_CSMA);
410 mii_nway_restart(dev);
412 if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
415 if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
416 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
417 AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
418 debug("Write IPG,IPG1,IPG2 failed\n");
425 static int asix_init_common(struct ueth_data *dev, uint8_t *enetaddr)
428 #define TIMEOUT_RESOLUTION 50 /* ms */
431 debug("** %s()\n", __func__);
433 if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
436 if (asix_write_hwaddr_common(dev, enetaddr) < 0)
440 link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
442 if (!link_detected) {
444 printf("Waiting for Ethernet connection... ");
445 udelay(TIMEOUT_RESOLUTION * 1000);
446 timeout += TIMEOUT_RESOLUTION;
448 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
453 printf("unable to connect.\n");
458 * Wait some more to avoid timeout on first transfer
459 * (e.g. EHCI timed out on TD - token=0x8008d80)
468 static int asix_send_common(struct ueth_data *dev, void *packet, int length)
473 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
474 PKTSIZE + sizeof(packet_len));
476 debug("** %s(), len %d\n", __func__, length);
478 packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
479 cpu_to_le32s(&packet_len);
481 memcpy(msg, &packet_len, sizeof(packet_len));
482 memcpy(msg + sizeof(packet_len), (void *)packet, length);
484 err = usb_bulk_msg(dev->pusb_dev,
485 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
487 length + sizeof(packet_len),
489 USB_BULK_SEND_TIMEOUT);
490 debug("Tx: len = %zu, actual = %u, err = %d\n",
491 length + sizeof(packet_len), actual_len, err);
496 #ifndef CONFIG_DM_ETH
500 static int asix_init(struct eth_device *eth, bd_t *bd)
502 struct ueth_data *dev = (struct ueth_data *)eth->priv;
504 return asix_init_common(dev, eth->enetaddr);
507 static int asix_send(struct eth_device *eth, void *packet, int length)
509 struct ueth_data *dev = (struct ueth_data *)eth->priv;
511 return asix_send_common(dev, packet, length);
514 static int asix_recv(struct eth_device *eth)
516 struct ueth_data *dev = (struct ueth_data *)eth->priv;
517 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
518 unsigned char *buf_ptr;
523 debug("** %s()\n", __func__);
525 err = usb_bulk_msg(dev->pusb_dev,
526 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
530 USB_BULK_RECV_TIMEOUT);
531 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
534 debug("Rx: failed to receive\n");
537 if (actual_len > AX_RX_URB_SIZE) {
538 debug("Rx: received too many bytes %d\n", actual_len);
543 while (actual_len > 0) {
545 * 1st 4 bytes contain the length of the actual data as two
546 * complementary 16-bit words. Extract the length of the data.
548 if (actual_len < sizeof(packet_len)) {
549 debug("Rx: incomplete packet length\n");
552 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
553 le32_to_cpus(&packet_len);
554 if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
555 debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
556 packet_len, (~packet_len >> 16) & 0x7ff,
560 packet_len = packet_len & 0x7ff;
561 if (packet_len > actual_len - sizeof(packet_len)) {
562 debug("Rx: too large packet: %d\n", packet_len);
566 /* Notify net stack */
567 net_process_received_packet(buf_ptr + sizeof(packet_len),
570 /* Adjust for next iteration. Packets are padded to 16-bits */
573 actual_len -= sizeof(packet_len) + packet_len;
574 buf_ptr += sizeof(packet_len) + packet_len;
580 static void asix_halt(struct eth_device *eth)
582 debug("** %s()\n", __func__);
585 static int asix_write_hwaddr(struct eth_device *eth)
587 struct ueth_data *dev = (struct ueth_data *)eth->priv;
589 return asix_write_hwaddr_common(dev, eth->enetaddr);
593 * Asix probing functions
595 void asix_eth_before_probe(void)
601 unsigned short vendor;
602 unsigned short product;
606 static const struct asix_dongle asix_dongles[] = {
607 { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
608 { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
609 { 0x2001, 0x1a02, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver C1 */
610 /* Cables-to-Go USB Ethernet Adapter */
611 { 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
612 { 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
613 { 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
614 { 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
615 { 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
616 { 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
617 /* DLink DUB-E100 H/W Ver B1 Alternate */
618 { 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
620 { 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
621 { 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B },
622 { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
625 /* Probe to see if a new device is actually an asix device */
626 int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
627 struct ueth_data *ss)
629 struct usb_interface *iface;
630 struct usb_interface_descriptor *iface_desc;
631 int ep_in_found = 0, ep_out_found = 0;
634 /* let's examine the device now */
635 iface = &dev->config.if_desc[ifnum];
636 iface_desc = &dev->config.if_desc[ifnum].desc;
638 for (i = 0; asix_dongles[i].vendor != 0; i++) {
639 if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
640 dev->descriptor.idProduct == asix_dongles[i].product)
641 /* Found a supported dongle */
645 if (asix_dongles[i].vendor == 0)
648 memset(ss, 0, sizeof(struct ueth_data));
650 /* At this point, we know we've got a live one */
651 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
652 dev->descriptor.idVendor, dev->descriptor.idProduct);
654 /* Initialize the ueth_data structure with some useful info */
657 ss->subclass = iface_desc->bInterfaceSubClass;
658 ss->protocol = iface_desc->bInterfaceProtocol;
660 /* alloc driver private */
661 ss->dev_priv = calloc(1, sizeof(struct asix_private));
665 ((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
668 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
669 * int. We will ignore any others.
671 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
672 /* is it an BULK endpoint? */
673 if ((iface->ep_desc[i].bmAttributes &
674 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
675 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
676 if (ep_addr & USB_DIR_IN) {
678 ss->ep_in = ep_addr &
679 USB_ENDPOINT_NUMBER_MASK;
684 ss->ep_out = ep_addr &
685 USB_ENDPOINT_NUMBER_MASK;
691 /* is it an interrupt endpoint? */
692 if ((iface->ep_desc[i].bmAttributes &
693 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
694 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
695 USB_ENDPOINT_NUMBER_MASK;
696 ss->irqinterval = iface->ep_desc[i].bInterval;
699 debug("Endpoints In %d Out %d Int %d\n",
700 ss->ep_in, ss->ep_out, ss->ep_int);
702 /* Do some basic sanity checks, and bail if we find a problem */
703 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
704 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
705 debug("Problems with device\n");
708 dev->privptr = (void *)ss;
712 int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
713 struct eth_device *eth)
715 struct asix_private *priv = (struct asix_private *)ss->dev_priv;
718 debug("%s: missing parameter.\n", __func__);
721 sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
722 eth->init = asix_init;
723 eth->send = asix_send;
724 eth->recv = asix_recv;
725 eth->halt = asix_halt;
726 if (!(priv->flags & FLAG_TYPE_AX88172))
727 eth->write_hwaddr = asix_write_hwaddr;
730 if (asix_basic_reset(ss))
733 /* Get the MAC address */
734 if (asix_read_mac_common(ss, priv, eth->enetaddr))
736 debug("MAC %pM\n", eth->enetaddr);
743 static int asix_eth_start(struct udevice *dev)
745 struct eth_pdata *pdata = dev_get_platdata(dev);
746 struct asix_private *priv = dev_get_priv(dev);
748 return asix_init_common(&priv->ueth, pdata->enetaddr);
751 void asix_eth_stop(struct udevice *dev)
753 debug("** %s()\n", __func__);
756 int asix_eth_send(struct udevice *dev, void *packet, int length)
758 struct asix_private *priv = dev_get_priv(dev);
760 return asix_send_common(&priv->ueth, packet, length);
763 int asix_eth_recv(struct udevice *dev, int flags, uchar **packetp)
765 struct asix_private *priv = dev_get_priv(dev);
766 struct ueth_data *ueth = &priv->ueth;
771 len = usb_ether_get_rx_bytes(ueth, &ptr);
772 debug("%s: first try, len=%d\n", __func__, len);
774 if (!(flags & ETH_RECV_CHECK_DEVICE))
776 ret = usb_ether_receive(ueth, AX_RX_URB_SIZE);
780 len = usb_ether_get_rx_bytes(ueth, &ptr);
781 debug("%s: second try, len=%d\n", __func__, len);
785 * 1st 4 bytes contain the length of the actual data as two
786 * complementary 16-bit words. Extract the length of the data.
788 if (len < sizeof(packet_len)) {
789 debug("Rx: incomplete packet length\n");
792 memcpy(&packet_len, ptr, sizeof(packet_len));
793 le32_to_cpus(&packet_len);
794 if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
795 debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
796 packet_len, (~packet_len >> 16) & 0x7ff,
800 packet_len = packet_len & 0x7ff;
801 if (packet_len > len - sizeof(packet_len)) {
802 debug("Rx: too large packet: %d\n", packet_len);
806 *packetp = ptr + sizeof(packet_len);
810 usb_ether_advance_rxbuf(ueth, -1);
814 static int asix_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
816 struct asix_private *priv = dev_get_priv(dev);
820 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
825 int asix_write_hwaddr(struct udevice *dev)
827 struct eth_pdata *pdata = dev_get_platdata(dev);
828 struct asix_private *priv = dev_get_priv(dev);
830 if (priv->flags & FLAG_TYPE_AX88172)
833 return asix_write_hwaddr_common(&priv->ueth, pdata->enetaddr);
836 static int asix_eth_probe(struct udevice *dev)
838 struct eth_pdata *pdata = dev_get_platdata(dev);
839 struct asix_private *priv = dev_get_priv(dev);
840 struct ueth_data *ss = &priv->ueth;
843 priv->flags = dev->driver_data;
844 ret = usb_ether_register(dev, ss, AX_RX_URB_SIZE);
848 ret = asix_basic_reset(ss);
852 /* Get the MAC address */
853 ret = asix_read_mac_common(ss, priv, pdata->enetaddr);
856 debug("MAC %pM\n", pdata->enetaddr);
861 return usb_ether_deregister(ss);
864 static const struct eth_ops asix_eth_ops = {
865 .start = asix_eth_start,
866 .send = asix_eth_send,
867 .recv = asix_eth_recv,
868 .free_pkt = asix_free_pkt,
869 .stop = asix_eth_stop,
870 .write_hwaddr = asix_write_hwaddr,
873 U_BOOT_DRIVER(asix_eth) = {
876 .probe = asix_eth_probe,
877 .ops = &asix_eth_ops,
878 .priv_auto_alloc_size = sizeof(struct asix_private),
879 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
882 static const struct usb_device_id asix_eth_id_table[] = {
883 /* Apple USB Ethernet Adapter */
884 { USB_DEVICE(0x05ac, 0x1402), .driver_info = FLAG_TYPE_AX88772 },
885 /* D-Link DUB-E100 H/W Ver B1 */
886 { USB_DEVICE(0x07d1, 0x3c05), .driver_info = FLAG_TYPE_AX88772 },
887 /* D-Link DUB-E100 H/W Ver C1 */
888 { USB_DEVICE(0x2001, 0x1a02), .driver_info = FLAG_TYPE_AX88772 },
889 /* Cables-to-Go USB Ethernet Adapter */
890 { USB_DEVICE(0x0b95, 0x772a), .driver_info = FLAG_TYPE_AX88772 },
891 /* Trendnet TU2-ET100 V3.0R */
892 { USB_DEVICE(0x0b95, 0x7720), .driver_info = FLAG_TYPE_AX88772 },
894 { USB_DEVICE(0x0b95, 0x1720), .driver_info = FLAG_TYPE_AX88172 },
895 /* MSI - ASIX 88772a */
896 { USB_DEVICE(0x0db0, 0xa877), .driver_info = FLAG_TYPE_AX88772 },
897 /* Linksys 200M v2.1 */
898 { USB_DEVICE(0x13b1, 0x0018), .driver_info = FLAG_TYPE_AX88172 },
899 /* 0Q0 cable ethernet */
900 { USB_DEVICE(0x1557, 0x7720), .driver_info = FLAG_TYPE_AX88772 },
901 /* DLink DUB-E100 H/W Ver B1 Alternate */
902 { USB_DEVICE(0x2001, 0x3c05), .driver_info = FLAG_TYPE_AX88772 },
904 { USB_DEVICE(0x0b95, 0x772b),
905 .driver_info = FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
906 { USB_DEVICE(0x0b95, 0x7e2b), .driver_info = FLAG_TYPE_AX88772B },
907 { } /* Terminating entry */
910 U_BOOT_USB_DEVICE(asix_eth, asix_eth_id_table);