drivers/usb/dwc3/ti_usb_phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**
   3  * ti_usb_phy.c - USB3 and USB3 PHY programming for dwc3
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   8  *
   9  * Taken from Linux Kernel v3.16 (drivers/phy/phy-ti-pipe3.c and
  10  * drivers/phy/phy-omap-usb2.c) and ported to uboot.
  11  *
  12  * "commit 56042e : phy: ti-pipe3: Fix suspend/resume and module reload" for
  13  * phy-ti-pipe3.c
  14  *
  15  * "commit eb82a3 : phy: omap-usb2: Balance pm_runtime_enable() on probe failure
  16  * and remove" for phy-omap-usb2.c
  17  */
  18
  19 #include <common.h>
  20 #include <malloc.h>
  21 #include <ti-usb-phy-uboot.h>
  22 #include <linux/ioport.h>
  23 #include <asm/io.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <dm.h>
  26
  27 #include "linux-compat.h"
  28
  29 #define PLL_STATUS              0x00000004
  30 #define PLL_GO                  0x00000008
  31 #define PLL_CONFIGURATION1      0x0000000C
  32 #define PLL_CONFIGURATION2      0x00000010
  33 #define PLL_CONFIGURATION3      0x00000014
  34 #define PLL_CONFIGURATION4      0x00000020
  35
  36 #define PLL_REGM_MASK           0x001FFE00
  37 #define PLL_REGM_SHIFT          0x9
  38 #define PLL_REGM_F_MASK         0x0003FFFF
  39 #define PLL_REGM_F_SHIFT        0x0
  40 #define PLL_REGN_MASK           0x000001FE
  41 #define PLL_REGN_SHIFT          0x1
  42 #define PLL_SELFREQDCO_MASK     0x0000000E
  43 #define PLL_SELFREQDCO_SHIFT    0x1
  44 #define PLL_SD_MASK             0x0003FC00
  45 #define PLL_SD_SHIFT            10
  46 #define SET_PLL_GO              0x1
  47 #define PLL_LDOPWDN             BIT(15)
  48 #define PLL_TICOPWDN            BIT(16)
  49 #define PLL_LOCK                0x2
  50 #define PLL_IDLE                0x1
  51
  52 #define OMAP_CTRL_DEV_PHY_PD                            BIT(0)
  53 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK          0x003FC000
  54 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT         0xE
  55
  56 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK         0xFFC00000
  57 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT        0x16
  58
  59 #define OMAP_CTRL_USB3_PHY_TX_RX_POWERON        0x3
  60 #define OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF       0x0
  61
  62 #define OMAP_CTRL_USB2_PHY_PD                   BIT(28)
  63
  64 #define AM437X_CTRL_USB2_PHY_PD                 BIT(0)
  65 #define AM437X_CTRL_USB2_OTG_PD                 BIT(1)
  66 #define AM437X_CTRL_USB2_OTGVDET_EN             BIT(19)
  67 #define AM437X_CTRL_USB2_OTGSESSEND_EN          BIT(20)
  68
  69 static LIST_HEAD(ti_usb_phy_list);
  70 typedef unsigned int u32;
  71
  72 struct usb3_dpll_params {
  73         u16     m;
  74         u8      n;
  75         u8      freq:3;
  76         u8      sd;
  77         u32     mf;
  78 };
  79
  80 struct usb3_dpll_map {
  81         unsigned long rate;
  82         struct usb3_dpll_params params;
  83         struct usb3_dpll_map *dpll_map;
  84 };
  85
  86 struct ti_usb_phy {
  87         void __iomem *pll_ctrl_base;
  88         void __iomem *usb2_phy_power;
  89         void __iomem *usb3_phy_power;
  90         struct usb3_dpll_map *dpll_map;
  91         struct list_head list;
  92         int index;
  93 };
  94
  95 static struct usb3_dpll_map dpll_map_usb[] = {
  96         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
  97         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
  98         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
  99         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
 100         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
 101         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
 102         { },                                    /* Terminator */
 103 };
 104
 105 static inline unsigned int ti_usb3_readl(void __iomem *base, u32 offset)
 106 {
 107         return readl(base + offset);
 108 }
 109
 110 static inline void ti_usb3_writel(void __iomem *base, u32 offset, u32 value)
 111 {
 112         writel(value, base + offset);
 113 }
 114
 115 #ifndef CONFIG_AM43XX
 116 static struct usb3_dpll_params *ti_usb3_get_dpll_params(struct ti_usb_phy *phy)
 117 {
 118         unsigned long rate;
 119         struct usb3_dpll_map *dpll_map = phy->dpll_map;
 120
 121         rate = get_sys_clk_freq();
 122
 123         for (; dpll_map->rate; dpll_map++) {
 124                 if (rate == dpll_map->rate)
 125                         return &dpll_map->params;
 126         }
 127
 128         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 129
 130         return NULL;
 131 }
 132
 133 static int ti_usb3_dpll_wait_lock(struct ti_usb_phy *phy)
 134 {
 135         u32 val;
 136         do {
 137                 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_STATUS);
 138                         if (val & PLL_LOCK)
 139                                 break;
 140         } while (1);
 141
 142         return 0;
 143 }
 144
 145 static int ti_usb3_dpll_program(struct ti_usb_phy *phy)
 146 {
 147         u32                     val;
 148         struct usb3_dpll_params *dpll_params;
 149
 150         if (!phy->pll_ctrl_base)
 151                 return -EINVAL;
 152
 153         dpll_params = ti_usb3_get_dpll_params(phy);
 154         if (!dpll_params)
 155                 return -EINVAL;
 156
 157         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 158         val &= ~PLL_REGN_MASK;
 159         val |= dpll_params->n << PLL_REGN_SHIFT;
 160         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 161
 162         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 163         val &= ~PLL_SELFREQDCO_MASK;
 164         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 165         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 166
 167         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 168         val &= ~PLL_REGM_MASK;
 169         val |= dpll_params->m << PLL_REGM_SHIFT;
 170         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 171
 172         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 173         val &= ~PLL_REGM_F_MASK;
 174         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 175         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 176
 177         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 178         val &= ~PLL_SD_MASK;
 179         val |= dpll_params->sd << PLL_SD_SHIFT;
 180         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 181
 182         ti_usb3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 183
 184         return ti_usb3_dpll_wait_lock(phy);
 185 }
 186 #endif
 187
 188 void ti_usb2_phy_power(struct ti_usb_phy *phy, int on)
 189 {
 190         u32 val;
 191
 192         val = readl(phy->usb2_phy_power);
 193
 194         if (on) {
 195 #if defined(CONFIG_DRA7XX)
 196                 if (phy->index == 1)
 197                         val &= ~OMAP_CTRL_USB2_PHY_PD;
 198                 else
 199                         val &= ~OMAP_CTRL_DEV_PHY_PD;
 200 #elif defined(CONFIG_AM43XX)
 201                 val &= ~(AM437X_CTRL_USB2_PHY_PD |
 202                          AM437X_CTRL_USB2_OTG_PD);
 203                 val |= (AM437X_CTRL_USB2_OTGVDET_EN |
 204                         AM437X_CTRL_USB2_OTGSESSEND_EN);
 205 #endif
 206         } else {
 207 #if defined(CONFIG_DRA7XX)
 208                 if (phy->index == 1)
 209                         val |= OMAP_CTRL_USB2_PHY_PD;
 210                 else
 211                         val |= OMAP_CTRL_DEV_PHY_PD;
 212
 213 #elif defined(CONFIG_AM43XX)
 214                 val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
 215                          AM437X_CTRL_USB2_OTGSESSEND_EN);
 216                 val |= (AM437X_CTRL_USB2_PHY_PD |
 217                         AM437X_CTRL_USB2_OTG_PD);
 218 #endif
 219         }
 220         writel(val, phy->usb2_phy_power);
 221 }
 222
 223 #ifndef CONFIG_AM43XX
 224 void ti_usb3_phy_power(struct ti_usb_phy *phy, int on)
 225 {
 226         u32 val;
 227         u32 rate;
 228         rate = get_sys_clk_freq();
 229         rate = rate/1000000;
 230
 231         if (!phy->usb3_phy_power)
 232                 return;
 233
 234         val = readl(phy->usb3_phy_power);
 235         if (on) {
 236                 val &= ~(OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK |
 237                         OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK);
 238                 val |= (OMAP_CTRL_USB3_PHY_TX_RX_POWERON) <<
 239                         OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
 240                 val |= rate <<
 241                         OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 242         } else {
 243                 val &= ~OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK;
 244                 val |= OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF <<
 245                         OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
 246         }
 247         writel(val, phy->usb3_phy_power);
 248 }
 249 #endif
 250
 251 /**
 252  * ti_usb_phy_uboot_init - usb phy uboot initialization code
 253  * @dev: struct ti_usb_phy_device containing initialization data
 254  *
 255  * Entry point for ti usb phy driver. This driver handles initialization
 256  * of both usb2 phy and usb3 phy. Pointer to ti_usb_phy_device should be
 257  * passed containing base address and other initialization data.
 258  * Returns '0' on success and a negative value on failure.
 259  *
 260  * Generally called from board_usb_init() implemented in board file.
 261  */
 262 int ti_usb_phy_uboot_init(struct ti_usb_phy_device *dev)
 263 {
 264         struct ti_usb_phy *phy;
 265
 266         phy = devm_kzalloc(NULL, sizeof(*phy), GFP_KERNEL);
 267         if (!phy) {
 268                 dev_err(NULL, "unable to alloc mem for TI USB3 PHY\n");
 269                 return -ENOMEM;
 270         }
 271
 272         phy->dpll_map = dpll_map_usb;
 273         phy->index = dev->index;
 274         phy->pll_ctrl_base = dev->pll_ctrl_base;
 275         phy->usb2_phy_power = dev->usb2_phy_power;
 276         phy->usb3_phy_power = dev->usb3_phy_power;
 277
 278 #ifndef CONFIG_AM43XX
 279         ti_usb3_dpll_program(phy);
 280         ti_usb3_phy_power(phy, 1);
 281 #endif
 282         ti_usb2_phy_power(phy, 1);
 283         mdelay(150);
 284         list_add_tail(&phy->list, &ti_usb_phy_list);
 285
 286         return 0;
 287 }
 288
 289 /**
 290  * ti_usb_phy_uboot_exit - usb phy uboot cleanup code
 291  * @index: index of this controller
 292  *
 293  * Performs cleanup of memory allocated in ti_usb_phy_uboot_init.
 294  * index of _this_ controller should be passed and should match with
 295  * the index passed in ti_usb_phy_device during init.
 296  *
 297  * Generally called from board file.
 298  */
 299 void ti_usb_phy_uboot_exit(int index)
 300 {
 301         struct ti_usb_phy *phy = NULL;
 302
 303         list_for_each_entry(phy, &ti_usb_phy_list, list) {
 304                 if (phy->index != index)
 305                         continue;
 306
 307                 ti_usb2_phy_power(phy, 0);
 308 #ifndef CONFIG_AM43XX
 309                 ti_usb3_phy_power(phy, 0);
 310 #endif
 311                 list_del(&phy->list);
 312                 kfree(phy);
 313                 break;
 314         }
 315 }