drivers/usb/dwc3/ti_usb_phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**
   3  * ti_usb_phy.c - USB3 and USB3 PHY programming for dwc3
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   8  *
   9  * Taken from Linux Kernel v3.16 (drivers/phy/phy-ti-pipe3.c and
  10  * drivers/phy/phy-omap-usb2.c) and ported to uboot.
  11  *
  12  * "commit 56042e : phy: ti-pipe3: Fix suspend/resume and module reload" for
  13  * phy-ti-pipe3.c
  14  *
  15  * "commit eb82a3 : phy: omap-usb2: Balance pm_runtime_enable() on probe failure
  16  * and remove" for phy-omap-usb2.c
  17  */
  18
  19 #include <common.h>
  20 #include <malloc.h>
  21 #include <ti-usb-phy-uboot.h>
  22 #include <dm/device_compat.h>
  23 #include <dm/devres.h>
  24 #include <linux/delay.h>
  25 #include <linux/ioport.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <dm.h>
  29
  30 #include "linux-compat.h"
  31
  32 #define PLL_STATUS              0x00000004
  33 #define PLL_GO                  0x00000008
  34 #define PLL_CONFIGURATION1      0x0000000C
  35 #define PLL_CONFIGURATION2      0x00000010
  36 #define PLL_CONFIGURATION3      0x00000014
  37 #define PLL_CONFIGURATION4      0x00000020
  38
  39 #define PLL_REGM_MASK           0x001FFE00
  40 #define PLL_REGM_SHIFT          0x9
  41 #define PLL_REGM_F_MASK         0x0003FFFF
  42 #define PLL_REGM_F_SHIFT        0x0
  43 #define PLL_REGN_MASK           0x000001FE
  44 #define PLL_REGN_SHIFT          0x1
  45 #define PLL_SELFREQDCO_MASK     0x0000000E
  46 #define PLL_SELFREQDCO_SHIFT    0x1
  47 #define PLL_SD_MASK             0x0003FC00
  48 #define PLL_SD_SHIFT            10
  49 #define SET_PLL_GO              0x1
  50 #define PLL_LDOPWDN             BIT(15)
  51 #define PLL_TICOPWDN            BIT(16)
  52 #define PLL_LOCK                0x2
  53 #define PLL_IDLE                0x1
  54
  55 #define OMAP_CTRL_DEV_PHY_PD                            BIT(0)
  56 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK          0x003FC000
  57 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT         0xE
  58
  59 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK         0xFFC00000
  60 #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT        0x16
  61
  62 #define OMAP_CTRL_USB3_PHY_TX_RX_POWERON        0x3
  63 #define OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF       0x0
  64
  65 #define OMAP_CTRL_USB2_PHY_PD                   BIT(28)
  66
  67 #define AM437X_CTRL_USB2_PHY_PD                 BIT(0)
  68 #define AM437X_CTRL_USB2_OTG_PD                 BIT(1)
  69 #define AM437X_CTRL_USB2_OTGVDET_EN             BIT(19)
  70 #define AM437X_CTRL_USB2_OTGSESSEND_EN          BIT(20)
  71
  72 static LIST_HEAD(ti_usb_phy_list);
  73 typedef unsigned int u32;
  74
  75 struct usb3_dpll_params {
  76         u16     m;
  77         u8      n;
  78         u8      freq:3;
  79         u8      sd;
  80         u32     mf;
  81 };
  82
  83 struct usb3_dpll_map {
  84         unsigned long rate;
  85         struct usb3_dpll_params params;
  86         struct usb3_dpll_map *dpll_map;
  87 };
  88
  89 struct ti_usb_phy {
  90         void __iomem *pll_ctrl_base;
  91         void __iomem *usb2_phy_power;
  92         void __iomem *usb3_phy_power;
  93         struct usb3_dpll_map *dpll_map;
  94         struct list_head list;
  95         int index;
  96 };
  97
  98 static struct usb3_dpll_map dpll_map_usb[] = {
  99         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
 100         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
 101         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
 102         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
 103         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
 104         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
 105         { },                                    /* Terminator */
 106 };
 107
 108 static inline unsigned int ti_usb3_readl(void __iomem *base, u32 offset)
 109 {
 110         return readl(base + offset);
 111 }
 112
 113 static inline void ti_usb3_writel(void __iomem *base, u32 offset, u32 value)
 114 {
 115         writel(value, base + offset);
 116 }
 117
 118 #ifndef CONFIG_AM43XX
 119 static struct usb3_dpll_params *ti_usb3_get_dpll_params(struct ti_usb_phy *phy)
 120 {
 121         unsigned long rate;
 122         struct usb3_dpll_map *dpll_map = phy->dpll_map;
 123
 124         rate = get_sys_clk_freq();
 125
 126         for (; dpll_map->rate; dpll_map++) {
 127                 if (rate == dpll_map->rate)
 128                         return &dpll_map->params;
 129         }
 130
 131         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 132
 133         return NULL;
 134 }
 135
 136 static int ti_usb3_dpll_wait_lock(struct ti_usb_phy *phy)
 137 {
 138         u32 val;
 139         do {
 140                 val = ti_usb3_readl(phy->pll_ctrl_base, PLL_STATUS);
 141                         if (val & PLL_LOCK)
 142                                 break;
 143         } while (1);
 144
 145         return 0;
 146 }
 147
 148 static int ti_usb3_dpll_program(struct ti_usb_phy *phy)
 149 {
 150         u32                     val;
 151         struct usb3_dpll_params *dpll_params;
 152
 153         if (!phy->pll_ctrl_base)
 154                 return -EINVAL;
 155
 156         dpll_params = ti_usb3_get_dpll_params(phy);
 157         if (!dpll_params)
 158                 return -EINVAL;
 159
 160         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 161         val &= ~PLL_REGN_MASK;
 162         val |= dpll_params->n << PLL_REGN_SHIFT;
 163         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 164
 165         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 166         val &= ~PLL_SELFREQDCO_MASK;
 167         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 168         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 169
 170         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 171         val &= ~PLL_REGM_MASK;
 172         val |= dpll_params->m << PLL_REGM_SHIFT;
 173         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 174
 175         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 176         val &= ~PLL_REGM_F_MASK;
 177         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 178         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 179
 180         val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 181         val &= ~PLL_SD_MASK;
 182         val |= dpll_params->sd << PLL_SD_SHIFT;
 183         ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 184
 185         ti_usb3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 186
 187         return ti_usb3_dpll_wait_lock(phy);
 188 }
 189 #endif
 190
 191 void ti_usb2_phy_power(struct ti_usb_phy *phy, int on)
 192 {
 193         u32 val;
 194
 195         val = readl(phy->usb2_phy_power);
 196
 197         if (on) {
 198 #if defined(CONFIG_DRA7XX)
 199                 if (phy->index == 1)
 200                         val &= ~OMAP_CTRL_USB2_PHY_PD;
 201                 else
 202                         val &= ~OMAP_CTRL_DEV_PHY_PD;
 203 #elif defined(CONFIG_AM43XX)
 204                 val &= ~(AM437X_CTRL_USB2_PHY_PD |
 205                          AM437X_CTRL_USB2_OTG_PD);
 206                 val |= (AM437X_CTRL_USB2_OTGVDET_EN |
 207                         AM437X_CTRL_USB2_OTGSESSEND_EN);
 208 #endif
 209         } else {
 210 #if defined(CONFIG_DRA7XX)
 211                 if (phy->index == 1)
 212                         val |= OMAP_CTRL_USB2_PHY_PD;
 213                 else
 214                         val |= OMAP_CTRL_DEV_PHY_PD;
 215
 216 #elif defined(CONFIG_AM43XX)
 217                 val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
 218                          AM437X_CTRL_USB2_OTGSESSEND_EN);
 219                 val |= (AM437X_CTRL_USB2_PHY_PD |
 220                         AM437X_CTRL_USB2_OTG_PD);
 221 #endif
 222         }
 223         writel(val, phy->usb2_phy_power);
 224 }
 225
 226 #ifndef CONFIG_AM43XX
 227 void ti_usb3_phy_power(struct ti_usb_phy *phy, int on)
 228 {
 229         u32 val;
 230         u32 rate;
 231         rate = get_sys_clk_freq();
 232         rate = rate/1000000;
 233
 234         if (!phy->usb3_phy_power)
 235                 return;
 236
 237         val = readl(phy->usb3_phy_power);
 238         if (on) {
 239                 val &= ~(OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK |
 240                         OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK);
 241                 val |= (OMAP_CTRL_USB3_PHY_TX_RX_POWERON) <<
 242                         OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
 243                 val |= rate <<
 244                         OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 245         } else {
 246                 val &= ~OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK;
 247                 val |= OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF <<
 248                         OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
 249         }
 250         writel(val, phy->usb3_phy_power);
 251 }
 252 #endif
 253
 254 /**
 255  * ti_usb_phy_uboot_init - usb phy uboot initialization code
 256  * @dev: struct ti_usb_phy_device containing initialization data
 257  *
 258  * Entry point for ti usb phy driver. This driver handles initialization
 259  * of both usb2 phy and usb3 phy. Pointer to ti_usb_phy_device should be
 260  * passed containing base address and other initialization data.
 261  * Returns '0' on success and a negative value on failure.
 262  *
 263  * Generally called from board_usb_init() implemented in board file.
 264  */
 265 int ti_usb_phy_uboot_init(struct ti_usb_phy_device *dev)
 266 {
 267         struct ti_usb_phy *phy;
 268
 269         phy = devm_kzalloc(NULL, sizeof(*phy), GFP_KERNEL);
 270         if (!phy) {
 271                 dev_err(NULL, "unable to alloc mem for TI USB3 PHY\n");
 272                 return -ENOMEM;
 273         }
 274
 275         phy->dpll_map = dpll_map_usb;
 276         phy->index = dev->index;
 277         phy->pll_ctrl_base = dev->pll_ctrl_base;
 278         phy->usb2_phy_power = dev->usb2_phy_power;
 279         phy->usb3_phy_power = dev->usb3_phy_power;
 280
 281 #ifndef CONFIG_AM43XX
 282         ti_usb3_dpll_program(phy);
 283         ti_usb3_phy_power(phy, 1);
 284 #endif
 285         ti_usb2_phy_power(phy, 1);
 286         mdelay(150);
 287         list_add_tail(&phy->list, &ti_usb_phy_list);
 288
 289         return 0;
 290 }
 291
 292 /**
 293  * ti_usb_phy_uboot_exit - usb phy uboot cleanup code
 294  * @index: index of this controller
 295  *
 296  * Performs cleanup of memory allocated in ti_usb_phy_uboot_init.
 297  * index of _this_ controller should be passed and should match with
 298  * the index passed in ti_usb_phy_device during init.
 299  *
 300  * Generally called from board file.
 301  */
 302 void ti_usb_phy_uboot_exit(int index)
 303 {
 304         struct ti_usb_phy *phy = NULL;
 305
 306         list_for_each_entry(phy, &ti_usb_phy_list, list) {
 307                 if (phy->index != index)
 308                         continue;
 309
 310                 ti_usb2_phy_power(phy, 0);
 311 #ifndef CONFIG_AM43XX
 312                 ti_usb3_phy_power(phy, 0);
 313 #endif
 314                 list_del(&phy->list);
 315                 kfree(phy);
 316                 break;
 317         }
 318 }