drivers/usb/dwc3/samsung_usb_phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * samsung_usb_phy.c - DesignWare USB3 (DWC3) PHY handling file
   4  *
   5  * Copyright (C) 2015 Samsung Electronics
   6  *
   7  * Author: Joonyoung Shim <jy0922.shim@samsung.com>
   8  */
   9
  10 #include <common.h>
  11 #include <asm/arch/power.h>
  12 #include <asm/arch/xhci-exynos.h>
  13 #include <linux/delay.h>
  14
  15 void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
  16 {
  17         u32 reg;
  18
  19         /* Reset USB 3.0 PHY */
  20         writel(0x0, &phy->phy_reg0);
  21
  22         clrbits_le32(&phy->phy_param0,
  23                         /* Select PHY CLK source */
  24                         PHYPARAM0_REF_USE_PAD |
  25                         /* Set Loss-of-Signal Detector sensitivity */
  26                         PHYPARAM0_REF_LOSLEVEL_MASK);
  27         setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
  28
  29
  30         writel(0x0, &phy->phy_resume);
  31
  32         /*
  33          * Setting the Frame length Adj value[6:1] to default 0x20
  34          * See xHCI 1.0 spec, 5.2.4
  35          */
  36         setbits_le32(&phy->link_system,
  37                         LINKSYSTEM_XHCI_VERSION_CONTROL |
  38                         LINKSYSTEM_FLADJ(0x20));
  39
  40         /* Set Tx De-Emphasis level */
  41         clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
  42         setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
  43
  44         setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
  45
  46         /* PHYTEST POWERDOWN Control */
  47         clrbits_le32(&phy->phy_test,
  48                         PHYTEST_POWERDOWN_SSP |
  49                         PHYTEST_POWERDOWN_HSP);
  50
  51         /* UTMI Power Control */
  52         writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
  53
  54                 /* Use core clock from main PLL */
  55         reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
  56                 /* Default 24Mhz crystal clock */
  57                 PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
  58                 PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
  59                 PHYCLKRST_SSC_REFCLKSEL(0) |
  60                 /* Force PortReset of PHY */
  61                 PHYCLKRST_PORTRESET |
  62                 /* Digital power supply in normal operating mode */
  63                 PHYCLKRST_RETENABLEN |
  64                 /* Enable ref clock for SS function */
  65                 PHYCLKRST_REF_SSP_EN |
  66                 /* Enable spread spectrum */
  67                 PHYCLKRST_SSC_EN |
  68                 /* Power down HS Bias and PLL blocks in suspend mode */
  69                 PHYCLKRST_COMMONONN;
  70
  71         writel(reg, &phy->phy_clk_rst);
  72
  73         /* giving time to Phy clock to settle before resetting */
  74         udelay(10);
  75
  76         reg &= ~PHYCLKRST_PORTRESET;
  77         writel(reg, &phy->phy_clk_rst);
  78 }