drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
  11  * to uboot.
  12  *
  13  * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
  14  */
  15
  16 #include <common.h>
  17 #include <cpu_func.h>
  18 #include <log.h>
  19 #include <malloc.h>
  20 #include <dm/device_compat.h>
  21 #include <dm/devres.h>
  22 #include <linux/bug.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/list.h>
  26
  27 #include <linux/usb/ch9.h>
  28 #include <linux/usb/gadget.h>
  29
  30 #include "core.h"
  31 #include "gadget.h"
  32 #include "io.h"
  33
  34 #include "linux-compat.h"
  35
  36 /**
  37  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  38  * @dwc: pointer to our context structure
  39  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  40  *
  41  * Caller should take care of locking. This function will
  42  * return 0 on success or -EINVAL if wrong Test Selector
  43  * is passed
  44  */
  45 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  46 {
  47         u32             reg;
  48
  49         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  50         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  51
  52         switch (mode) {
  53         case TEST_J:
  54         case TEST_K:
  55         case TEST_SE0_NAK:
  56         case TEST_PACKET:
  57         case TEST_FORCE_EN:
  58                 reg |= mode << 1;
  59                 break;
  60         default:
  61                 return -EINVAL;
  62         }
  63
  64         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  65
  66         return 0;
  67 }
  68
  69 /**
  70  * dwc3_gadget_get_link_state - Gets current state of USB Link
  71  * @dwc: pointer to our context structure
  72  *
  73  * Caller should take care of locking. This function will
  74  * return the link state on success (>= 0) or -ETIMEDOUT.
  75  */
  76 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  77 {
  78         u32             reg;
  79
  80         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  81
  82         return DWC3_DSTS_USBLNKST(reg);
  83 }
  84
  85 /**
  86  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  87  * @dwc: pointer to our context structure
  88  * @state: the state to put link into
  89  *
  90  * Caller should take care of locking. This function will
  91  * return 0 on success or -ETIMEDOUT.
  92  */
  93 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  94 {
  95         int             retries = 10000;
  96         u32             reg;
  97
  98         /*
  99          * Wait until device controller is ready. Only applies to 1.94a and
 100          * later RTL.
 101          */
 102         if (dwc->revision >= DWC3_REVISION_194A) {
 103                 while (--retries) {
 104                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 105                         if (reg & DWC3_DSTS_DCNRD)
 106                                 udelay(5);
 107                         else
 108                                 break;
 109                 }
 110
 111                 if (retries <= 0)
 112                         return -ETIMEDOUT;
 113         }
 114
 115         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 116         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 117
 118         /* set requested state */
 119         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 120         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 121
 122         /*
 123          * The following code is racy when called from dwc3_gadget_wakeup,
 124          * and is not needed, at least on newer versions
 125          */
 126         if (dwc->revision >= DWC3_REVISION_194A)
 127                 return 0;
 128
 129         /* wait for a change in DSTS */
 130         retries = 10000;
 131         while (--retries) {
 132                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 133
 134                 if (DWC3_DSTS_USBLNKST(reg) == state)
 135                         return 0;
 136
 137                 udelay(5);
 138         }
 139
 140         dev_vdbg(dwc->dev, "link state change request timed out\n");
 141
 142         return -ETIMEDOUT;
 143 }
 144
 145 /**
 146  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 147  * @dwc: pointer to our context structure
 148  *
 149  * This function will a best effort FIFO allocation in order
 150  * to improve FIFO usage and throughput, while still allowing
 151  * us to enable as many endpoints as possible.
 152  *
 153  * Keep in mind that this operation will be highly dependent
 154  * on the configured size for RAM1 - which contains TxFifo -,
 155  * the amount of endpoints enabled on coreConsultant tool, and
 156  * the width of the Master Bus.
 157  *
 158  * In the ideal world, we would always be able to satisfy the
 159  * following equation:
 160  *
 161  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 162  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 163  *
 164  * Unfortunately, due to many variables that's not always the case.
 165  */
 166 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 167 {
 168         int             last_fifo_depth = 0;
 169         int             fifo_size;
 170         int             mdwidth;
 171         int             num;
 172
 173         if (!dwc->needs_fifo_resize)
 174                 return 0;
 175
 176         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 177
 178         /* MDWIDTH is represented in bits, we need it in bytes */
 179         mdwidth >>= 3;
 180
 181         /*
 182          * FIXME For now we will only allocate 1 wMaxPacketSize space
 183          * for each enabled endpoint, later patches will come to
 184          * improve this algorithm so that we better use the internal
 185          * FIFO space
 186          */
 187         for (num = 0; num < dwc->num_in_eps; num++) {
 188                 /* bit0 indicates direction; 1 means IN ep */
 189                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 190                 int             mult = 1;
 191                 int             tmp;
 192
 193                 if (!(dep->flags & DWC3_EP_ENABLED))
 194                         continue;
 195
 196                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 197                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 198                         mult = 3;
 199
 200                 /*
 201                  * REVISIT: the following assumes we will always have enough
 202                  * space available on the FIFO RAM for all possible use cases.
 203                  * Make sure that's true somehow and change FIFO allocation
 204                  * accordingly.
 205                  *
 206                  * If we have Bulk or Isochronous endpoints, we want
 207                  * them to be able to be very, very fast. So we're giving
 208                  * those endpoints a fifo_size which is enough for 3 full
 209                  * packets
 210                  */
 211                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 212                 tmp += mdwidth;
 213
 214                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 215
 216                 fifo_size |= (last_fifo_depth << 16);
 217
 218                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 219                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 220
 221                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 222
 223                 last_fifo_depth += (fifo_size & 0xffff);
 224         }
 225
 226         return 0;
 227 }
 228
 229 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 230                 int status)
 231 {
 232         struct dwc3                     *dwc = dep->dwc;
 233
 234         if (req->queued) {
 235                 dep->busy_slot++;
 236                 /*
 237                  * Skip LINK TRB. We can't use req->trb and check for
 238                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 239                  * just completed (not the LINK TRB).
 240                  */
 241                 if (((dep->busy_slot & DWC3_TRB_MASK) ==
 242                         DWC3_TRB_NUM- 1) &&
 243                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 244                         dep->busy_slot++;
 245                 req->queued = false;
 246         }
 247
 248         list_del(&req->list);
 249         req->trb = NULL;
 250         if (req->request.length)
 251                 dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
 252
 253         if (req->request.status == -EINPROGRESS)
 254                 req->request.status = status;
 255
 256         if (dwc->ep0_bounced && dep->number == 0)
 257                 dwc->ep0_bounced = false;
 258         else
 259                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 260                                 req->direction);
 261
 262         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 263                         req, dep->name, req->request.actual,
 264                         req->request.length, status);
 265
 266         spin_unlock(&dwc->lock);
 267         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 268         spin_lock(&dwc->lock);
 269 }
 270
 271 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 272 {
 273         u32             timeout = 500;
 274         u32             reg;
 275
 276         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 277         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 278
 279         do {
 280                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 281                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 282                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 283                                         DWC3_DGCMD_STATUS(reg));
 284                         return 0;
 285                 }
 286
 287                 /*
 288                  * We can't sleep here, because it's also called from
 289                  * interrupt context.
 290                  */
 291                 timeout--;
 292                 if (!timeout)
 293                         return -ETIMEDOUT;
 294                 udelay(1);
 295         } while (1);
 296 }
 297
 298 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 299                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 300 {
 301         u32                     timeout = 500;
 302         u32                     reg;
 303
 304         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 305         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 306         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 307
 308         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 309         do {
 310                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 311                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 312                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 313                                         DWC3_DEPCMD_STATUS(reg));
 314                         return 0;
 315                 }
 316
 317                 /*
 318                  * We can't sleep here, because it is also called from
 319                  * interrupt context.
 320                  */
 321                 timeout--;
 322                 if (!timeout)
 323                         return -ETIMEDOUT;
 324
 325                 udelay(1);
 326         } while (1);
 327 }
 328
 329 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 330                 struct dwc3_trb *trb)
 331 {
 332         u32             offset = (char *) trb - (char *) dep->trb_pool;
 333
 334         return dep->trb_pool_dma + offset;
 335 }
 336
 337 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 338 {
 339         if (dep->trb_pool)
 340                 return 0;
 341
 342         if (dep->number == 0 || dep->number == 1)
 343                 return 0;
 344
 345         dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
 346                                            DWC3_TRB_NUM,
 347                                            (unsigned long *)&dep->trb_pool_dma);
 348         if (!dep->trb_pool) {
 349                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 350                                 dep->name);
 351                 return -ENOMEM;
 352         }
 353
 354         return 0;
 355 }
 356
 357 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 358 {
 359         dma_free_coherent(dep->trb_pool);
 360
 361         dep->trb_pool = NULL;
 362         dep->trb_pool_dma = 0;
 363 }
 364
 365 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 366 {
 367         struct dwc3_gadget_ep_cmd_params params;
 368         u32                     cmd;
 369
 370         memset(&params, 0x00, sizeof(params));
 371
 372         if (dep->number != 1) {
 373                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 374                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 375                 if (dep->number > 1) {
 376                         if (dwc->start_config_issued)
 377                                 return 0;
 378                         dwc->start_config_issued = true;
 379                         cmd |= DWC3_DEPCMD_PARAM(2);
 380                 }
 381
 382                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 389                 const struct usb_endpoint_descriptor *desc,
 390                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 391                 bool ignore, bool restore)
 392 {
 393         struct dwc3_gadget_ep_cmd_params params;
 394
 395         memset(&params, 0x00, sizeof(params));
 396
 397         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 398                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 399
 400         /* Burst size is only needed in SuperSpeed mode */
 401         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 402                 u32 burst = dep->endpoint.maxburst - 1;
 403
 404                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 405         }
 406
 407         if (ignore)
 408                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 409
 410         if (restore) {
 411                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 412                 params.param2 |= dep->saved_state;
 413         }
 414
 415         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 416                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 417
 418         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 419                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 420                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 421                 dep->stream_capable = true;
 422         }
 423
 424         if (!usb_endpoint_xfer_control(desc))
 425                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 426
 427         /*
 428          * We are doing 1:1 mapping for endpoints, meaning
 429          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 430          * so on. We consider the direction bit as part of the physical
 431          * endpoint number. So USB endpoint 0x81 is 0x03.
 432          */
 433         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 434
 435         /*
 436          * We must use the lower 16 TX FIFOs even though
 437          * HW might have more
 438          */
 439         if (dep->direction)
 440                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 441
 442         if (desc->bInterval) {
 443                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 444                 dep->interval = 1 << (desc->bInterval - 1);
 445         }
 446
 447         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 448                         DWC3_DEPCMD_SETEPCONFIG, &params);
 449 }
 450
 451 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 452 {
 453         struct dwc3_gadget_ep_cmd_params params;
 454
 455         memset(&params, 0x00, sizeof(params));
 456
 457         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 458
 459         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 460                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 461 }
 462
 463 /**
 464  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 465  * @dep: endpoint to be initialized
 466  * @desc: USB Endpoint Descriptor
 467  *
 468  * Caller should take care of locking
 469  */
 470 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 471                 const struct usb_endpoint_descriptor *desc,
 472                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 473                 bool ignore, bool restore)
 474 {
 475         struct dwc3             *dwc = dep->dwc;
 476         u32                     reg;
 477         int                     ret;
 478
 479         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 480
 481         if (!(dep->flags & DWC3_EP_ENABLED)) {
 482                 ret = dwc3_gadget_start_config(dwc, dep);
 483                 if (ret)
 484                         return ret;
 485         }
 486
 487         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 488                         restore);
 489         if (ret)
 490                 return ret;
 491
 492         if (!(dep->flags & DWC3_EP_ENABLED)) {
 493                 struct dwc3_trb *trb_st_hw;
 494                 struct dwc3_trb *trb_link;
 495
 496                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 497                 if (ret)
 498                         return ret;
 499
 500                 dep->endpoint.desc = desc;
 501                 dep->comp_desc = comp_desc;
 502                 dep->type = usb_endpoint_type(desc);
 503                 dep->flags |= DWC3_EP_ENABLED;
 504
 505                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 506                 reg |= DWC3_DALEPENA_EP(dep->number);
 507                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 508
 509                 if (!usb_endpoint_xfer_isoc(desc))
 510                         return 0;
 511
 512                 /* Link TRB for ISOC. The HWO bit is never reset */
 513                 trb_st_hw = &dep->trb_pool[0];
 514
 515                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 516                 memset(trb_link, 0, sizeof(*trb_link));
 517
 518                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 519                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 520                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 521                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 522         }
 523
 524         return 0;
 525 }
 526
 527 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 528 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 529 {
 530         struct dwc3_request             *req;
 531
 532         if (!list_empty(&dep->req_queued)) {
 533                 dwc3_stop_active_transfer(dwc, dep->number, true);
 534
 535                 /* - giveback all requests to gadget driver */
 536                 while (!list_empty(&dep->req_queued)) {
 537                         req = next_request(&dep->req_queued);
 538
 539                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 540                 }
 541         }
 542
 543         while (!list_empty(&dep->request_list)) {
 544                 req = next_request(&dep->request_list);
 545
 546                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 547         }
 548 }
 549
 550 /**
 551  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 552  * @dep: the endpoint to disable
 553  *
 554  * This function also removes requests which are currently processed ny the
 555  * hardware and those which are not yet scheduled.
 556  * Caller should take care of locking.
 557  */
 558 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 559 {
 560         struct dwc3             *dwc = dep->dwc;
 561         u32                     reg;
 562
 563         dwc3_remove_requests(dwc, dep);
 564
 565         /* make sure HW endpoint isn't stalled */
 566         if (dep->flags & DWC3_EP_STALL)
 567                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 568
 569         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 570         reg &= ~DWC3_DALEPENA_EP(dep->number);
 571         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 572
 573         dep->stream_capable = false;
 574         dep->endpoint.desc = NULL;
 575         dep->comp_desc = NULL;
 576         dep->type = 0;
 577         dep->flags = 0;
 578
 579         return 0;
 580 }
 581
 582 /* -------------------------------------------------------------------------- */
 583
 584 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 585                 const struct usb_endpoint_descriptor *desc)
 586 {
 587         return -EINVAL;
 588 }
 589
 590 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 591 {
 592         return -EINVAL;
 593 }
 594
 595 /* -------------------------------------------------------------------------- */
 596
 597 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 598                 const struct usb_endpoint_descriptor *desc)
 599 {
 600         struct dwc3_ep                  *dep;
 601         unsigned long                   flags;
 602         int                             ret;
 603
 604         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 605                 pr_debug("dwc3: invalid parameters\n");
 606                 return -EINVAL;
 607         }
 608
 609         if (!desc->wMaxPacketSize) {
 610                 pr_debug("dwc3: missing wMaxPacketSize\n");
 611                 return -EINVAL;
 612         }
 613
 614         dep = to_dwc3_ep(ep);
 615
 616         if (dep->flags & DWC3_EP_ENABLED) {
 617                 WARN(true, "%s is already enabled\n",
 618                                 dep->name);
 619                 return 0;
 620         }
 621
 622         switch (usb_endpoint_type(desc)) {
 623         case USB_ENDPOINT_XFER_CONTROL:
 624                 strlcat(dep->name, "-control", sizeof(dep->name));
 625                 break;
 626         case USB_ENDPOINT_XFER_ISOC:
 627                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 628                 break;
 629         case USB_ENDPOINT_XFER_BULK:
 630                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 631                 break;
 632         case USB_ENDPOINT_XFER_INT:
 633                 strlcat(dep->name, "-int", sizeof(dep->name));
 634                 break;
 635         default:
 636                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 637         }
 638
 639         spin_lock_irqsave(&dwc->lock, flags);
 640         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 641         spin_unlock_irqrestore(&dwc->lock, flags);
 642
 643         return ret;
 644 }
 645
 646 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 647 {
 648         struct dwc3_ep                  *dep;
 649         unsigned long                   flags;
 650         int                             ret;
 651
 652         if (!ep) {
 653                 pr_debug("dwc3: invalid parameters\n");
 654                 return -EINVAL;
 655         }
 656
 657         dep = to_dwc3_ep(ep);
 658
 659         if (!(dep->flags & DWC3_EP_ENABLED)) {
 660                 WARN(true, "%s is already disabled\n",
 661                                 dep->name);
 662                 return 0;
 663         }
 664
 665         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 666                         dep->number >> 1,
 667                         (dep->number & 1) ? "in" : "out");
 668
 669         spin_lock_irqsave(&dwc->lock, flags);
 670         ret = __dwc3_gadget_ep_disable(dep);
 671         spin_unlock_irqrestore(&dwc->lock, flags);
 672
 673         return ret;
 674 }
 675
 676 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 677         gfp_t gfp_flags)
 678 {
 679         struct dwc3_request             *req;
 680         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 681
 682         req = kzalloc(sizeof(*req), gfp_flags);
 683         if (!req)
 684                 return NULL;
 685
 686         req->epnum      = dep->number;
 687         req->dep        = dep;
 688
 689         return &req->request;
 690 }
 691
 692 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 693                 struct usb_request *request)
 694 {
 695         struct dwc3_request             *req = to_dwc3_request(request);
 696
 697         kfree(req);
 698 }
 699
 700 /**
 701  * dwc3_prepare_one_trb - setup one TRB from one request
 702  * @dep: endpoint for which this request is prepared
 703  * @req: dwc3_request pointer
 704  */
 705 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 706                 struct dwc3_request *req, dma_addr_t dma,
 707                 unsigned length, unsigned last, unsigned chain, unsigned node)
 708 {
 709         struct dwc3_trb         *trb;
 710
 711         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 712                         dep->name, req, (unsigned long long) dma,
 713                         length, last ? " last" : "",
 714                         chain ? " chain" : "");
 715
 716
 717         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 718
 719         if (!req->trb) {
 720                 dwc3_gadget_move_request_queued(req);
 721                 req->trb = trb;
 722                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 723                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 724         }
 725
 726         dep->free_slot++;
 727         /* Skip the LINK-TRB on ISOC */
 728         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 729                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 730                 dep->free_slot++;
 731
 732         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 733         trb->bpl = lower_32_bits(dma);
 734         trb->bph = upper_32_bits(dma);
 735
 736         switch (usb_endpoint_type(dep->endpoint.desc)) {
 737         case USB_ENDPOINT_XFER_CONTROL:
 738                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 739                 break;
 740
 741         case USB_ENDPOINT_XFER_ISOC:
 742                 if (!node)
 743                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 744                 else
 745                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 746                 break;
 747
 748         case USB_ENDPOINT_XFER_BULK:
 749         case USB_ENDPOINT_XFER_INT:
 750                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 751                 break;
 752         default:
 753                 /*
 754                  * This is only possible with faulty memory because we
 755                  * checked it already :)
 756                  */
 757                 BUG();
 758         }
 759
 760         if (!req->request.no_interrupt && !chain)
 761                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 762
 763         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 764                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 765                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 766         } else if (last) {
 767                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 768         }
 769
 770         if (chain)
 771                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 772
 773         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 774                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 775
 776         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 777
 778         dwc3_flush_cache((uintptr_t)dma, length);
 779         dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
 780 }
 781
 782 /*
 783  * dwc3_prepare_trbs - setup TRBs from requests
 784  * @dep: endpoint for which requests are being prepared
 785  * @starting: true if the endpoint is idle and no requests are queued.
 786  *
 787  * The function goes through the requests list and sets up TRBs for the
 788  * transfers. The function returns once there are no more TRBs available or
 789  * it runs out of requests.
 790  */
 791 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 792 {
 793         struct dwc3_request     *req, *n;
 794         u32                     trbs_left;
 795         u32                     max;
 796
 797         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 798
 799         /* the first request must not be queued */
 800         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 801
 802         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 803         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 804                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 805                 if (trbs_left > max)
 806                         trbs_left = max;
 807         }
 808
 809         /*
 810          * If busy & slot are equal than it is either full or empty. If we are
 811          * starting to process requests then we are empty. Otherwise we are
 812          * full and don't do anything
 813          */
 814         if (!trbs_left) {
 815                 if (!starting)
 816                         return;
 817                 trbs_left = DWC3_TRB_NUM;
 818                 /*
 819                  * In case we start from scratch, we queue the ISOC requests
 820                  * starting from slot 1. This is done because we use ring
 821                  * buffer and have no LST bit to stop us. Instead, we place
 822                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 823                  * after the first request so we start at slot 1 and have
 824                  * 7 requests proceed before we hit the first IOC.
 825                  * Other transfer types don't use the ring buffer and are
 826                  * processed from the first TRB until the last one. Since we
 827                  * don't wrap around we have to start at the beginning.
 828                  */
 829                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 830                         dep->busy_slot = 1;
 831                         dep->free_slot = 1;
 832                 } else {
 833                         dep->busy_slot = 0;
 834                         dep->free_slot = 0;
 835                 }
 836         }
 837
 838         /* The last TRB is a link TRB, not used for xfer */
 839         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 840                 return;
 841
 842         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 843                 unsigned        length;
 844                 dma_addr_t      dma;
 845
 846                 dma = req->request.dma;
 847                 length = req->request.length;
 848
 849                 dwc3_prepare_one_trb(dep, req, dma, length,
 850                                      true, false, 0);
 851
 852                 break;
 853         }
 854 }
 855
 856 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 857                 int start_new)
 858 {
 859         struct dwc3_gadget_ep_cmd_params params;
 860         struct dwc3_request             *req;
 861         struct dwc3                     *dwc = dep->dwc;
 862         int                             ret;
 863         u32                             cmd;
 864
 865         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 866                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 867                 return -EBUSY;
 868         }
 869         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 870
 871         /*
 872          * If we are getting here after a short-out-packet we don't enqueue any
 873          * new requests as we try to set the IOC bit only on the last request.
 874          */
 875         if (start_new) {
 876                 if (list_empty(&dep->req_queued))
 877                         dwc3_prepare_trbs(dep, start_new);
 878
 879                 /* req points to the first request which will be sent */
 880                 req = next_request(&dep->req_queued);
 881         } else {
 882                 dwc3_prepare_trbs(dep, start_new);
 883
 884                 /*
 885                  * req points to the first request where HWO changed from 0 to 1
 886                  */
 887                 req = next_request(&dep->req_queued);
 888         }
 889         if (!req) {
 890                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 891                 return 0;
 892         }
 893
 894         memset(&params, 0, sizeof(params));
 895
 896         if (start_new) {
 897                 params.param0 = upper_32_bits(req->trb_dma);
 898                 params.param1 = lower_32_bits(req->trb_dma);
 899                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 900         } else {
 901                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 902         }
 903
 904         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 905         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 906         if (ret < 0) {
 907                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 908
 909                 /*
 910                  * FIXME we need to iterate over the list of requests
 911                  * here and stop, unmap, free and del each of the linked
 912                  * requests instead of what we do now.
 913                  */
 914                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 915                                 req->direction);
 916                 list_del(&req->list);
 917                 return ret;
 918         }
 919
 920         dep->flags |= DWC3_EP_BUSY;
 921
 922         if (start_new) {
 923                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 924                                 dep->number);
 925                 WARN_ON_ONCE(!dep->resource_index);
 926         }
 927
 928         return 0;
 929 }
 930
 931 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 932                 struct dwc3_ep *dep, u32 cur_uf)
 933 {
 934         u32 uf;
 935
 936         if (list_empty(&dep->request_list)) {
 937                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
 938                         dep->name);
 939                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 940                 return;
 941         }
 942
 943         /* 4 micro frames in the future */
 944         uf = cur_uf + dep->interval * 4;
 945
 946         __dwc3_gadget_kick_transfer(dep, uf, 1);
 947 }
 948
 949 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 950                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 951 {
 952         u32 cur_uf, mask;
 953
 954         mask = ~(dep->interval - 1);
 955         cur_uf = event->parameters & mask;
 956
 957         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 958 }
 959
 960 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 961 {
 962         struct dwc3             *dwc = dep->dwc;
 963         int                     ret;
 964
 965         req->request.actual     = 0;
 966         req->request.status     = -EINPROGRESS;
 967         req->direction          = dep->direction;
 968         req->epnum              = dep->number;
 969
 970         /*
 971          * DWC3 hangs on OUT requests smaller than maxpacket size,
 972          * so HACK the request length
 973          */
 974         if (dep->direction == 0 &&
 975             req->request.length < dep->endpoint.maxpacket)
 976                 req->request.length = dep->endpoint.maxpacket;
 977
 978         /*
 979          * We only add to our list of requests now and
 980          * start consuming the list once we get XferNotReady
 981          * IRQ.
 982          *
 983          * That way, we avoid doing anything that we don't need
 984          * to do now and defer it until the point we receive a
 985          * particular token from the Host side.
 986          *
 987          * This will also avoid Host cancelling URBs due to too
 988          * many NAKs.
 989          */
 990         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 991                         dep->direction);
 992         if (ret)
 993                 return ret;
 994
 995         list_add_tail(&req->list, &dep->request_list);
 996
 997         /*
 998          * There are a few special cases:
 999          *
1000          * 1. XferNotReady with empty list of requests. We need to kick the
1001          *    transfer here in that situation, otherwise we will be NAKing
1002          *    forever. If we get XferNotReady before gadget driver has a
1003          *    chance to queue a request, we will ACK the IRQ but won't be
1004          *    able to receive the data until the next request is queued.
1005          *    The following code is handling exactly that.
1006          *
1007          */
1008         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1009                 /*
1010                  * If xfernotready is already elapsed and it is a case
1011                  * of isoc transfer, then issue END TRANSFER, so that
1012                  * you can receive xfernotready again and can have
1013                  * notion of current microframe.
1014                  */
1015                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1016                         if (list_empty(&dep->req_queued)) {
1017                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1018                                 dep->flags = DWC3_EP_ENABLED;
1019                         }
1020                         return 0;
1021                 }
1022
1023                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1024                 if (ret && ret != -EBUSY)
1025                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1026                                         dep->name);
1027                 return ret;
1028         }
1029
1030         /*
1031          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1032          *    kick the transfer here after queuing a request, otherwise the
1033          *    core may not see the modified TRB(s).
1034          */
1035         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1036                         (dep->flags & DWC3_EP_BUSY) &&
1037                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1038                 WARN_ON_ONCE(!dep->resource_index);
1039                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1040                                 false);
1041                 if (ret && ret != -EBUSY)
1042                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1043                                         dep->name);
1044                 return ret;
1045         }
1046
1047         /*
1048          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1049          * right away, otherwise host will not know we have streams to be
1050          * handled.
1051          */
1052         if (dep->stream_capable) {
1053                 int     ret;
1054
1055                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1056                 if (ret && ret != -EBUSY) {
1057                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1058                                         dep->name);
1059                 }
1060         }
1061
1062         return 0;
1063 }
1064
1065 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1066         gfp_t gfp_flags)
1067 {
1068         struct dwc3_request             *req = to_dwc3_request(request);
1069         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1070
1071         unsigned long                   flags;
1072
1073         int                             ret;
1074
1075         spin_lock_irqsave(&dwc->lock, flags);
1076         if (!dep->endpoint.desc) {
1077                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1078                                 request, ep->name);
1079                 ret = -ESHUTDOWN;
1080                 goto out;
1081         }
1082
1083         if (req->dep != dep) {
1084                 WARN(true, "request %p belongs to '%s'\n",
1085                                 request, req->dep->name);
1086                 ret = -EINVAL;
1087                 goto out;
1088         }
1089
1090         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1091                         request, ep->name, request->length);
1092
1093         ret = __dwc3_gadget_ep_queue(dep, req);
1094
1095 out:
1096         spin_unlock_irqrestore(&dwc->lock, flags);
1097
1098         return ret;
1099 }
1100
1101 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1102                 struct usb_request *request)
1103 {
1104         struct dwc3_request             *req = to_dwc3_request(request);
1105         struct dwc3_request             *r = NULL;
1106
1107         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1108         struct dwc3                     *dwc = dep->dwc;
1109
1110         unsigned long                   flags;
1111         int                             ret = 0;
1112
1113         spin_lock_irqsave(&dwc->lock, flags);
1114
1115         list_for_each_entry(r, &dep->request_list, list) {
1116                 if (r == req)
1117                         break;
1118         }
1119
1120         if (r != req) {
1121                 list_for_each_entry(r, &dep->req_queued, list) {
1122                         if (r == req)
1123                                 break;
1124                 }
1125                 if (r == req) {
1126                         /* wait until it is processed */
1127                         dwc3_stop_active_transfer(dwc, dep->number, true);
1128                         goto out1;
1129                 }
1130                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1131                                 request, ep->name);
1132                 ret = -EINVAL;
1133                 goto out0;
1134         }
1135
1136 out1:
1137         /* giveback the request */
1138         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1139
1140 out0:
1141         spin_unlock_irqrestore(&dwc->lock, flags);
1142
1143         return ret;
1144 }
1145
1146 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1147 {
1148         struct dwc3_gadget_ep_cmd_params        params;
1149         struct dwc3                             *dwc = dep->dwc;
1150         int                                     ret;
1151
1152         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1153                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1154                 return -EINVAL;
1155         }
1156
1157         memset(&params, 0x00, sizeof(params));
1158
1159         if (value) {
1160                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1161                                 (!list_empty(&dep->req_queued) ||
1162                                  !list_empty(&dep->request_list)))) {
1163                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1164                                         dep->name);
1165                         return -EAGAIN;
1166                 }
1167
1168                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1169                         DWC3_DEPCMD_SETSTALL, &params);
1170                 if (ret)
1171                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1172                                         dep->name);
1173                 else
1174                         dep->flags |= DWC3_EP_STALL;
1175         } else {
1176                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1177                         DWC3_DEPCMD_CLEARSTALL, &params);
1178                 if (ret)
1179                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1180                                         dep->name);
1181                 else
1182                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1183         }
1184
1185         return ret;
1186 }
1187
1188 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1189 {
1190         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1191
1192         unsigned long                   flags;
1193
1194         int                             ret;
1195
1196         spin_lock_irqsave(&dwc->lock, flags);
1197         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1198         spin_unlock_irqrestore(&dwc->lock, flags);
1199
1200         return ret;
1201 }
1202
1203 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1204 {
1205         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1206         unsigned long                   flags;
1207         int                             ret;
1208
1209         spin_lock_irqsave(&dwc->lock, flags);
1210         dep->flags |= DWC3_EP_WEDGE;
1211
1212         if (dep->number == 0 || dep->number == 1)
1213                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1214         else
1215                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1216         spin_unlock_irqrestore(&dwc->lock, flags);
1217
1218         return ret;
1219 }
1220
1221 /* -------------------------------------------------------------------------- */
1222
1223 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1224         .bLength        = USB_DT_ENDPOINT_SIZE,
1225         .bDescriptorType = USB_DT_ENDPOINT,
1226         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1227 };
1228
1229 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1230         .enable         = dwc3_gadget_ep0_enable,
1231         .disable        = dwc3_gadget_ep0_disable,
1232         .alloc_request  = dwc3_gadget_ep_alloc_request,
1233         .free_request   = dwc3_gadget_ep_free_request,
1234         .queue          = dwc3_gadget_ep0_queue,
1235         .dequeue        = dwc3_gadget_ep_dequeue,
1236         .set_halt       = dwc3_gadget_ep0_set_halt,
1237         .set_wedge      = dwc3_gadget_ep_set_wedge,
1238 };
1239
1240 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1241         .enable         = dwc3_gadget_ep_enable,
1242         .disable        = dwc3_gadget_ep_disable,
1243         .alloc_request  = dwc3_gadget_ep_alloc_request,
1244         .free_request   = dwc3_gadget_ep_free_request,
1245         .queue          = dwc3_gadget_ep_queue,
1246         .dequeue        = dwc3_gadget_ep_dequeue,
1247         .set_halt       = dwc3_gadget_ep_set_halt,
1248         .set_wedge      = dwc3_gadget_ep_set_wedge,
1249 };
1250
1251 /* -------------------------------------------------------------------------- */
1252
1253 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1254 {
1255         struct dwc3             *dwc = gadget_to_dwc(g);
1256         u32                     reg;
1257
1258         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1259         return DWC3_DSTS_SOFFN(reg);
1260 }
1261
1262 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1263 {
1264         struct dwc3             *dwc = gadget_to_dwc(g);
1265
1266         unsigned long           timeout;
1267         unsigned long           flags;
1268
1269         u32                     reg;
1270
1271         int                     ret = 0;
1272
1273         u8                      link_state;
1274         u8                      speed;
1275
1276         spin_lock_irqsave(&dwc->lock, flags);
1277
1278         /*
1279          * According to the Databook Remote wakeup request should
1280          * be issued only when the device is in early suspend state.
1281          *
1282          * We can check that via USB Link State bits in DSTS register.
1283          */
1284         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1285
1286         speed = reg & DWC3_DSTS_CONNECTSPD;
1287         if (speed == DWC3_DSTS_SUPERSPEED) {
1288                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1289                 ret = -EINVAL;
1290                 goto out;
1291         }
1292
1293         link_state = DWC3_DSTS_USBLNKST(reg);
1294
1295         switch (link_state) {
1296         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1297         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1298                 break;
1299         default:
1300                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1301                                 link_state);
1302                 ret = -EINVAL;
1303                 goto out;
1304         }
1305
1306         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1307         if (ret < 0) {
1308                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1309                 goto out;
1310         }
1311
1312         /* Recent versions do this automatically */
1313         if (dwc->revision < DWC3_REVISION_194A) {
1314                 /* write zeroes to Link Change Request */
1315                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1316                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1317                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1318         }
1319
1320         /* poll until Link State changes to ON */
1321         timeout = 1000;
1322
1323         while (timeout--) {
1324                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1325
1326                 /* in HS, means ON */
1327                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1328                         break;
1329         }
1330
1331         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1332                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1333                 ret = -EINVAL;
1334         }
1335
1336 out:
1337         spin_unlock_irqrestore(&dwc->lock, flags);
1338
1339         return ret;
1340 }
1341
1342 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1343                 int is_selfpowered)
1344 {
1345         struct dwc3             *dwc = gadget_to_dwc(g);
1346         unsigned long           flags;
1347
1348         spin_lock_irqsave(&dwc->lock, flags);
1349         dwc->is_selfpowered = !!is_selfpowered;
1350         spin_unlock_irqrestore(&dwc->lock, flags);
1351
1352         return 0;
1353 }
1354
1355 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1356 {
1357         u32                     reg;
1358         u32                     timeout = 500;
1359
1360         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1361         if (is_on) {
1362                 if (dwc->revision <= DWC3_REVISION_187A) {
1363                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1364                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1365                 }
1366
1367                 if (dwc->revision >= DWC3_REVISION_194A)
1368                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1369                 reg |= DWC3_DCTL_RUN_STOP;
1370
1371                 if (dwc->has_hibernation)
1372                         reg |= DWC3_DCTL_KEEP_CONNECT;
1373
1374                 dwc->pullups_connected = true;
1375         } else {
1376                 reg &= ~DWC3_DCTL_RUN_STOP;
1377
1378                 if (dwc->has_hibernation && !suspend)
1379                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1380
1381                 dwc->pullups_connected = false;
1382         }
1383
1384         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1385
1386         do {
1387                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1388                 if (is_on) {
1389                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1390                                 break;
1391                 } else {
1392                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1393                                 break;
1394                 }
1395                 timeout--;
1396                 if (!timeout)
1397                         return -ETIMEDOUT;
1398                 udelay(1);
1399         } while (1);
1400
1401         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1402                         dwc->gadget_driver
1403                         ? dwc->gadget_driver->function : "no-function",
1404                         is_on ? "connect" : "disconnect");
1405
1406         return 0;
1407 }
1408
1409 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1410 {
1411         struct dwc3             *dwc = gadget_to_dwc(g);
1412         unsigned long           flags;
1413         int                     ret;
1414
1415         is_on = !!is_on;
1416
1417         spin_lock_irqsave(&dwc->lock, flags);
1418         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1419         spin_unlock_irqrestore(&dwc->lock, flags);
1420
1421         return ret;
1422 }
1423
1424 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1425 {
1426         u32                     reg;
1427
1428         /* Enable all but Start and End of Frame IRQs */
1429         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1430                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1431                         DWC3_DEVTEN_CMDCMPLTEN |
1432                         DWC3_DEVTEN_ERRTICERREN |
1433                         DWC3_DEVTEN_WKUPEVTEN |
1434                         DWC3_DEVTEN_ULSTCNGEN |
1435                         DWC3_DEVTEN_CONNECTDONEEN |
1436                         DWC3_DEVTEN_USBRSTEN |
1437                         DWC3_DEVTEN_DISCONNEVTEN);
1438
1439         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1440 }
1441
1442 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1443 {
1444         /* mask all interrupts */
1445         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1446 }
1447
1448 static int dwc3_gadget_start(struct usb_gadget *g,
1449                 struct usb_gadget_driver *driver)
1450 {
1451         struct dwc3             *dwc = gadget_to_dwc(g);
1452         struct dwc3_ep          *dep;
1453         unsigned long           flags;
1454         int                     ret = 0;
1455         u32                     reg;
1456
1457         spin_lock_irqsave(&dwc->lock, flags);
1458
1459         if (dwc->gadget_driver) {
1460                 dev_err(dwc->dev, "%s is already bound to %s\n",
1461                                 dwc->gadget.name,
1462                                 dwc->gadget_driver->function);
1463                 ret = -EBUSY;
1464                 goto err1;
1465         }
1466
1467         dwc->gadget_driver      = driver;
1468
1469         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1470         reg &= ~(DWC3_DCFG_SPEED_MASK);
1471
1472         /**
1473          * WORKAROUND: DWC3 revision < 2.20a have an issue
1474          * which would cause metastability state on Run/Stop
1475          * bit if we try to force the IP to USB2-only mode.
1476          *
1477          * Because of that, we cannot configure the IP to any
1478          * speed other than the SuperSpeed
1479          *
1480          * Refers to:
1481          *
1482          * STAR#9000525659: Clock Domain Crossing on DCTL in
1483          * USB 2.0 Mode
1484          */
1485         if (dwc->revision < DWC3_REVISION_220A) {
1486                 reg |= DWC3_DCFG_SUPERSPEED;
1487         } else {
1488                 switch (dwc->maximum_speed) {
1489                 case USB_SPEED_LOW:
1490                         reg |= DWC3_DSTS_LOWSPEED;
1491                         break;
1492                 case USB_SPEED_FULL:
1493                         reg |= DWC3_DSTS_FULLSPEED1;
1494                         break;
1495                 case USB_SPEED_HIGH:
1496                         reg |= DWC3_DSTS_HIGHSPEED;
1497                         break;
1498                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1499                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1500                 default:
1501                         reg |= DWC3_DSTS_SUPERSPEED;
1502                 }
1503         }
1504         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1505
1506         dwc->start_config_issued = false;
1507
1508         /* Start with SuperSpeed Default */
1509         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1510
1511         dep = dwc->eps[0];
1512         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1513                         false);
1514         if (ret) {
1515                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1516                 goto err2;
1517         }
1518
1519         dep = dwc->eps[1];
1520         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1521                         false);
1522         if (ret) {
1523                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1524                 goto err3;
1525         }
1526
1527         /* begin to receive SETUP packets */
1528         dwc->ep0state = EP0_SETUP_PHASE;
1529         dwc3_ep0_out_start(dwc);
1530
1531         dwc3_gadget_enable_irq(dwc);
1532
1533         spin_unlock_irqrestore(&dwc->lock, flags);
1534
1535         return 0;
1536
1537 err3:
1538         __dwc3_gadget_ep_disable(dwc->eps[0]);
1539
1540 err2:
1541         dwc->gadget_driver = NULL;
1542
1543 err1:
1544         spin_unlock_irqrestore(&dwc->lock, flags);
1545
1546         return ret;
1547 }
1548
1549 static int dwc3_gadget_stop(struct usb_gadget *g)
1550 {
1551         struct dwc3             *dwc = gadget_to_dwc(g);
1552         unsigned long           flags;
1553
1554         spin_lock_irqsave(&dwc->lock, flags);
1555
1556         dwc3_gadget_disable_irq(dwc);
1557         __dwc3_gadget_ep_disable(dwc->eps[0]);
1558         __dwc3_gadget_ep_disable(dwc->eps[1]);
1559
1560         dwc->gadget_driver      = NULL;
1561
1562         spin_unlock_irqrestore(&dwc->lock, flags);
1563
1564         return 0;
1565 }
1566
1567 static const struct usb_gadget_ops dwc3_gadget_ops = {
1568         .get_frame              = dwc3_gadget_get_frame,
1569         .wakeup                 = dwc3_gadget_wakeup,
1570         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1571         .pullup                 = dwc3_gadget_pullup,
1572         .udc_start              = dwc3_gadget_start,
1573         .udc_stop               = dwc3_gadget_stop,
1574 };
1575
1576 /* -------------------------------------------------------------------------- */
1577
1578 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1579                 u8 num, u32 direction)
1580 {
1581         struct dwc3_ep                  *dep;
1582         u8                              i;
1583
1584         for (i = 0; i < num; i++) {
1585                 u8 epnum = (i << 1) | (!!direction);
1586
1587                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1588                 if (!dep)
1589                         return -ENOMEM;
1590
1591                 dep->dwc = dwc;
1592                 dep->number = epnum;
1593                 dep->direction = !!direction;
1594                 dwc->eps[epnum] = dep;
1595
1596                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1597                                 (epnum & 1) ? "in" : "out");
1598
1599                 dep->endpoint.name = dep->name;
1600
1601                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1602
1603                 if (epnum == 0 || epnum == 1) {
1604                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1605                         dep->endpoint.maxburst = 1;
1606                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1607                         if (!epnum)
1608                                 dwc->gadget.ep0 = &dep->endpoint;
1609                 } else {
1610                         int             ret;
1611
1612                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1613                         dep->endpoint.max_streams = 15;
1614                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1615                         list_add_tail(&dep->endpoint.ep_list,
1616                                         &dwc->gadget.ep_list);
1617
1618                         ret = dwc3_alloc_trb_pool(dep);
1619                         if (ret)
1620                                 return ret;
1621                 }
1622
1623                 INIT_LIST_HEAD(&dep->request_list);
1624                 INIT_LIST_HEAD(&dep->req_queued);
1625         }
1626
1627         return 0;
1628 }
1629
1630 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1631 {
1632         int                             ret;
1633
1634         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1635
1636         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1637         if (ret < 0) {
1638                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1639                 return ret;
1640         }
1641
1642         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1643         if (ret < 0) {
1644                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1645                 return ret;
1646         }
1647
1648         return 0;
1649 }
1650
1651 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1652 {
1653         struct dwc3_ep                  *dep;
1654         u8                              epnum;
1655
1656         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1657                 dep = dwc->eps[epnum];
1658                 if (!dep)
1659                         continue;
1660                 /*
1661                  * Physical endpoints 0 and 1 are special; they form the
1662                  * bi-directional USB endpoint 0.
1663                  *
1664                  * For those two physical endpoints, we don't allocate a TRB
1665                  * pool nor do we add them the endpoints list. Due to that, we
1666                  * shouldn't do these two operations otherwise we would end up
1667                  * with all sorts of bugs when removing dwc3.ko.
1668                  */
1669                 if (epnum != 0 && epnum != 1) {
1670                         dwc3_free_trb_pool(dep);
1671                         list_del(&dep->endpoint.ep_list);
1672                 }
1673
1674                 kfree(dep);
1675         }
1676 }
1677
1678 /* -------------------------------------------------------------------------- */
1679
1680 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1681                 struct dwc3_request *req, struct dwc3_trb *trb,
1682                 const struct dwc3_event_depevt *event, int status)
1683 {
1684         unsigned int            count;
1685         unsigned int            s_pkt = 0;
1686         unsigned int            trb_status;
1687
1688         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1689                 /*
1690                  * We continue despite the error. There is not much we
1691                  * can do. If we don't clean it up we loop forever. If
1692                  * we skip the TRB then it gets overwritten after a
1693                  * while since we use them in a ring buffer. A BUG()
1694                  * would help. Lets hope that if this occurs, someone
1695                  * fixes the root cause instead of looking away :)
1696                  */
1697                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1698                                 dep->name, trb);
1699         count = trb->size & DWC3_TRB_SIZE_MASK;
1700
1701         if (dep->direction) {
1702                 if (count) {
1703                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1704                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1705                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1706                                                 dep->name);
1707                                 /*
1708                                  * If missed isoc occurred and there is
1709                                  * no request queued then issue END
1710                                  * TRANSFER, so that core generates
1711                                  * next xfernotready and we will issue
1712                                  * a fresh START TRANSFER.
1713                                  * If there are still queued request
1714                                  * then wait, do not issue either END
1715                                  * or UPDATE TRANSFER, just attach next
1716                                  * request in request_list during
1717                                  * giveback.If any future queued request
1718                                  * is successfully transferred then we
1719                                  * will issue UPDATE TRANSFER for all
1720                                  * request in the request_list.
1721                                  */
1722                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1723                         } else {
1724                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1725                                                 dep->name);
1726                                 status = -ECONNRESET;
1727                         }
1728                 } else {
1729                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1730                 }
1731         } else {
1732                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1733                         s_pkt = 1;
1734         }
1735
1736         /*
1737          * We assume here we will always receive the entire data block
1738          * which we should receive. Meaning, if we program RX to
1739          * receive 4K but we receive only 2K, we assume that's all we
1740          * should receive and we simply bounce the request back to the
1741          * gadget driver for further processing.
1742          */
1743         req->request.actual += req->request.length - count;
1744         if (s_pkt)
1745                 return 1;
1746         if ((event->status & DEPEVT_STATUS_LST) &&
1747                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1748                                 DWC3_TRB_CTRL_HWO)))
1749                 return 1;
1750         if ((event->status & DEPEVT_STATUS_IOC) &&
1751                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1752                 return 1;
1753         return 0;
1754 }
1755
1756 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1757                 const struct dwc3_event_depevt *event, int status)
1758 {
1759         struct dwc3_request     *req;
1760         struct dwc3_trb         *trb;
1761         unsigned int            slot;
1762
1763         req = next_request(&dep->req_queued);
1764         if (!req) {
1765                 WARN_ON_ONCE(1);
1766                 return 1;
1767         }
1768
1769         slot = req->start_slot;
1770         if ((slot == DWC3_TRB_NUM - 1) &&
1771             usb_endpoint_xfer_isoc(dep->endpoint.desc))
1772                 slot++;
1773         slot %= DWC3_TRB_NUM;
1774         trb = &dep->trb_pool[slot];
1775
1776         dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
1777         __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
1778         dwc3_gadget_giveback(dep, req, status);
1779
1780         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1781                         list_empty(&dep->req_queued)) {
1782                 if (list_empty(&dep->request_list)) {
1783                         /*
1784                          * If there is no entry in request list then do
1785                          * not issue END TRANSFER now. Just set PENDING
1786                          * flag, so that END TRANSFER is issued when an
1787                          * entry is added into request list.
1788                          */
1789                         dep->flags = DWC3_EP_PENDING_REQUEST;
1790                 } else {
1791                         dwc3_stop_active_transfer(dwc, dep->number, true);
1792                         dep->flags = DWC3_EP_ENABLED;
1793                 }
1794                 return 1;
1795         }
1796
1797         return 1;
1798 }
1799
1800 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1801                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1802 {
1803         unsigned                status = 0;
1804         int                     clean_busy;
1805
1806         if (event->status & DEPEVT_STATUS_BUSERR)
1807                 status = -ECONNRESET;
1808
1809         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1810         if (clean_busy)
1811                 dep->flags &= ~DWC3_EP_BUSY;
1812
1813         /*
1814          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1815          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1816          */
1817         if (dwc->revision < DWC3_REVISION_183A) {
1818                 u32             reg;
1819                 int             i;
1820
1821                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1822                         dep = dwc->eps[i];
1823
1824                         if (!(dep->flags & DWC3_EP_ENABLED))
1825                                 continue;
1826
1827                         if (!list_empty(&dep->req_queued))
1828                                 return;
1829                 }
1830
1831                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1832                 reg |= dwc->u1u2;
1833                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1834
1835                 dwc->u1u2 = 0;
1836         }
1837 }
1838
1839 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1840                 const struct dwc3_event_depevt *event)
1841 {
1842         struct dwc3_ep          *dep;
1843         u8                      epnum = event->endpoint_number;
1844
1845         dep = dwc->eps[epnum];
1846
1847         if (!(dep->flags & DWC3_EP_ENABLED))
1848                 return;
1849
1850         if (epnum == 0 || epnum == 1) {
1851                 dwc3_ep0_interrupt(dwc, event);
1852                 return;
1853         }
1854
1855         switch (event->endpoint_event) {
1856         case DWC3_DEPEVT_XFERCOMPLETE:
1857                 dep->resource_index = 0;
1858
1859                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1860                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1861                                         dep->name);
1862                         return;
1863                 }
1864
1865                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1866                 break;
1867         case DWC3_DEPEVT_XFERINPROGRESS:
1868                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1869                 break;
1870         case DWC3_DEPEVT_XFERNOTREADY:
1871                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1872                         dwc3_gadget_start_isoc(dwc, dep, event);
1873                 } else {
1874                         int ret;
1875
1876                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1877                                         dep->name, event->status &
1878                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1879                                         ? "Transfer Active"
1880                                         : "Transfer Not Active");
1881
1882                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1883                         if (!ret || ret == -EBUSY)
1884                                 return;
1885
1886                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1887                                         dep->name);
1888                 }
1889
1890                 break;
1891         case DWC3_DEPEVT_STREAMEVT:
1892                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1893                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1894                                         dep->name);
1895                         return;
1896                 }
1897
1898                 switch (event->status) {
1899                 case DEPEVT_STREAMEVT_FOUND:
1900                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1901                                         event->parameters);
1902
1903                         break;
1904                 case DEPEVT_STREAMEVT_NOTFOUND:
1905                         /* FALLTHROUGH */
1906                 default:
1907                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1908                 }
1909                 break;
1910         case DWC3_DEPEVT_RXTXFIFOEVT:
1911                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1912                 break;
1913         case DWC3_DEPEVT_EPCMDCMPLT:
1914                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1915                 break;
1916         }
1917 }
1918
1919 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1920 {
1921         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1922                 spin_unlock(&dwc->lock);
1923                 dwc->gadget_driver->disconnect(&dwc->gadget);
1924                 spin_lock(&dwc->lock);
1925         }
1926 }
1927
1928 static void dwc3_suspend_gadget(struct dwc3 *dwc)
1929 {
1930         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
1931                 spin_unlock(&dwc->lock);
1932                 dwc->gadget_driver->suspend(&dwc->gadget);
1933                 spin_lock(&dwc->lock);
1934         }
1935 }
1936
1937 static void dwc3_resume_gadget(struct dwc3 *dwc)
1938 {
1939         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
1940                 spin_unlock(&dwc->lock);
1941                 dwc->gadget_driver->resume(&dwc->gadget);
1942         }
1943 }
1944
1945 static void dwc3_reset_gadget(struct dwc3 *dwc)
1946 {
1947         if (!dwc->gadget_driver)
1948                 return;
1949
1950         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
1951                 spin_unlock(&dwc->lock);
1952                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
1953                 spin_lock(&dwc->lock);
1954         }
1955 }
1956
1957 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
1958 {
1959         struct dwc3_ep *dep;
1960         struct dwc3_gadget_ep_cmd_params params;
1961         u32 cmd;
1962         int ret;
1963
1964         dep = dwc->eps[epnum];
1965
1966         if (!dep->resource_index)
1967                 return;
1968
1969         /*
1970          * NOTICE: We are violating what the Databook says about the
1971          * EndTransfer command. Ideally we would _always_ wait for the
1972          * EndTransfer Command Completion IRQ, but that's causing too
1973          * much trouble synchronizing between us and gadget driver.
1974          *
1975          * We have discussed this with the IP Provider and it was
1976          * suggested to giveback all requests here, but give HW some
1977          * extra time to synchronize with the interconnect. We're using
1978          * an arbitraty 100us delay for that.
1979          *
1980          * Note also that a similar handling was tested by Synopsys
1981          * (thanks a lot Paul) and nothing bad has come out of it.
1982          * In short, what we're doing is:
1983          *
1984          * - Issue EndTransfer WITH CMDIOC bit set
1985          * - Wait 100us
1986          */
1987
1988         cmd = DWC3_DEPCMD_ENDTRANSFER;
1989         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1990         cmd |= DWC3_DEPCMD_CMDIOC;
1991         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1992         memset(&params, 0, sizeof(params));
1993         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1994         WARN_ON_ONCE(ret);
1995         dep->resource_index = 0;
1996         dep->flags &= ~DWC3_EP_BUSY;
1997         udelay(100);
1998 }
1999
2000 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2001 {
2002         u32 epnum;
2003
2004         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2005                 struct dwc3_ep *dep;
2006
2007                 dep = dwc->eps[epnum];
2008                 if (!dep)
2009                         continue;
2010
2011                 if (!(dep->flags & DWC3_EP_ENABLED))
2012                         continue;
2013
2014                 dwc3_remove_requests(dwc, dep);
2015         }
2016 }
2017
2018 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2019 {
2020         u32 epnum;
2021
2022         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2023                 struct dwc3_ep *dep;
2024                 struct dwc3_gadget_ep_cmd_params params;
2025                 int ret;
2026
2027                 dep = dwc->eps[epnum];
2028                 if (!dep)
2029                         continue;
2030
2031                 if (!(dep->flags & DWC3_EP_STALL))
2032                         continue;
2033
2034                 dep->flags &= ~DWC3_EP_STALL;
2035
2036                 memset(&params, 0, sizeof(params));
2037                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2038                                 DWC3_DEPCMD_CLEARSTALL, &params);
2039                 WARN_ON_ONCE(ret);
2040         }
2041 }
2042
2043 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2044 {
2045         int                     reg;
2046
2047         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2048         reg &= ~DWC3_DCTL_INITU1ENA;
2049         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2050
2051         reg &= ~DWC3_DCTL_INITU2ENA;
2052         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2053
2054         dwc3_disconnect_gadget(dwc);
2055         dwc->start_config_issued = false;
2056
2057         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2058         dwc->setup_packet_pending = false;
2059         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2060 }
2061
2062 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2063 {
2064         u32                     reg;
2065
2066         /*
2067          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2068          * would cause a missing Disconnect Event if there's a
2069          * pending Setup Packet in the FIFO.
2070          *
2071          * There's no suggested workaround on the official Bug
2072          * report, which states that "unless the driver/application
2073          * is doing any special handling of a disconnect event,
2074          * there is no functional issue".
2075          *
2076          * Unfortunately, it turns out that we _do_ some special
2077          * handling of a disconnect event, namely complete all
2078          * pending transfers, notify gadget driver of the
2079          * disconnection, and so on.
2080          *
2081          * Our suggested workaround is to follow the Disconnect
2082          * Event steps here, instead, based on a setup_packet_pending
2083          * flag. Such flag gets set whenever we have a XferNotReady
2084          * event on EP0 and gets cleared on XferComplete for the
2085          * same endpoint.
2086          *
2087          * Refers to:
2088          *
2089          * STAR#9000466709: RTL: Device : Disconnect event not
2090          * generated if setup packet pending in FIFO
2091          */
2092         if (dwc->revision < DWC3_REVISION_188A) {
2093                 if (dwc->setup_packet_pending)
2094                         dwc3_gadget_disconnect_interrupt(dwc);
2095         }
2096
2097         dwc3_reset_gadget(dwc);
2098
2099         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2100         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2101         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2102         dwc->test_mode = false;
2103
2104         dwc3_stop_active_transfers(dwc);
2105         dwc3_clear_stall_all_ep(dwc);
2106         dwc->start_config_issued = false;
2107
2108         /* Reset device address to zero */
2109         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2110         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2111         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2112 }
2113
2114 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2115 {
2116         u32 reg;
2117         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2118
2119         /*
2120          * We change the clock only at SS but I dunno why I would want to do
2121          * this. Maybe it becomes part of the power saving plan.
2122          */
2123
2124         if (speed != DWC3_DSTS_SUPERSPEED)
2125                 return;
2126
2127         /*
2128          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2129          * each time on Connect Done.
2130          */
2131         if (!usb30_clock)
2132                 return;
2133
2134         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2135         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2136         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2137 }
2138
2139 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2140 {
2141         struct dwc3_ep          *dep;
2142         int                     ret;
2143         u32                     reg;
2144         u8                      speed;
2145
2146         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2147         speed = reg & DWC3_DSTS_CONNECTSPD;
2148         dwc->speed = speed;
2149
2150         dwc3_update_ram_clk_sel(dwc, speed);
2151
2152         switch (speed) {
2153         case DWC3_DCFG_SUPERSPEED:
2154                 /*
2155                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2156                  * would cause a missing USB3 Reset event.
2157                  *
2158                  * In such situations, we should force a USB3 Reset
2159                  * event by calling our dwc3_gadget_reset_interrupt()
2160                  * routine.
2161                  *
2162                  * Refers to:
2163                  *
2164                  * STAR#9000483510: RTL: SS : USB3 reset event may
2165                  * not be generated always when the link enters poll
2166                  */
2167                 if (dwc->revision < DWC3_REVISION_190A)
2168                         dwc3_gadget_reset_interrupt(dwc);
2169
2170                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2171                 dwc->gadget.ep0->maxpacket = 512;
2172                 dwc->gadget.speed = USB_SPEED_SUPER;
2173                 break;
2174         case DWC3_DCFG_HIGHSPEED:
2175                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2176                 dwc->gadget.ep0->maxpacket = 64;
2177                 dwc->gadget.speed = USB_SPEED_HIGH;
2178                 break;
2179         case DWC3_DCFG_FULLSPEED2:
2180         case DWC3_DCFG_FULLSPEED1:
2181                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2182                 dwc->gadget.ep0->maxpacket = 64;
2183                 dwc->gadget.speed = USB_SPEED_FULL;
2184                 break;
2185         case DWC3_DCFG_LOWSPEED:
2186                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2187                 dwc->gadget.ep0->maxpacket = 8;
2188                 dwc->gadget.speed = USB_SPEED_LOW;
2189                 break;
2190         }
2191
2192         /* Enable USB2 LPM Capability */
2193
2194         if ((dwc->revision > DWC3_REVISION_194A)
2195                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2196                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2197                 reg |= DWC3_DCFG_LPM_CAP;
2198                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2199
2200                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2201                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2202
2203                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2204
2205                 /*
2206                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2207                  * DCFG.LPMCap is set, core responses with an ACK and the
2208                  * BESL value in the LPM token is less than or equal to LPM
2209                  * NYET threshold.
2210                  */
2211                 if (dwc->revision < DWC3_REVISION_240A  && dwc->has_lpm_erratum)
2212                         WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2213
2214                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2215                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2216
2217                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2218         } else {
2219                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2220                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2221                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2222         }
2223
2224         dep = dwc->eps[0];
2225         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2226                         false);
2227         if (ret) {
2228                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2229                 return;
2230         }
2231
2232         dep = dwc->eps[1];
2233         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2234                         false);
2235         if (ret) {
2236                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2237                 return;
2238         }
2239
2240         /*
2241          * Configure PHY via GUSB3PIPECTLn if required.
2242          *
2243          * Update GTXFIFOSIZn
2244          *
2245          * In both cases reset values should be sufficient.
2246          */
2247 }
2248
2249 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2250 {
2251         /*
2252          * TODO take core out of low power mode when that's
2253          * implemented.
2254          */
2255
2256         dwc->gadget_driver->resume(&dwc->gadget);
2257 }
2258
2259 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2260                 unsigned int evtinfo)
2261 {
2262         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2263         unsigned int            pwropt;
2264
2265         /*
2266          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2267          * Hibernation mode enabled which would show up when device detects
2268          * host-initiated U3 exit.
2269          *
2270          * In that case, device will generate a Link State Change Interrupt
2271          * from U3 to RESUME which is only necessary if Hibernation is
2272          * configured in.
2273          *
2274          * There are no functional changes due to such spurious event and we
2275          * just need to ignore it.
2276          *
2277          * Refers to:
2278          *
2279          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2280          * operational mode
2281          */
2282         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2283         if ((dwc->revision < DWC3_REVISION_250A) &&
2284                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2285                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2286                                 (next == DWC3_LINK_STATE_RESUME)) {
2287                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2288                         return;
2289                 }
2290         }
2291
2292         /*
2293          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2294          * on the link partner, the USB session might do multiple entry/exit
2295          * of low power states before a transfer takes place.
2296          *
2297          * Due to this problem, we might experience lower throughput. The
2298          * suggested workaround is to disable DCTL[12:9] bits if we're
2299          * transitioning from U1/U2 to U0 and enable those bits again
2300          * after a transfer completes and there are no pending transfers
2301          * on any of the enabled endpoints.
2302          *
2303          * This is the first half of that workaround.
2304          *
2305          * Refers to:
2306          *
2307          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2308          * core send LGO_Ux entering U0
2309          */
2310         if (dwc->revision < DWC3_REVISION_183A) {
2311                 if (next == DWC3_LINK_STATE_U0) {
2312                         u32     u1u2;
2313                         u32     reg;
2314
2315                         switch (dwc->link_state) {
2316                         case DWC3_LINK_STATE_U1:
2317                         case DWC3_LINK_STATE_U2:
2318                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2319                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2320                                                 | DWC3_DCTL_ACCEPTU2ENA
2321                                                 | DWC3_DCTL_INITU1ENA
2322                                                 | DWC3_DCTL_ACCEPTU1ENA);
2323
2324                                 if (!dwc->u1u2)
2325                                         dwc->u1u2 = reg & u1u2;
2326
2327                                 reg &= ~u1u2;
2328
2329                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2330                                 break;
2331                         default:
2332                                 /* do nothing */
2333                                 break;
2334                         }
2335                 }
2336         }
2337
2338         switch (next) {
2339         case DWC3_LINK_STATE_U1:
2340                 if (dwc->speed == USB_SPEED_SUPER)
2341                         dwc3_suspend_gadget(dwc);
2342                 break;
2343         case DWC3_LINK_STATE_U2:
2344         case DWC3_LINK_STATE_U3:
2345                 dwc3_suspend_gadget(dwc);
2346                 break;
2347         case DWC3_LINK_STATE_RESUME:
2348                 dwc3_resume_gadget(dwc);
2349                 break;
2350         default:
2351                 /* do nothing */
2352                 break;
2353         }
2354
2355         dwc->link_state = next;
2356 }
2357
2358 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2359                 unsigned int evtinfo)
2360 {
2361         unsigned int is_ss = evtinfo & (1UL << 4);
2362
2363         /**
2364          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2365          * have a known issue which can cause USB CV TD.9.23 to fail
2366          * randomly.
2367          *
2368          * Because of this issue, core could generate bogus hibernation
2369          * events which SW needs to ignore.
2370          *
2371          * Refers to:
2372          *
2373          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2374          * Device Fallback from SuperSpeed
2375          */
2376         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2377                 return;
2378
2379         /* enter hibernation here */
2380 }
2381
2382 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2383                 const struct dwc3_event_devt *event)
2384 {
2385         switch (event->type) {
2386         case DWC3_DEVICE_EVENT_DISCONNECT:
2387                 dwc3_gadget_disconnect_interrupt(dwc);
2388                 break;
2389         case DWC3_DEVICE_EVENT_RESET:
2390                 dwc3_gadget_reset_interrupt(dwc);
2391                 break;
2392         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2393                 dwc3_gadget_conndone_interrupt(dwc);
2394                 break;
2395         case DWC3_DEVICE_EVENT_WAKEUP:
2396                 dwc3_gadget_wakeup_interrupt(dwc);
2397                 break;
2398         case DWC3_DEVICE_EVENT_HIBER_REQ:
2399                 if (!dwc->has_hibernation) {
2400                         WARN(1 ,"unexpected hibernation event\n");
2401                         break;
2402                 }
2403                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2404                 break;
2405         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2406                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2407                 break;
2408         case DWC3_DEVICE_EVENT_EOPF:
2409                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2410                 break;
2411         case DWC3_DEVICE_EVENT_SOF:
2412                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2413                 break;
2414         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2415                 dev_vdbg(dwc->dev, "Erratic Error\n");
2416                 break;
2417         case DWC3_DEVICE_EVENT_CMD_CMPL:
2418                 dev_vdbg(dwc->dev, "Command Complete\n");
2419                 break;
2420         case DWC3_DEVICE_EVENT_OVERFLOW:
2421                 dev_vdbg(dwc->dev, "Overflow\n");
2422                 break;
2423         default:
2424                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2425         }
2426 }
2427
2428 static void dwc3_process_event_entry(struct dwc3 *dwc,
2429                 const union dwc3_event *event)
2430 {
2431         /* Endpoint IRQ, handle it and return early */
2432         if (event->type.is_devspec == 0) {
2433                 /* depevt */
2434                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2435         }
2436
2437         switch (event->type.type) {
2438         case DWC3_EVENT_TYPE_DEV:
2439                 dwc3_gadget_interrupt(dwc, &event->devt);
2440                 break;
2441         /* REVISIT what to do with Carkit and I2C events ? */
2442         default:
2443                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2444         }
2445 }
2446
2447 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2448 {
2449         struct dwc3_event_buffer *evt;
2450         irqreturn_t ret = IRQ_NONE;
2451         int left;
2452         u32 reg;
2453
2454         evt = dwc->ev_buffs[buf];
2455         left = evt->count;
2456
2457         if (!(evt->flags & DWC3_EVENT_PENDING))
2458                 return IRQ_NONE;
2459
2460         while (left > 0) {
2461                 union dwc3_event event;
2462
2463                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2464
2465                 dwc3_process_event_entry(dwc, &event);
2466
2467                 /*
2468                  * FIXME we wrap around correctly to the next entry as
2469                  * almost all entries are 4 bytes in size. There is one
2470                  * entry which has 12 bytes which is a regular entry
2471                  * followed by 8 bytes data. ATM I don't know how
2472                  * things are organized if we get next to the a
2473                  * boundary so I worry about that once we try to handle
2474                  * that.
2475                  */
2476                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2477                 left -= 4;
2478
2479                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2480         }
2481
2482         evt->count = 0;
2483         evt->flags &= ~DWC3_EVENT_PENDING;
2484         ret = IRQ_HANDLED;
2485
2486         /* Unmask interrupt */
2487         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2488         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2489         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2490
2491         return ret;
2492 }
2493
2494 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2495 {
2496         struct dwc3 *dwc = _dwc;
2497         unsigned long flags;
2498         irqreturn_t ret = IRQ_NONE;
2499         int i;
2500
2501         spin_lock_irqsave(&dwc->lock, flags);
2502
2503         for (i = 0; i < dwc->num_event_buffers; i++)
2504                 ret |= dwc3_process_event_buf(dwc, i);
2505
2506         spin_unlock_irqrestore(&dwc->lock, flags);
2507
2508         return ret;
2509 }
2510
2511 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2512 {
2513         struct dwc3_event_buffer *evt;
2514         u32 count;
2515         u32 reg;
2516
2517         evt = dwc->ev_buffs[buf];
2518
2519         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2520         count &= DWC3_GEVNTCOUNT_MASK;
2521         if (!count)
2522                 return IRQ_NONE;
2523
2524         evt->count = count;
2525         evt->flags |= DWC3_EVENT_PENDING;
2526
2527         /* Mask interrupt */
2528         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2529         reg |= DWC3_GEVNTSIZ_INTMASK;
2530         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2531
2532         return IRQ_WAKE_THREAD;
2533 }
2534
2535 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2536 {
2537         struct dwc3                     *dwc = _dwc;
2538         int                             i;
2539         irqreturn_t                     ret = IRQ_NONE;
2540
2541         spin_lock(&dwc->lock);
2542
2543         for (i = 0; i < dwc->num_event_buffers; i++) {
2544                 irqreturn_t status;
2545
2546                 status = dwc3_check_event_buf(dwc, i);
2547                 if (status == IRQ_WAKE_THREAD)
2548                         ret = status;
2549         }
2550
2551         spin_unlock(&dwc->lock);
2552
2553         return ret;
2554 }
2555
2556 /**
2557  * dwc3_gadget_init - Initializes gadget related registers
2558  * @dwc: pointer to our controller context structure
2559  *
2560  * Returns 0 on success otherwise negative errno.
2561  */
2562 int dwc3_gadget_init(struct dwc3 *dwc)
2563 {
2564         int                                     ret;
2565
2566         dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2567                                         (unsigned long *)&dwc->ctrl_req_addr);
2568         if (!dwc->ctrl_req) {
2569                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2570                 ret = -ENOMEM;
2571                 goto err0;
2572         }
2573
2574         dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
2575                                           (unsigned long *)&dwc->ep0_trb_addr);
2576         if (!dwc->ep0_trb) {
2577                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2578                 ret = -ENOMEM;
2579                 goto err1;
2580         }
2581
2582         dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2583                                   DWC3_EP0_BOUNCE_SIZE);
2584         if (!dwc->setup_buf) {
2585                 ret = -ENOMEM;
2586                 goto err2;
2587         }
2588
2589         dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2590                                         (unsigned long *)&dwc->ep0_bounce_addr);
2591         if (!dwc->ep0_bounce) {
2592                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2593                 ret = -ENOMEM;
2594                 goto err3;
2595         }
2596
2597         dwc->gadget.ops                 = &dwc3_gadget_ops;
2598         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2599         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2600         dwc->gadget.name                = "dwc3-gadget";
2601
2602         /*
2603          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2604          * on ep out.
2605          */
2606         dwc->gadget.quirk_ep_out_aligned_size = true;
2607
2608         /*
2609          * REVISIT: Here we should clear all pending IRQs to be
2610          * sure we're starting from a well known location.
2611          */
2612
2613         ret = dwc3_gadget_init_endpoints(dwc);
2614         if (ret)
2615                 goto err4;
2616
2617         ret = usb_add_gadget_udc((struct device *)dwc->dev, &dwc->gadget);
2618         if (ret) {
2619                 dev_err(dwc->dev, "failed to register udc\n");
2620                 goto err4;
2621         }
2622
2623         return 0;
2624
2625 err4:
2626         dwc3_gadget_free_endpoints(dwc);
2627         dma_free_coherent(dwc->ep0_bounce);
2628
2629 err3:
2630         kfree(dwc->setup_buf);
2631
2632 err2:
2633         dma_free_coherent(dwc->ep0_trb);
2634
2635 err1:
2636         dma_free_coherent(dwc->ctrl_req);
2637
2638 err0:
2639         return ret;
2640 }
2641
2642 /* -------------------------------------------------------------------------- */
2643
2644 void dwc3_gadget_exit(struct dwc3 *dwc)
2645 {
2646         usb_del_gadget_udc(&dwc->gadget);
2647
2648         dwc3_gadget_free_endpoints(dwc);
2649
2650         dma_free_coherent(dwc->ep0_bounce);
2651
2652         kfree(dwc->setup_buf);
2653
2654         dma_free_coherent(dwc->ep0_trb);
2655
2656         dma_free_coherent(dwc->ctrl_req);
2657 }
2658
2659 /**
2660  * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2661  * @dwc: struct dwce *
2662  *
2663  * Handles ep0 and gadget interrupt
2664  *
2665  * Should be called from dwc3 core.
2666  */
2667 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2668 {
2669         int ret = dwc3_interrupt(0, dwc);
2670
2671         if (ret == IRQ_WAKE_THREAD) {
2672                 int i;
2673                 struct dwc3_event_buffer *evt;
2674
2675                 dwc3_thread_interrupt(0, dwc);
2676
2677                 /* Clean + Invalidate the buffers after touching them */
2678                 for (i = 0; i < dwc->num_event_buffers; i++) {
2679                         evt = dwc->ev_buffs[i];
2680                         dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
2681                 }
2682         }
2683 }