drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11  * to uboot.
  12  *
  13  * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14  */
  15
  16 #include <common.h>
  17 #include <cpu_func.h>
  18 #include <malloc.h>
  19 #include <dwc3-uboot.h>
  20 #include <dm/device_compat.h>
  21 #include <dm/devres.h>
  22 #include <linux/bug.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/ioport.h>
  26 #include <dm.h>
  27 #include <generic-phy.h>
  28 #include <linux/usb/ch9.h>
  29 #include <linux/usb/gadget.h>
  30
  31 #include "core.h"
  32 #include "gadget.h"
  33 #include "io.h"
  34
  35 #include "linux-compat.h"
  36
  37 static LIST_HEAD(dwc3_list);
  38 /* -------------------------------------------------------------------------- */
  39
  40 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  41 {
  42         u32 reg;
  43
  44         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  45         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  46         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  47         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  48 }
  49
  50 /**
  51  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  52  * @dwc: pointer to our context structure
  53  */
  54 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  55 {
  56         u32             reg;
  57
  58         /* Before Resetting PHY, put Core in Reset */
  59         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  60         reg |= DWC3_GCTL_CORESOFTRESET;
  61         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  62
  63         /* Assert USB3 PHY reset */
  64         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  65         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  66         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  67
  68         /* Assert USB2 PHY reset */
  69         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  70         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  71         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  72
  73         mdelay(100);
  74
  75         /* Clear USB3 PHY reset */
  76         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  77         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  78         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  79
  80         /* Clear USB2 PHY reset */
  81         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  82         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  83         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  84
  85         mdelay(100);
  86
  87         /* After PHYs are stable we can take Core out of reset state */
  88         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  89         reg &= ~DWC3_GCTL_CORESOFTRESET;
  90         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  91
  92         return 0;
  93 }
  94
  95 /**
  96  * dwc3_free_one_event_buffer - Frees one event buffer
  97  * @dwc: Pointer to our controller context structure
  98  * @evt: Pointer to event buffer to be freed
  99  */
 100 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 101                 struct dwc3_event_buffer *evt)
 102 {
 103         dma_free_coherent(evt->buf);
 104 }
 105
 106 /**
 107  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 108  * @dwc: Pointer to our controller context structure
 109  * @length: size of the event buffer
 110  *
 111  * Returns a pointer to the allocated event buffer structure on success
 112  * otherwise ERR_PTR(errno).
 113  */
 114 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 115                 unsigned length)
 116 {
 117         struct dwc3_event_buffer        *evt;
 118
 119         evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
 120                            GFP_KERNEL);
 121         if (!evt)
 122                 return ERR_PTR(-ENOMEM);
 123
 124         evt->dwc        = dwc;
 125         evt->length     = length;
 126         evt->buf        = dma_alloc_coherent(length,
 127                                              (unsigned long *)&evt->dma);
 128         if (!evt->buf)
 129                 return ERR_PTR(-ENOMEM);
 130
 131         dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
 132
 133         return evt;
 134 }
 135
 136 /**
 137  * dwc3_free_event_buffers - frees all allocated event buffers
 138  * @dwc: Pointer to our controller context structure
 139  */
 140 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 141 {
 142         struct dwc3_event_buffer        *evt;
 143         int i;
 144
 145         for (i = 0; i < dwc->num_event_buffers; i++) {
 146                 evt = dwc->ev_buffs[i];
 147                 if (evt)
 148                         dwc3_free_one_event_buffer(dwc, evt);
 149         }
 150 }
 151
 152 /**
 153  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 154  * @dwc: pointer to our controller context structure
 155  * @length: size of event buffer
 156  *
 157  * Returns 0 on success otherwise negative errno. In the error case, dwc
 158  * may contain some buffers allocated but not all which were requested.
 159  */
 160 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 161 {
 162         int                     num;
 163         int                     i;
 164
 165         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 166         dwc->num_event_buffers = num;
 167
 168         dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
 169                                  sizeof(*dwc->ev_buffs) * num);
 170         if (!dwc->ev_buffs)
 171                 return -ENOMEM;
 172
 173         for (i = 0; i < num; i++) {
 174                 struct dwc3_event_buffer        *evt;
 175
 176                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 177                 if (IS_ERR(evt)) {
 178                         dev_err(dwc->dev, "can't allocate event buffer\n");
 179                         return PTR_ERR(evt);
 180                 }
 181                 dwc->ev_buffs[i] = evt;
 182         }
 183
 184         return 0;
 185 }
 186
 187 /**
 188  * dwc3_event_buffers_setup - setup our allocated event buffers
 189  * @dwc: pointer to our controller context structure
 190  *
 191  * Returns 0 on success otherwise negative errno.
 192  */
 193 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 194 {
 195         struct dwc3_event_buffer        *evt;
 196         int                             n;
 197
 198         for (n = 0; n < dwc->num_event_buffers; n++) {
 199                 evt = dwc->ev_buffs[n];
 200                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 201                                 evt->buf, (unsigned long long) evt->dma,
 202                                 evt->length);
 203
 204                 evt->lpos = 0;
 205
 206                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 207                                 lower_32_bits(evt->dma));
 208                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 209                                 upper_32_bits(evt->dma));
 210                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 211                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 212                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 213         }
 214
 215         return 0;
 216 }
 217
 218 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 219 {
 220         struct dwc3_event_buffer        *evt;
 221         int                             n;
 222
 223         for (n = 0; n < dwc->num_event_buffers; n++) {
 224                 evt = dwc->ev_buffs[n];
 225
 226                 evt->lpos = 0;
 227
 228                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 229                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 230                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 231                                 | DWC3_GEVNTSIZ_SIZE(0));
 232                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 233         }
 234 }
 235
 236 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 237 {
 238         if (!dwc->has_hibernation)
 239                 return 0;
 240
 241         if (!dwc->nr_scratch)
 242                 return 0;
 243
 244         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 245                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 246         if (!dwc->scratchbuf)
 247                 return -ENOMEM;
 248
 249         return 0;
 250 }
 251
 252 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 253 {
 254         dma_addr_t scratch_addr;
 255         u32 param;
 256         int ret;
 257
 258         if (!dwc->has_hibernation)
 259                 return 0;
 260
 261         if (!dwc->nr_scratch)
 262                 return 0;
 263
 264         scratch_addr = dma_map_single(dwc->scratchbuf,
 265                                       dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 266                                       DMA_BIDIRECTIONAL);
 267         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 268                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 269                 ret = -EFAULT;
 270                 goto err0;
 271         }
 272
 273         dwc->scratch_addr = scratch_addr;
 274
 275         param = lower_32_bits(scratch_addr);
 276
 277         ret = dwc3_send_gadget_generic_command(dwc,
 278                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 279         if (ret < 0)
 280                 goto err1;
 281
 282         param = upper_32_bits(scratch_addr);
 283
 284         ret = dwc3_send_gadget_generic_command(dwc,
 285                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 286         if (ret < 0)
 287                 goto err1;
 288
 289         return 0;
 290
 291 err1:
 292         dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 293                          DMA_BIDIRECTIONAL);
 294
 295 err0:
 296         return ret;
 297 }
 298
 299 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 300 {
 301         if (!dwc->has_hibernation)
 302                 return;
 303
 304         if (!dwc->nr_scratch)
 305                 return;
 306
 307         dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
 308                          DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 309         kfree(dwc->scratchbuf);
 310 }
 311
 312 static void dwc3_core_num_eps(struct dwc3 *dwc)
 313 {
 314         struct dwc3_hwparams    *parms = &dwc->hwparams;
 315
 316         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 317         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 318
 319         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 320                         dwc->num_in_eps, dwc->num_out_eps);
 321 }
 322
 323 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 324 {
 325         struct dwc3_hwparams    *parms = &dwc->hwparams;
 326
 327         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 328         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 329         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 330         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 331         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 332         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 333         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 334         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 335         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 336 }
 337
 338 /**
 339  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 340  * @dwc: Pointer to our controller context structure
 341  */
 342 static void dwc3_phy_setup(struct dwc3 *dwc)
 343 {
 344         u32 reg;
 345
 346         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 347
 348         /*
 349          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 350          * to '0' during coreConsultant configuration. So default value
 351          * will be '0' when the core is reset. Application needs to set it
 352          * to '1' after the core initialization is completed.
 353          */
 354         if (dwc->revision > DWC3_REVISION_194A)
 355                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 356
 357         if (dwc->u2ss_inp3_quirk)
 358                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 359
 360         if (dwc->req_p1p2p3_quirk)
 361                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 362
 363         if (dwc->del_p1p2p3_quirk)
 364                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 365
 366         if (dwc->del_phy_power_chg_quirk)
 367                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 368
 369         if (dwc->lfps_filter_quirk)
 370                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 371
 372         if (dwc->rx_detect_poll_quirk)
 373                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 374
 375         if (dwc->tx_de_emphasis_quirk)
 376                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 377
 378         if (dwc->dis_u3_susphy_quirk)
 379                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 380
 381         if (dwc->dis_del_phy_power_chg_quirk)
 382                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 383
 384         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 385
 386         mdelay(100);
 387
 388         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 389
 390         /*
 391          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 392          * '0' during coreConsultant configuration. So default value will
 393          * be '0' when the core is reset. Application needs to set it to
 394          * '1' after the core initialization is completed.
 395          */
 396         if (dwc->revision > DWC3_REVISION_194A)
 397                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 398
 399         if (dwc->dis_u2_susphy_quirk)
 400                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 401
 402         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 403
 404         mdelay(100);
 405 }
 406
 407 /**
 408  * dwc3_core_init - Low-level initialization of DWC3 Core
 409  * @dwc: Pointer to our controller context structure
 410  *
 411  * Returns 0 on success otherwise negative errno.
 412  */
 413 static int dwc3_core_init(struct dwc3 *dwc)
 414 {
 415         unsigned long           timeout;
 416         u32                     hwparams4 = dwc->hwparams.hwparams4;
 417         u32                     reg;
 418         int                     ret;
 419
 420         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 421         /* This should read as U3 followed by revision number */
 422         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 423                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 424                 ret = -ENODEV;
 425                 goto err0;
 426         }
 427         dwc->revision = reg;
 428
 429         /* Handle USB2.0-only core configuration */
 430         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 431                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 432                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 433                         dwc->maximum_speed = USB_SPEED_HIGH;
 434         }
 435
 436         /* issue device SoftReset too */
 437         timeout = 5000;
 438         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 439         while (timeout--) {
 440                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 441                 if (!(reg & DWC3_DCTL_CSFTRST))
 442                         break;
 443         };
 444
 445         if (!timeout) {
 446                 dev_err(dwc->dev, "Reset Timed Out\n");
 447                 ret = -ETIMEDOUT;
 448                 goto err0;
 449         }
 450
 451         dwc3_phy_setup(dwc);
 452
 453         ret = dwc3_core_soft_reset(dwc);
 454         if (ret)
 455                 goto err0;
 456
 457         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 458         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 459
 460         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 461         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 462                 /**
 463                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 464                  * issue which would cause xHCI compliance tests to fail.
 465                  *
 466                  * Because of that we cannot enable clock gating on such
 467                  * configurations.
 468                  *
 469                  * Refers to:
 470                  *
 471                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 472                  * SOF/ITP Mode Used
 473                  */
 474                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 475                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 476                                 (dwc->revision >= DWC3_REVISION_210A &&
 477                                 dwc->revision <= DWC3_REVISION_250A))
 478                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 479                 else
 480                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 481                 break;
 482         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 483                 /* enable hibernation here */
 484                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 485
 486                 /*
 487                  * REVISIT Enabling this bit so that host-mode hibernation
 488                  * will work. Device-mode hibernation is not yet implemented.
 489                  */
 490                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 491                 break;
 492         default:
 493                 dev_dbg(dwc->dev, "No power optimization available\n");
 494         }
 495
 496         /* check if current dwc3 is on simulation board */
 497         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 498                 dev_dbg(dwc->dev, "it is on FPGA board\n");
 499                 dwc->is_fpga = true;
 500         }
 501
 502         if(dwc->disable_scramble_quirk && !dwc->is_fpga)
 503                 WARN(true,
 504                      "disable_scramble cannot be used on non-FPGA builds\n");
 505
 506         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 507                 reg |= DWC3_GCTL_DISSCRAMBLE;
 508         else
 509                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 510
 511         if (dwc->u2exit_lfps_quirk)
 512                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 513
 514         /*
 515          * WORKAROUND: DWC3 revisions <1.90a have a bug
 516          * where the device can fail to connect at SuperSpeed
 517          * and falls back to high-speed mode which causes
 518          * the device to enter a Connect/Disconnect loop
 519          */
 520         if (dwc->revision < DWC3_REVISION_190A)
 521                 reg |= DWC3_GCTL_U2RSTECN;
 522
 523         dwc3_core_num_eps(dwc);
 524
 525         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 526
 527         ret = dwc3_alloc_scratch_buffers(dwc);
 528         if (ret)
 529                 goto err0;
 530
 531         ret = dwc3_setup_scratch_buffers(dwc);
 532         if (ret)
 533                 goto err1;
 534
 535         return 0;
 536
 537 err1:
 538         dwc3_free_scratch_buffers(dwc);
 539
 540 err0:
 541         return ret;
 542 }
 543
 544 static void dwc3_core_exit(struct dwc3 *dwc)
 545 {
 546         dwc3_free_scratch_buffers(dwc);
 547 }
 548
 549 static int dwc3_core_init_mode(struct dwc3 *dwc)
 550 {
 551         int ret;
 552
 553         switch (dwc->dr_mode) {
 554         case USB_DR_MODE_PERIPHERAL:
 555                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 556                 ret = dwc3_gadget_init(dwc);
 557                 if (ret) {
 558                         dev_err(dev, "failed to initialize gadget\n");
 559                         return ret;
 560                 }
 561                 break;
 562         case USB_DR_MODE_HOST:
 563                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 564                 ret = dwc3_host_init(dwc);
 565                 if (ret) {
 566                         dev_err(dev, "failed to initialize host\n");
 567                         return ret;
 568                 }
 569                 break;
 570         case USB_DR_MODE_OTG:
 571                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 572                 ret = dwc3_host_init(dwc);
 573                 if (ret) {
 574                         dev_err(dev, "failed to initialize host\n");
 575                         return ret;
 576                 }
 577
 578                 ret = dwc3_gadget_init(dwc);
 579                 if (ret) {
 580                         dev_err(dev, "failed to initialize gadget\n");
 581                         return ret;
 582                 }
 583                 break;
 584         default:
 585                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 586                 return -EINVAL;
 587         }
 588
 589         return 0;
 590 }
 591
 592 static void dwc3_gadget_run(struct dwc3 *dwc)
 593 {
 594         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
 595         mdelay(100);
 596 }
 597
 598 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 599 {
 600         switch (dwc->dr_mode) {
 601         case USB_DR_MODE_PERIPHERAL:
 602                 dwc3_gadget_exit(dwc);
 603                 break;
 604         case USB_DR_MODE_HOST:
 605                 dwc3_host_exit(dwc);
 606                 break;
 607         case USB_DR_MODE_OTG:
 608                 dwc3_host_exit(dwc);
 609                 dwc3_gadget_exit(dwc);
 610                 break;
 611         default:
 612                 /* do nothing */
 613                 break;
 614         }
 615
 616         /*
 617          * switch back to peripheral mode
 618          * This enables the phy to enter idle and then, if enabled, suspend.
 619          */
 620         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 621         dwc3_gadget_run(dwc);
 622 }
 623
 624 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
 625                                   struct dwc3 *dwc)
 626 {
 627         enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
 628         u32 reg;
 629
 630         /* Set dwc3 usb2 phy config */
 631         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 632
 633         switch (hsphy_mode) {
 634         case USBPHY_INTERFACE_MODE_UTMI:
 635                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 636                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 637                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 638                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 639                 break;
 640         case USBPHY_INTERFACE_MODE_UTMIW:
 641                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 642                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 643                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 644                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 645                 break;
 646         default:
 647                 break;
 648         }
 649
 650         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 651 }
 652
 653 #define DWC3_ALIGN_MASK         (16 - 1)
 654
 655 /**
 656  * dwc3_uboot_init - dwc3 core uboot initialization code
 657  * @dwc3_dev: struct dwc3_device containing initialization data
 658  *
 659  * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
 660  * kernel driver). Pointer to dwc3_device should be passed containing
 661  * base address and other initialization data. Returns '0' on success and
 662  * a negative value on failure.
 663  *
 664  * Generally called from board_usb_init() implemented in board file.
 665  */
 666 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 667 {
 668         struct dwc3             *dwc;
 669         struct device           *dev = NULL;
 670         u8                      lpm_nyet_threshold;
 671         u8                      tx_de_emphasis;
 672         u8                      hird_threshold;
 673
 674         int                     ret;
 675
 676         void                    *mem;
 677
 678         mem = devm_kzalloc((struct udevice *)dev,
 679                            sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 680         if (!mem)
 681                 return -ENOMEM;
 682
 683         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 684         dwc->mem = mem;
 685
 686         dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
 687                                         DWC3_GLOBALS_REGS_START);
 688
 689         /* default to highest possible threshold */
 690         lpm_nyet_threshold = 0xff;
 691
 692         /* default to -3.5dB de-emphasis */
 693         tx_de_emphasis = 1;
 694
 695         /*
 696          * default to assert utmi_sleep_n and use maximum allowed HIRD
 697          * threshold value of 0b1100
 698          */
 699         hird_threshold = 12;
 700
 701         dwc->maximum_speed = dwc3_dev->maximum_speed;
 702         dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
 703         if (dwc3_dev->lpm_nyet_threshold)
 704                 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
 705         dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
 706         if (dwc3_dev->hird_threshold)
 707                 hird_threshold = dwc3_dev->hird_threshold;
 708
 709         dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
 710         dwc->dr_mode = dwc3_dev->dr_mode;
 711
 712         dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
 713         dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
 714         dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
 715         dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
 716         dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
 717         dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
 718         dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
 719         dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
 720         dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
 721         dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 722         dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
 723
 724         dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 725         if (dwc3_dev->tx_de_emphasis)
 726                 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
 727
 728         /* default to superspeed if no maximum_speed passed */
 729         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 730                 dwc->maximum_speed = USB_SPEED_SUPER;
 731
 732         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 733         dwc->tx_de_emphasis = tx_de_emphasis;
 734
 735         dwc->hird_threshold = hird_threshold
 736                 | (dwc->is_utmi_l1_suspend << 4);
 737
 738         dwc->index = dwc3_dev->index;
 739
 740         dwc3_cache_hwparams(dwc);
 741
 742         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 743         if (ret) {
 744                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 745                 return -ENOMEM;
 746         }
 747
 748         if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 749                 dwc->dr_mode = USB_DR_MODE_HOST;
 750         else if (!IS_ENABLED(CONFIG_USB_HOST))
 751                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 752
 753         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 754                 dwc->dr_mode = USB_DR_MODE_OTG;
 755
 756         ret = dwc3_core_init(dwc);
 757         if (ret) {
 758                 dev_err(dev, "failed to initialize core\n");
 759                 goto err0;
 760         }
 761
 762         dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
 763
 764         ret = dwc3_event_buffers_setup(dwc);
 765         if (ret) {
 766                 dev_err(dwc->dev, "failed to setup event buffers\n");
 767                 goto err1;
 768         }
 769
 770         ret = dwc3_core_init_mode(dwc);
 771         if (ret)
 772                 goto err2;
 773
 774         list_add_tail(&dwc->list, &dwc3_list);
 775
 776         return 0;
 777
 778 err2:
 779         dwc3_event_buffers_cleanup(dwc);
 780
 781 err1:
 782         dwc3_core_exit(dwc);
 783
 784 err0:
 785         dwc3_free_event_buffers(dwc);
 786
 787         return ret;
 788 }
 789
 790 /**
 791  * dwc3_uboot_exit - dwc3 core uboot cleanup code
 792  * @index: index of this controller
 793  *
 794  * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
 795  * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
 796  * should be passed and should match with the index passed in
 797  * dwc3_device during init.
 798  *
 799  * Generally called from board file.
 800  */
 801 void dwc3_uboot_exit(int index)
 802 {
 803         struct dwc3 *dwc;
 804
 805         list_for_each_entry(dwc, &dwc3_list, list) {
 806                 if (dwc->index != index)
 807                         continue;
 808
 809                 dwc3_core_exit_mode(dwc);
 810                 dwc3_event_buffers_cleanup(dwc);
 811                 dwc3_free_event_buffers(dwc);
 812                 dwc3_core_exit(dwc);
 813                 list_del(&dwc->list);
 814                 kfree(dwc->mem);
 815                 break;
 816         }
 817 }
 818
 819 /**
 820  * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
 821  * @index: index of this controller
 822  *
 823  * Invokes dwc3 gadget interrupts.
 824  *
 825  * Generally called from board file.
 826  */
 827 void dwc3_uboot_handle_interrupt(int index)
 828 {
 829         struct dwc3 *dwc = NULL;
 830
 831         list_for_each_entry(dwc, &dwc3_list, list) {
 832                 if (dwc->index != index)
 833                         continue;
 834
 835                 dwc3_gadget_uboot_handle_interrupt(dwc);
 836                 break;
 837         }
 838 }
 839
 840 MODULE_ALIAS("platform:dwc3");
 841 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 842 MODULE_LICENSE("GPL v2");
 843 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
 844
 845 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
 846 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
 847 {
 848         int ret;
 849
 850         ret = generic_phy_get_bulk(dev, phys);
 851         if (ret)
 852                 return ret;
 853
 854         ret = generic_phy_init_bulk(phys);
 855         if (ret)
 856                 return ret;
 857
 858         ret = generic_phy_power_on_bulk(phys);
 859         if (ret)
 860                 generic_phy_exit_bulk(phys);
 861
 862         return ret;
 863 }
 864
 865 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
 866 {
 867         int ret;
 868
 869         ret = generic_phy_power_off_bulk(phys);
 870         ret |= generic_phy_exit_bulk(phys);
 871         return ret;
 872 }
 873 #endif
 874
 875 #if CONFIG_IS_ENABLED(DM_USB)
 876 void dwc3_of_parse(struct dwc3 *dwc)
 877 {
 878         const u8 *tmp;
 879         struct udevice *dev = dwc->dev;
 880         u8 lpm_nyet_threshold;
 881         u8 tx_de_emphasis;
 882         u8 hird_threshold;
 883
 884         /* default to highest possible threshold */
 885         lpm_nyet_threshold = 0xff;
 886
 887         /* default to -3.5dB de-emphasis */
 888         tx_de_emphasis = 1;
 889
 890         /*
 891          * default to assert utmi_sleep_n and use maximum allowed HIRD
 892          * threshold value of 0b1100
 893          */
 894         hird_threshold = 12;
 895
 896         dwc->has_lpm_erratum = dev_read_bool(dev,
 897                                 "snps,has-lpm-erratum");
 898         tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
 899         if (tmp)
 900                 lpm_nyet_threshold = *tmp;
 901
 902         dwc->is_utmi_l1_suspend = dev_read_bool(dev,
 903                                 "snps,is-utmi-l1-suspend");
 904         tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
 905         if (tmp)
 906                 hird_threshold = *tmp;
 907
 908         dwc->disable_scramble_quirk = dev_read_bool(dev,
 909                                 "snps,disable_scramble_quirk");
 910         dwc->u2exit_lfps_quirk = dev_read_bool(dev,
 911                                 "snps,u2exit_lfps_quirk");
 912         dwc->u2ss_inp3_quirk = dev_read_bool(dev,
 913                                 "snps,u2ss_inp3_quirk");
 914         dwc->req_p1p2p3_quirk = dev_read_bool(dev,
 915                                 "snps,req_p1p2p3_quirk");
 916         dwc->del_p1p2p3_quirk = dev_read_bool(dev,
 917                                 "snps,del_p1p2p3_quirk");
 918         dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
 919                                 "snps,del_phy_power_chg_quirk");
 920         dwc->lfps_filter_quirk = dev_read_bool(dev,
 921                                 "snps,lfps_filter_quirk");
 922         dwc->rx_detect_poll_quirk = dev_read_bool(dev,
 923                                 "snps,rx_detect_poll_quirk");
 924         dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
 925                                 "snps,dis_u3_susphy_quirk");
 926         dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
 927                                 "snps,dis_u2_susphy_quirk");
 928         dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
 929                                 "snps,dis-del-phy-power-chg-quirk");
 930         dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
 931                                 "snps,tx_de_emphasis_quirk");
 932         tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
 933         if (tmp)
 934                 tx_de_emphasis = *tmp;
 935
 936         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 937         dwc->tx_de_emphasis = tx_de_emphasis;
 938
 939         dwc->hird_threshold = hird_threshold
 940                 | (dwc->is_utmi_l1_suspend << 4);
 941 }
 942
 943 int dwc3_init(struct dwc3 *dwc)
 944 {
 945         int ret;
 946
 947         dwc3_cache_hwparams(dwc);
 948
 949         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 950         if (ret) {
 951                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 952                 return -ENOMEM;
 953         }
 954
 955         ret = dwc3_core_init(dwc);
 956         if (ret) {
 957                 dev_err(dev, "failed to initialize core\n");
 958                 goto core_fail;
 959         }
 960
 961         ret = dwc3_event_buffers_setup(dwc);
 962         if (ret) {
 963                 dev_err(dwc->dev, "failed to setup event buffers\n");
 964                 goto event_fail;
 965         }
 966
 967         ret = dwc3_core_init_mode(dwc);
 968         if (ret)
 969                 goto mode_fail;
 970
 971         return 0;
 972
 973 mode_fail:
 974         dwc3_event_buffers_cleanup(dwc);
 975
 976 event_fail:
 977         dwc3_core_exit(dwc);
 978
 979 core_fail:
 980         dwc3_free_event_buffers(dwc);
 981
 982         return ret;
 983 }
 984
 985 void dwc3_remove(struct dwc3 *dwc)
 986 {
 987         dwc3_core_exit_mode(dwc);
 988         dwc3_event_buffers_cleanup(dwc);
 989         dwc3_free_event_buffers(dwc);
 990         dwc3_core_exit(dwc);
 991         kfree(dwc->mem);
 992 }
 993 #endif