drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11  * to uboot.
  12  *
  13  * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14  */
  15
  16 #include <common.h>
  17 #include <cpu_func.h>
  18 #include <malloc.h>
  19 #include <dwc3-uboot.h>
  20 #include <dm/device_compat.h>
  21 #include <dm/devres.h>
  22 #include <linux/bug.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/err.h>
  26 #include <linux/ioport.h>
  27 #include <dm.h>
  28 #include <generic-phy.h>
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31
  32 #include "core.h"
  33 #include "gadget.h"
  34 #include "io.h"
  35
  36 #include "linux-compat.h"
  37
  38 static LIST_HEAD(dwc3_list);
  39 /* -------------------------------------------------------------------------- */
  40
  41 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  42 {
  43         u32 reg;
  44
  45         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  46         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  47         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  48         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  49 }
  50
  51 /**
  52  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  53  * @dwc: pointer to our context structure
  54  */
  55 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  56 {
  57         u32             reg;
  58
  59         /* Before Resetting PHY, put Core in Reset */
  60         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  61         reg |= DWC3_GCTL_CORESOFTRESET;
  62         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  63
  64         /* Assert USB3 PHY reset */
  65         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  66         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  67         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  68
  69         /* Assert USB2 PHY reset */
  70         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  71         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  72         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  73
  74         mdelay(100);
  75
  76         /* Clear USB3 PHY reset */
  77         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  78         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  79         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  80
  81         /* Clear USB2 PHY reset */
  82         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  83         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  84         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  85
  86         mdelay(100);
  87
  88         /* After PHYs are stable we can take Core out of reset state */
  89         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  90         reg &= ~DWC3_GCTL_CORESOFTRESET;
  91         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  92
  93         return 0;
  94 }
  95
  96 /**
  97  * dwc3_free_one_event_buffer - Frees one event buffer
  98  * @dwc: Pointer to our controller context structure
  99  * @evt: Pointer to event buffer to be freed
 100  */
 101 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 102                 struct dwc3_event_buffer *evt)
 103 {
 104         dma_free_coherent(evt->buf);
 105 }
 106
 107 /**
 108  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 109  * @dwc: Pointer to our controller context structure
 110  * @length: size of the event buffer
 111  *
 112  * Returns a pointer to the allocated event buffer structure on success
 113  * otherwise ERR_PTR(errno).
 114  */
 115 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 116                 unsigned length)
 117 {
 118         struct dwc3_event_buffer        *evt;
 119
 120         evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
 121                            GFP_KERNEL);
 122         if (!evt)
 123                 return ERR_PTR(-ENOMEM);
 124
 125         evt->dwc        = dwc;
 126         evt->length     = length;
 127         evt->buf        = dma_alloc_coherent(length,
 128                                              (unsigned long *)&evt->dma);
 129         if (!evt->buf)
 130                 return ERR_PTR(-ENOMEM);
 131
 132         dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
 133
 134         return evt;
 135 }
 136
 137 /**
 138  * dwc3_free_event_buffers - frees all allocated event buffers
 139  * @dwc: Pointer to our controller context structure
 140  */
 141 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 142 {
 143         struct dwc3_event_buffer        *evt;
 144         int i;
 145
 146         for (i = 0; i < dwc->num_event_buffers; i++) {
 147                 evt = dwc->ev_buffs[i];
 148                 if (evt)
 149                         dwc3_free_one_event_buffer(dwc, evt);
 150         }
 151 }
 152
 153 /**
 154  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 155  * @dwc: pointer to our controller context structure
 156  * @length: size of event buffer
 157  *
 158  * Returns 0 on success otherwise negative errno. In the error case, dwc
 159  * may contain some buffers allocated but not all which were requested.
 160  */
 161 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 162 {
 163         int                     num;
 164         int                     i;
 165
 166         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 167         dwc->num_event_buffers = num;
 168
 169         dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
 170                                  sizeof(*dwc->ev_buffs) * num);
 171         if (!dwc->ev_buffs)
 172                 return -ENOMEM;
 173
 174         for (i = 0; i < num; i++) {
 175                 struct dwc3_event_buffer        *evt;
 176
 177                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 178                 if (IS_ERR(evt)) {
 179                         dev_err(dwc->dev, "can't allocate event buffer\n");
 180                         return PTR_ERR(evt);
 181                 }
 182                 dwc->ev_buffs[i] = evt;
 183         }
 184
 185         return 0;
 186 }
 187
 188 /**
 189  * dwc3_event_buffers_setup - setup our allocated event buffers
 190  * @dwc: pointer to our controller context structure
 191  *
 192  * Returns 0 on success otherwise negative errno.
 193  */
 194 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 195 {
 196         struct dwc3_event_buffer        *evt;
 197         int                             n;
 198
 199         for (n = 0; n < dwc->num_event_buffers; n++) {
 200                 evt = dwc->ev_buffs[n];
 201                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 202                                 evt->buf, (unsigned long long) evt->dma,
 203                                 evt->length);
 204
 205                 evt->lpos = 0;
 206
 207                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 208                                 lower_32_bits(evt->dma));
 209                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 210                                 upper_32_bits(evt->dma));
 211                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 212                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 213                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 214         }
 215
 216         return 0;
 217 }
 218
 219 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 220 {
 221         struct dwc3_event_buffer        *evt;
 222         int                             n;
 223
 224         for (n = 0; n < dwc->num_event_buffers; n++) {
 225                 evt = dwc->ev_buffs[n];
 226
 227                 evt->lpos = 0;
 228
 229                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 230                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 231                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 232                                 | DWC3_GEVNTSIZ_SIZE(0));
 233                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 234         }
 235 }
 236
 237 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 238 {
 239         if (!dwc->has_hibernation)
 240                 return 0;
 241
 242         if (!dwc->nr_scratch)
 243                 return 0;
 244
 245         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 246                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 247         if (!dwc->scratchbuf)
 248                 return -ENOMEM;
 249
 250         return 0;
 251 }
 252
 253 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 254 {
 255         dma_addr_t scratch_addr;
 256         u32 param;
 257         int ret;
 258
 259         if (!dwc->has_hibernation)
 260                 return 0;
 261
 262         if (!dwc->nr_scratch)
 263                 return 0;
 264
 265         scratch_addr = dma_map_single(dwc->scratchbuf,
 266                                       dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 267                                       DMA_BIDIRECTIONAL);
 268         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 269                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 270                 ret = -EFAULT;
 271                 goto err0;
 272         }
 273
 274         dwc->scratch_addr = scratch_addr;
 275
 276         param = lower_32_bits(scratch_addr);
 277
 278         ret = dwc3_send_gadget_generic_command(dwc,
 279                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 280         if (ret < 0)
 281                 goto err1;
 282
 283         param = upper_32_bits(scratch_addr);
 284
 285         ret = dwc3_send_gadget_generic_command(dwc,
 286                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 287         if (ret < 0)
 288                 goto err1;
 289
 290         return 0;
 291
 292 err1:
 293         dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 294                          DMA_BIDIRECTIONAL);
 295
 296 err0:
 297         return ret;
 298 }
 299
 300 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 301 {
 302         if (!dwc->has_hibernation)
 303                 return;
 304
 305         if (!dwc->nr_scratch)
 306                 return;
 307
 308         dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
 309                          DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 310         kfree(dwc->scratchbuf);
 311 }
 312
 313 static void dwc3_core_num_eps(struct dwc3 *dwc)
 314 {
 315         struct dwc3_hwparams    *parms = &dwc->hwparams;
 316
 317         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 318         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 319
 320         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 321                         dwc->num_in_eps, dwc->num_out_eps);
 322 }
 323
 324 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 325 {
 326         struct dwc3_hwparams    *parms = &dwc->hwparams;
 327
 328         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 329         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 330         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 331         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 332         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 333         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 334         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 335         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 336         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 337 }
 338
 339 /**
 340  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 341  * @dwc: Pointer to our controller context structure
 342  */
 343 static void dwc3_phy_setup(struct dwc3 *dwc)
 344 {
 345         u32 reg;
 346
 347         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 348
 349         /*
 350          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 351          * to '0' during coreConsultant configuration. So default value
 352          * will be '0' when the core is reset. Application needs to set it
 353          * to '1' after the core initialization is completed.
 354          */
 355         if (dwc->revision > DWC3_REVISION_194A)
 356                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 357
 358         if (dwc->u2ss_inp3_quirk)
 359                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 360
 361         if (dwc->req_p1p2p3_quirk)
 362                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 363
 364         if (dwc->del_p1p2p3_quirk)
 365                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 366
 367         if (dwc->del_phy_power_chg_quirk)
 368                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 369
 370         if (dwc->lfps_filter_quirk)
 371                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 372
 373         if (dwc->rx_detect_poll_quirk)
 374                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 375
 376         if (dwc->tx_de_emphasis_quirk)
 377                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 378
 379         if (dwc->dis_u3_susphy_quirk)
 380                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 381
 382         if (dwc->dis_del_phy_power_chg_quirk)
 383                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 384
 385         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 386
 387         mdelay(100);
 388
 389         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 390
 391         /*
 392          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 393          * '0' during coreConsultant configuration. So default value will
 394          * be '0' when the core is reset. Application needs to set it to
 395          * '1' after the core initialization is completed.
 396          */
 397         if (dwc->revision > DWC3_REVISION_194A)
 398                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 399
 400         if (dwc->dis_u2_susphy_quirk)
 401                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 402
 403         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 404
 405         mdelay(100);
 406 }
 407
 408 /**
 409  * dwc3_core_init - Low-level initialization of DWC3 Core
 410  * @dwc: Pointer to our controller context structure
 411  *
 412  * Returns 0 on success otherwise negative errno.
 413  */
 414 static int dwc3_core_init(struct dwc3 *dwc)
 415 {
 416         unsigned long           timeout;
 417         u32                     hwparams4 = dwc->hwparams.hwparams4;
 418         u32                     reg;
 419         int                     ret;
 420
 421         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 422         /* This should read as U3 followed by revision number */
 423         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 424                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 425                 ret = -ENODEV;
 426                 goto err0;
 427         }
 428         dwc->revision = reg;
 429
 430         /* Handle USB2.0-only core configuration */
 431         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 432                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 433                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 434                         dwc->maximum_speed = USB_SPEED_HIGH;
 435         }
 436
 437         /* issue device SoftReset too */
 438         timeout = 5000;
 439         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 440         while (timeout--) {
 441                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 442                 if (!(reg & DWC3_DCTL_CSFTRST))
 443                         break;
 444         };
 445
 446         if (!timeout) {
 447                 dev_err(dwc->dev, "Reset Timed Out\n");
 448                 ret = -ETIMEDOUT;
 449                 goto err0;
 450         }
 451
 452         dwc3_phy_setup(dwc);
 453
 454         ret = dwc3_core_soft_reset(dwc);
 455         if (ret)
 456                 goto err0;
 457
 458         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 459         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 460
 461         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 462         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 463                 /**
 464                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 465                  * issue which would cause xHCI compliance tests to fail.
 466                  *
 467                  * Because of that we cannot enable clock gating on such
 468                  * configurations.
 469                  *
 470                  * Refers to:
 471                  *
 472                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 473                  * SOF/ITP Mode Used
 474                  */
 475                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 476                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 477                                 (dwc->revision >= DWC3_REVISION_210A &&
 478                                 dwc->revision <= DWC3_REVISION_250A))
 479                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 480                 else
 481                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 482                 break;
 483         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 484                 /* enable hibernation here */
 485                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 486
 487                 /*
 488                  * REVISIT Enabling this bit so that host-mode hibernation
 489                  * will work. Device-mode hibernation is not yet implemented.
 490                  */
 491                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 492                 break;
 493         default:
 494                 dev_dbg(dwc->dev, "No power optimization available\n");
 495         }
 496
 497         /* check if current dwc3 is on simulation board */
 498         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 499                 dev_dbg(dwc->dev, "it is on FPGA board\n");
 500                 dwc->is_fpga = true;
 501         }
 502
 503         if(dwc->disable_scramble_quirk && !dwc->is_fpga)
 504                 WARN(true,
 505                      "disable_scramble cannot be used on non-FPGA builds\n");
 506
 507         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 508                 reg |= DWC3_GCTL_DISSCRAMBLE;
 509         else
 510                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 511
 512         if (dwc->u2exit_lfps_quirk)
 513                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 514
 515         /*
 516          * WORKAROUND: DWC3 revisions <1.90a have a bug
 517          * where the device can fail to connect at SuperSpeed
 518          * and falls back to high-speed mode which causes
 519          * the device to enter a Connect/Disconnect loop
 520          */
 521         if (dwc->revision < DWC3_REVISION_190A)
 522                 reg |= DWC3_GCTL_U2RSTECN;
 523
 524         dwc3_core_num_eps(dwc);
 525
 526         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 527
 528         ret = dwc3_alloc_scratch_buffers(dwc);
 529         if (ret)
 530                 goto err0;
 531
 532         ret = dwc3_setup_scratch_buffers(dwc);
 533         if (ret)
 534                 goto err1;
 535
 536         return 0;
 537
 538 err1:
 539         dwc3_free_scratch_buffers(dwc);
 540
 541 err0:
 542         return ret;
 543 }
 544
 545 static void dwc3_core_exit(struct dwc3 *dwc)
 546 {
 547         dwc3_free_scratch_buffers(dwc);
 548 }
 549
 550 static int dwc3_core_init_mode(struct dwc3 *dwc)
 551 {
 552         int ret;
 553
 554         switch (dwc->dr_mode) {
 555         case USB_DR_MODE_PERIPHERAL:
 556                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 557                 ret = dwc3_gadget_init(dwc);
 558                 if (ret) {
 559                         dev_err(dev, "failed to initialize gadget\n");
 560                         return ret;
 561                 }
 562                 break;
 563         case USB_DR_MODE_HOST:
 564                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 565                 ret = dwc3_host_init(dwc);
 566                 if (ret) {
 567                         dev_err(dev, "failed to initialize host\n");
 568                         return ret;
 569                 }
 570                 break;
 571         case USB_DR_MODE_OTG:
 572                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 573                 ret = dwc3_host_init(dwc);
 574                 if (ret) {
 575                         dev_err(dev, "failed to initialize host\n");
 576                         return ret;
 577                 }
 578
 579                 ret = dwc3_gadget_init(dwc);
 580                 if (ret) {
 581                         dev_err(dev, "failed to initialize gadget\n");
 582                         return ret;
 583                 }
 584                 break;
 585         default:
 586                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 587                 return -EINVAL;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static void dwc3_gadget_run(struct dwc3 *dwc)
 594 {
 595         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
 596         mdelay(100);
 597 }
 598
 599 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 600 {
 601         switch (dwc->dr_mode) {
 602         case USB_DR_MODE_PERIPHERAL:
 603                 dwc3_gadget_exit(dwc);
 604                 break;
 605         case USB_DR_MODE_HOST:
 606                 dwc3_host_exit(dwc);
 607                 break;
 608         case USB_DR_MODE_OTG:
 609                 dwc3_host_exit(dwc);
 610                 dwc3_gadget_exit(dwc);
 611                 break;
 612         default:
 613                 /* do nothing */
 614                 break;
 615         }
 616
 617         /*
 618          * switch back to peripheral mode
 619          * This enables the phy to enter idle and then, if enabled, suspend.
 620          */
 621         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 622         dwc3_gadget_run(dwc);
 623 }
 624
 625 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
 626                                   struct dwc3 *dwc)
 627 {
 628         enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
 629         u32 reg;
 630
 631         /* Set dwc3 usb2 phy config */
 632         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 633
 634         switch (hsphy_mode) {
 635         case USBPHY_INTERFACE_MODE_UTMI:
 636                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 637                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 638                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 639                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 640                 break;
 641         case USBPHY_INTERFACE_MODE_UTMIW:
 642                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 643                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 644                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 645                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 646                 break;
 647         default:
 648                 break;
 649         }
 650
 651         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 652 }
 653
 654 #define DWC3_ALIGN_MASK         (16 - 1)
 655
 656 /**
 657  * dwc3_uboot_init - dwc3 core uboot initialization code
 658  * @dwc3_dev: struct dwc3_device containing initialization data
 659  *
 660  * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
 661  * kernel driver). Pointer to dwc3_device should be passed containing
 662  * base address and other initialization data. Returns '0' on success and
 663  * a negative value on failure.
 664  *
 665  * Generally called from board_usb_init() implemented in board file.
 666  */
 667 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 668 {
 669         struct dwc3             *dwc;
 670         struct device           *dev = NULL;
 671         u8                      lpm_nyet_threshold;
 672         u8                      tx_de_emphasis;
 673         u8                      hird_threshold;
 674
 675         int                     ret;
 676
 677         void                    *mem;
 678
 679         mem = devm_kzalloc((struct udevice *)dev,
 680                            sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 681         if (!mem)
 682                 return -ENOMEM;
 683
 684         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 685         dwc->mem = mem;
 686
 687         dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
 688                                         DWC3_GLOBALS_REGS_START);
 689
 690         /* default to highest possible threshold */
 691         lpm_nyet_threshold = 0xff;
 692
 693         /* default to -3.5dB de-emphasis */
 694         tx_de_emphasis = 1;
 695
 696         /*
 697          * default to assert utmi_sleep_n and use maximum allowed HIRD
 698          * threshold value of 0b1100
 699          */
 700         hird_threshold = 12;
 701
 702         dwc->maximum_speed = dwc3_dev->maximum_speed;
 703         dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
 704         if (dwc3_dev->lpm_nyet_threshold)
 705                 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
 706         dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
 707         if (dwc3_dev->hird_threshold)
 708                 hird_threshold = dwc3_dev->hird_threshold;
 709
 710         dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
 711         dwc->dr_mode = dwc3_dev->dr_mode;
 712
 713         dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
 714         dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
 715         dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
 716         dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
 717         dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
 718         dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
 719         dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
 720         dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
 721         dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
 722         dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 723         dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
 724
 725         dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 726         if (dwc3_dev->tx_de_emphasis)
 727                 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
 728
 729         /* default to superspeed if no maximum_speed passed */
 730         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 731                 dwc->maximum_speed = USB_SPEED_SUPER;
 732
 733         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 734         dwc->tx_de_emphasis = tx_de_emphasis;
 735
 736         dwc->hird_threshold = hird_threshold
 737                 | (dwc->is_utmi_l1_suspend << 4);
 738
 739         dwc->index = dwc3_dev->index;
 740
 741         dwc3_cache_hwparams(dwc);
 742
 743         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 744         if (ret) {
 745                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 746                 return -ENOMEM;
 747         }
 748
 749         if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 750                 dwc->dr_mode = USB_DR_MODE_HOST;
 751         else if (!IS_ENABLED(CONFIG_USB_HOST))
 752                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 753
 754         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 755                 dwc->dr_mode = USB_DR_MODE_OTG;
 756
 757         ret = dwc3_core_init(dwc);
 758         if (ret) {
 759                 dev_err(dev, "failed to initialize core\n");
 760                 goto err0;
 761         }
 762
 763         dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
 764
 765         ret = dwc3_event_buffers_setup(dwc);
 766         if (ret) {
 767                 dev_err(dwc->dev, "failed to setup event buffers\n");
 768                 goto err1;
 769         }
 770
 771         ret = dwc3_core_init_mode(dwc);
 772         if (ret)
 773                 goto err2;
 774
 775         list_add_tail(&dwc->list, &dwc3_list);
 776
 777         return 0;
 778
 779 err2:
 780         dwc3_event_buffers_cleanup(dwc);
 781
 782 err1:
 783         dwc3_core_exit(dwc);
 784
 785 err0:
 786         dwc3_free_event_buffers(dwc);
 787
 788         return ret;
 789 }
 790
 791 /**
 792  * dwc3_uboot_exit - dwc3 core uboot cleanup code
 793  * @index: index of this controller
 794  *
 795  * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
 796  * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
 797  * should be passed and should match with the index passed in
 798  * dwc3_device during init.
 799  *
 800  * Generally called from board file.
 801  */
 802 void dwc3_uboot_exit(int index)
 803 {
 804         struct dwc3 *dwc;
 805
 806         list_for_each_entry(dwc, &dwc3_list, list) {
 807                 if (dwc->index != index)
 808                         continue;
 809
 810                 dwc3_core_exit_mode(dwc);
 811                 dwc3_event_buffers_cleanup(dwc);
 812                 dwc3_free_event_buffers(dwc);
 813                 dwc3_core_exit(dwc);
 814                 list_del(&dwc->list);
 815                 kfree(dwc->mem);
 816                 break;
 817         }
 818 }
 819
 820 /**
 821  * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
 822  * @index: index of this controller
 823  *
 824  * Invokes dwc3 gadget interrupts.
 825  *
 826  * Generally called from board file.
 827  */
 828 void dwc3_uboot_handle_interrupt(int index)
 829 {
 830         struct dwc3 *dwc = NULL;
 831
 832         list_for_each_entry(dwc, &dwc3_list, list) {
 833                 if (dwc->index != index)
 834                         continue;
 835
 836                 dwc3_gadget_uboot_handle_interrupt(dwc);
 837                 break;
 838         }
 839 }
 840
 841 MODULE_ALIAS("platform:dwc3");
 842 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 843 MODULE_LICENSE("GPL v2");
 844 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
 845
 846 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
 847 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
 848 {
 849         int ret;
 850
 851         ret = generic_phy_get_bulk(dev, phys);
 852         if (ret)
 853                 return ret;
 854
 855         ret = generic_phy_init_bulk(phys);
 856         if (ret)
 857                 return ret;
 858
 859         ret = generic_phy_power_on_bulk(phys);
 860         if (ret)
 861                 generic_phy_exit_bulk(phys);
 862
 863         return ret;
 864 }
 865
 866 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
 867 {
 868         int ret;
 869
 870         ret = generic_phy_power_off_bulk(phys);
 871         ret |= generic_phy_exit_bulk(phys);
 872         return ret;
 873 }
 874 #endif
 875
 876 #if CONFIG_IS_ENABLED(DM_USB)
 877 void dwc3_of_parse(struct dwc3 *dwc)
 878 {
 879         const u8 *tmp;
 880         struct udevice *dev = dwc->dev;
 881         u8 lpm_nyet_threshold;
 882         u8 tx_de_emphasis;
 883         u8 hird_threshold;
 884
 885         /* default to highest possible threshold */
 886         lpm_nyet_threshold = 0xff;
 887
 888         /* default to -3.5dB de-emphasis */
 889         tx_de_emphasis = 1;
 890
 891         /*
 892          * default to assert utmi_sleep_n and use maximum allowed HIRD
 893          * threshold value of 0b1100
 894          */
 895         hird_threshold = 12;
 896
 897         dwc->has_lpm_erratum = dev_read_bool(dev,
 898                                 "snps,has-lpm-erratum");
 899         tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
 900         if (tmp)
 901                 lpm_nyet_threshold = *tmp;
 902
 903         dwc->is_utmi_l1_suspend = dev_read_bool(dev,
 904                                 "snps,is-utmi-l1-suspend");
 905         tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
 906         if (tmp)
 907                 hird_threshold = *tmp;
 908
 909         dwc->disable_scramble_quirk = dev_read_bool(dev,
 910                                 "snps,disable_scramble_quirk");
 911         dwc->u2exit_lfps_quirk = dev_read_bool(dev,
 912                                 "snps,u2exit_lfps_quirk");
 913         dwc->u2ss_inp3_quirk = dev_read_bool(dev,
 914                                 "snps,u2ss_inp3_quirk");
 915         dwc->req_p1p2p3_quirk = dev_read_bool(dev,
 916                                 "snps,req_p1p2p3_quirk");
 917         dwc->del_p1p2p3_quirk = dev_read_bool(dev,
 918                                 "snps,del_p1p2p3_quirk");
 919         dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
 920                                 "snps,del_phy_power_chg_quirk");
 921         dwc->lfps_filter_quirk = dev_read_bool(dev,
 922                                 "snps,lfps_filter_quirk");
 923         dwc->rx_detect_poll_quirk = dev_read_bool(dev,
 924                                 "snps,rx_detect_poll_quirk");
 925         dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
 926                                 "snps,dis_u3_susphy_quirk");
 927         dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
 928                                 "snps,dis_u2_susphy_quirk");
 929         dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
 930                                 "snps,dis-del-phy-power-chg-quirk");
 931         dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
 932                                 "snps,tx_de_emphasis_quirk");
 933         tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
 934         if (tmp)
 935                 tx_de_emphasis = *tmp;
 936
 937         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 938         dwc->tx_de_emphasis = tx_de_emphasis;
 939
 940         dwc->hird_threshold = hird_threshold
 941                 | (dwc->is_utmi_l1_suspend << 4);
 942 }
 943
 944 int dwc3_init(struct dwc3 *dwc)
 945 {
 946         int ret;
 947
 948         dwc3_cache_hwparams(dwc);
 949
 950         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 951         if (ret) {
 952                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 953                 return -ENOMEM;
 954         }
 955
 956         ret = dwc3_core_init(dwc);
 957         if (ret) {
 958                 dev_err(dev, "failed to initialize core\n");
 959                 goto core_fail;
 960         }
 961
 962         ret = dwc3_event_buffers_setup(dwc);
 963         if (ret) {
 964                 dev_err(dwc->dev, "failed to setup event buffers\n");
 965                 goto event_fail;
 966         }
 967
 968         ret = dwc3_core_init_mode(dwc);
 969         if (ret)
 970                 goto mode_fail;
 971
 972         return 0;
 973
 974 mode_fail:
 975         dwc3_event_buffers_cleanup(dwc);
 976
 977 event_fail:
 978         dwc3_core_exit(dwc);
 979
 980 core_fail:
 981         dwc3_free_event_buffers(dwc);
 982
 983         return ret;
 984 }
 985
 986 void dwc3_remove(struct dwc3 *dwc)
 987 {
 988         dwc3_core_exit_mode(dwc);
 989         dwc3_event_buffers_cleanup(dwc);
 990         dwc3_free_event_buffers(dwc);
 991         dwc3_core_exit(dwc);
 992         kfree(dwc->mem);
 993 }
 994 #endif