drivers/spi/zynqmp_gqspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2018 Xilinx
   4  *
   5  * Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/io.h>
  12 #include <clk.h>
  13 #include <dm.h>
  14 #include <malloc.h>
  15 #include <memalign.h>
  16 #include <spi.h>
  17 #include <ubi_uboot.h>
  18 #include <wait_bit.h>
  19 #include <dm/device_compat.h>
  20 #include <linux/err.h>
  21
  22 #define GQSPI_GFIFO_STRT_MODE_MASK      BIT(29)
  23 #define GQSPI_CONFIG_MODE_EN_MASK       (3 << 30)
  24 #define GQSPI_CONFIG_DMA_MODE           (2 << 30)
  25 #define GQSPI_CONFIG_CPHA_MASK          BIT(2)
  26 #define GQSPI_CONFIG_CPOL_MASK          BIT(1)
  27
  28 /*
  29  * QSPI Interrupt Registers bit Masks
  30  *
  31  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  32  * bit definitions.
  33  */
  34 #define GQSPI_IXR_TXNFULL_MASK          0x00000004 /* QSPI TX FIFO Overflow */
  35 #define GQSPI_IXR_TXFULL_MASK           0x00000008 /* QSPI TX FIFO is full */
  36 #define GQSPI_IXR_RXNEMTY_MASK          0x00000010 /* QSPI RX FIFO Not Empty */
  37 #define GQSPI_IXR_GFEMTY_MASK           0x00000080 /* QSPI Generic FIFO Empty */
  38 #define GQSPI_IXR_ALL_MASK              (GQSPI_IXR_TXNFULL_MASK | \
  39                                          GQSPI_IXR_RXNEMTY_MASK)
  40
  41 /*
  42  * QSPI Enable Register bit Masks
  43  *
  44  * This register is used to enable or disable the QSPI controller
  45  */
  46 #define GQSPI_ENABLE_ENABLE_MASK        0x00000001 /* QSPI Enable Bit Mask */
  47
  48 #define GQSPI_GFIFO_LOW_BUS             BIT(14)
  49 #define GQSPI_GFIFO_CS_LOWER            BIT(12)
  50 #define GQSPI_GFIFO_UP_BUS              BIT(15)
  51 #define GQSPI_GFIFO_CS_UPPER            BIT(13)
  52 #define GQSPI_SPI_MODE_QSPI             (3 << 10)
  53 #define GQSPI_SPI_MODE_SPI              BIT(10)
  54 #define GQSPI_SPI_MODE_DUAL_SPI         (2 << 10)
  55 #define GQSPI_IMD_DATA_CS_ASSERT        5
  56 #define GQSPI_IMD_DATA_CS_DEASSERT      5
  57 #define GQSPI_GFIFO_TX                  BIT(16)
  58 #define GQSPI_GFIFO_RX                  BIT(17)
  59 #define GQSPI_GFIFO_STRIPE_MASK         BIT(18)
  60 #define GQSPI_GFIFO_IMD_MASK            0xFF
  61 #define GQSPI_GFIFO_EXP_MASK            BIT(9)
  62 #define GQSPI_GFIFO_DATA_XFR_MASK       BIT(8)
  63 #define GQSPI_STRT_GEN_FIFO             BIT(28)
  64 #define GQSPI_GEN_FIFO_STRT_MOD         BIT(29)
  65 #define GQSPI_GFIFO_WP_HOLD             BIT(19)
  66 #define GQSPI_BAUD_DIV_MASK             (7 << 3)
  67 #define GQSPI_DFLT_BAUD_RATE_DIV        BIT(3)
  68 #define GQSPI_GFIFO_ALL_INT_MASK        0xFBE
  69 #define GQSPI_DMA_DST_I_STS_DONE        BIT(1)
  70 #define GQSPI_DMA_DST_I_STS_MASK        0xFE
  71 #define MODEBITS                        0x6
  72
  73 #define GQSPI_GFIFO_SELECT              BIT(0)
  74 #define GQSPI_FIFO_THRESHOLD            1
  75
  76 #define SPI_XFER_ON_BOTH                0
  77 #define SPI_XFER_ON_LOWER               1
  78 #define SPI_XFER_ON_UPPER               2
  79
  80 #define GQSPI_DMA_ALIGN                 0x4
  81 #define GQSPI_MAX_BAUD_RATE_VAL         7
  82 #define GQSPI_DFLT_BAUD_RATE_VAL        2
  83
  84 #define GQSPI_TIMEOUT                   100000000
  85
  86 #define GQSPI_BAUD_DIV_SHIFT            2
  87 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT   5
  88 #define GQSPI_LPBK_DLY_ADJ_DLY_1        0x2
  89 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT  3
  90 #define GQSPI_LPBK_DLY_ADJ_DLY_0        0x3
  91 #define GQSPI_USE_DATA_DLY              0x1
  92 #define GQSPI_USE_DATA_DLY_SHIFT        31
  93 #define GQSPI_DATA_DLY_ADJ_VALUE        0x2
  94 #define GQSPI_DATA_DLY_ADJ_SHIFT        28
  95 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE   0x1
  96 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT   2
  97 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
  98 #define IOU_TAPDLY_BYPASS_OFST          0xFF180390
  99 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK    0x00000020
 100 #define GQSPI_FREQ_40MHZ                40000000
 101 #define GQSPI_FREQ_100MHZ               100000000
 102 #define GQSPI_FREQ_150MHZ               150000000
 103 #define IOU_TAPDLY_BYPASS_MASK          0x7
 104
 105 #define GQSPI_REG_OFFSET                0x100
 106 #define GQSPI_DMA_REG_OFFSET            0x800
 107
 108 /* QSPI register offsets */
 109 struct zynqmp_qspi_regs {
 110         u32 confr;      /* 0x00 */
 111         u32 isr;        /* 0x04 */
 112         u32 ier;        /* 0x08 */
 113         u32 idisr;      /* 0x0C */
 114         u32 imaskr;     /* 0x10 */
 115         u32 enbr;       /* 0x14 */
 116         u32 dr;         /* 0x18 */
 117         u32 txd0r;      /* 0x1C */
 118         u32 drxr;       /* 0x20 */
 119         u32 sicr;       /* 0x24 */
 120         u32 txftr;      /* 0x28 */
 121         u32 rxftr;      /* 0x2C */
 122         u32 gpior;      /* 0x30 */
 123         u32 reserved0;  /* 0x34 */
 124         u32 lpbkdly;    /* 0x38 */
 125         u32 reserved1;  /* 0x3C */
 126         u32 genfifo;    /* 0x40 */
 127         u32 gqspisel;   /* 0x44 */
 128         u32 reserved2;  /* 0x48 */
 129         u32 gqfifoctrl; /* 0x4C */
 130         u32 gqfthr;     /* 0x50 */
 131         u32 gqpollcfg;  /* 0x54 */
 132         u32 gqpollto;   /* 0x58 */
 133         u32 gqxfersts;  /* 0x5C */
 134         u32 gqfifosnap; /* 0x60 */
 135         u32 gqrxcpy;    /* 0x64 */
 136         u32 reserved3[36];      /* 0x68 */
 137         u32 gqspidlyadj;        /* 0xF8 */
 138 };
 139
 140 struct zynqmp_qspi_dma_regs {
 141         u32 dmadst;     /* 0x00 */
 142         u32 dmasize;    /* 0x04 */
 143         u32 dmasts;     /* 0x08 */
 144         u32 dmactrl;    /* 0x0C */
 145         u32 reserved0;  /* 0x10 */
 146         u32 dmaisr;     /* 0x14 */
 147         u32 dmaier;     /* 0x18 */
 148         u32 dmaidr;     /* 0x1C */
 149         u32 dmaimr;     /* 0x20 */
 150         u32 dmactrl2;   /* 0x24 */
 151         u32 dmadstmsb;  /* 0x28 */
 152 };
 153
 154 DECLARE_GLOBAL_DATA_PTR;
 155
 156 struct zynqmp_qspi_platdata {
 157         struct zynqmp_qspi_regs *regs;
 158         struct zynqmp_qspi_dma_regs *dma_regs;
 159         u32 frequency;
 160         u32 speed_hz;
 161 };
 162
 163 struct zynqmp_qspi_priv {
 164         struct zynqmp_qspi_regs *regs;
 165         struct zynqmp_qspi_dma_regs *dma_regs;
 166         const void *tx_buf;
 167         void *rx_buf;
 168         unsigned int len;
 169         int bytes_to_transfer;
 170         int bytes_to_receive;
 171         unsigned int is_inst;
 172         unsigned int cs_change:1;
 173 };
 174
 175 static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
 176 {
 177         struct zynqmp_qspi_platdata *plat = bus->platdata;
 178
 179         debug("%s\n", __func__);
 180
 181         plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
 182                                                  GQSPI_REG_OFFSET);
 183         plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
 184                           (devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET);
 185
 186         return 0;
 187 }
 188
 189 static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
 190 {
 191         u32 config_reg;
 192         struct zynqmp_qspi_regs *regs = priv->regs;
 193
 194         writel(GQSPI_GFIFO_SELECT, &regs->gqspisel);
 195         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
 196         writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
 197         writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
 198         writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
 199
 200         config_reg = readl(&regs->confr);
 201         config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
 202                         GQSPI_CONFIG_MODE_EN_MASK);
 203         config_reg |= GQSPI_CONFIG_DMA_MODE |
 204                       GQSPI_GFIFO_WP_HOLD |
 205                       GQSPI_DFLT_BAUD_RATE_DIV;
 206         writel(config_reg, &regs->confr);
 207
 208         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 209 }
 210
 211 static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
 212 {
 213         u32 gqspi_fifo_reg = 0;
 214
 215         gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
 216                          GQSPI_GFIFO_CS_LOWER;
 217
 218         return gqspi_fifo_reg;
 219 }
 220
 221 static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
 222                                       u32 gqspi_fifo_reg)
 223 {
 224         struct zynqmp_qspi_regs *regs = priv->regs;
 225         int ret = 0;
 226
 227         ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
 228                                 GQSPI_TIMEOUT, 1);
 229         if (ret)
 230                 printf("%s Timeout\n", __func__);
 231
 232         writel(gqspi_fifo_reg, &regs->genfifo);
 233 }
 234
 235 static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
 236 {
 237         u32 gqspi_fifo_reg = 0;
 238
 239         if (is_on) {
 240                 gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
 241                 gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
 242                                   GQSPI_IMD_DATA_CS_ASSERT;
 243         } else {
 244                 gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
 245                 gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
 246         }
 247
 248         debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
 249
 250         zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 251 }
 252
 253 void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 254 {
 255         struct zynqmp_qspi_platdata *plat = bus->platdata;
 256         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 257         struct zynqmp_qspi_regs *regs = priv->regs;
 258         u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
 259         u32 reqhz = 0;
 260
 261         clk_rate = plat->frequency;
 262         reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
 263
 264         debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
 265               __func__, reqhz, clk_rate, baudrateval);
 266
 267         if (reqhz < GQSPI_FREQ_40MHZ) {
 268                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 269                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 270                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 271         } else if (reqhz <= GQSPI_FREQ_100MHZ) {
 272                 zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
 273                 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
 274                                 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
 275                 lpbkdlyadj = readl(&regs->lpbkdly);
 276                 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
 277                 datadlyadj = readl(&regs->gqspidlyadj);
 278                 datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
 279                                 | (GQSPI_DATA_DLY_ADJ_VALUE <<
 280                                         GQSPI_DATA_DLY_ADJ_SHIFT));
 281         } else if (reqhz <= GQSPI_FREQ_150MHZ) {
 282                 lpbkdlyadj = readl(&regs->lpbkdly);
 283                 lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
 284                                 GQSPI_LPBK_DLY_ADJ_DLY_0);
 285         }
 286
 287         zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
 288                           tapdlybypass);
 289         writel(lpbkdlyadj, &regs->lpbkdly);
 290         writel(datadlyadj, &regs->gqspidlyadj);
 291 }
 292
 293 static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
 294 {
 295         struct zynqmp_qspi_platdata *plat = bus->platdata;
 296         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 297         struct zynqmp_qspi_regs *regs = priv->regs;
 298         u32 confr;
 299         u8 baud_rate_val = 0;
 300
 301         debug("%s\n", __func__);
 302         if (speed > plat->frequency)
 303                 speed = plat->frequency;
 304
 305         /* Set the clock frequency */
 306         confr = readl(&regs->confr);
 307         if (speed == 0) {
 308                 /* Set baudrate x8, if the freq is 0 */
 309                 baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 310         } else if (plat->speed_hz != speed) {
 311                 while ((baud_rate_val < 8) &&
 312                        ((plat->frequency /
 313                        (2 << baud_rate_val)) > speed))
 314                         baud_rate_val++;
 315
 316                 if (baud_rate_val > GQSPI_MAX_BAUD_RATE_VAL)
 317                         baud_rate_val = GQSPI_DFLT_BAUD_RATE_VAL;
 318
 319                 plat->speed_hz = plat->frequency / (2 << baud_rate_val);
 320         }
 321         confr &= ~GQSPI_BAUD_DIV_MASK;
 322         confr |= (baud_rate_val << 3);
 323         writel(confr, &regs->confr);
 324
 325         zynqmp_qspi_set_tapdelay(bus, baud_rate_val);
 326         debug("regs=%p, speed=%d\n", priv->regs, plat->speed_hz);
 327
 328         return 0;
 329 }
 330
 331 static int zynqmp_qspi_probe(struct udevice *bus)
 332 {
 333         struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
 334         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 335         struct clk clk;
 336         unsigned long clock;
 337         int ret;
 338
 339         debug("%s: bus:%p, priv:%p\n", __func__, bus, priv);
 340
 341         priv->regs = plat->regs;
 342         priv->dma_regs = plat->dma_regs;
 343
 344         ret = clk_get_by_index(bus, 0, &clk);
 345         if (ret < 0) {
 346                 dev_err(dev, "failed to get clock\n");
 347                 return ret;
 348         }
 349
 350         clock = clk_get_rate(&clk);
 351         if (IS_ERR_VALUE(clock)) {
 352                 dev_err(dev, "failed to get rate\n");
 353                 return clock;
 354         }
 355         debug("%s: CLK %ld\n", __func__, clock);
 356
 357         ret = clk_enable(&clk);
 358         if (ret && ret != -ENOSYS) {
 359                 dev_err(dev, "failed to enable clock\n");
 360                 return ret;
 361         }
 362         plat->frequency = clock;
 363         plat->speed_hz = plat->frequency / 2;
 364
 365         /* init the zynq spi hw */
 366         zynqmp_qspi_init_hw(priv);
 367
 368         return 0;
 369 }
 370
 371 static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
 372 {
 373         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 374         struct zynqmp_qspi_regs *regs = priv->regs;
 375         u32 confr;
 376
 377         debug("%s\n", __func__);
 378         /* Set the SPI Clock phase and polarities */
 379         confr = readl(&regs->confr);
 380         confr &= ~(GQSPI_CONFIG_CPHA_MASK |
 381                    GQSPI_CONFIG_CPOL_MASK);
 382
 383         if (mode & SPI_CPHA)
 384                 confr |= GQSPI_CONFIG_CPHA_MASK;
 385         if (mode & SPI_CPOL)
 386                 confr |= GQSPI_CONFIG_CPOL_MASK;
 387
 388         writel(confr, &regs->confr);
 389
 390         return 0;
 391 }
 392
 393 static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
 394 {
 395         u32 data;
 396         int ret = 0;
 397         struct zynqmp_qspi_regs *regs = priv->regs;
 398         u32 *buf = (u32 *)priv->tx_buf;
 399         u32 len = size;
 400
 401         debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr),
 402               size);
 403
 404         while (size) {
 405                 ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXNFULL_MASK, 1,
 406                                         GQSPI_TIMEOUT, 1);
 407                 if (ret) {
 408                         printf("%s: Timeout\n", __func__);
 409                         return ret;
 410                 }
 411
 412                 if (size >= 4) {
 413                         writel(*buf, &regs->txd0r);
 414                         buf++;
 415                         size -= 4;
 416                 } else {
 417                         switch (size) {
 418                         case 1:
 419                                 data = *((u8 *)buf);
 420                                 buf += 1;
 421                                 data |= GENMASK(31, 8);
 422                                 break;
 423                         case 2:
 424                                 data = *((u16 *)buf);
 425                                 buf += 2;
 426                                 data |= GENMASK(31, 16);
 427                                 break;
 428                         case 3:
 429                                 data = *((u16 *)buf);
 430                                 buf += 2;
 431                                 data |= (*((u8 *)buf) << 16);
 432                                 buf += 1;
 433                                 data |= GENMASK(31, 24);
 434                                 break;
 435                         }
 436                         writel(data, &regs->txd0r);
 437                         size = 0;
 438                 }
 439         }
 440
 441         priv->tx_buf += len;
 442         return 0;
 443 }
 444
 445 static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
 446 {
 447         u32 gen_fifo_cmd;
 448         u32 bytecount = 0;
 449
 450         while (priv->len) {
 451                 gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 452                 gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_SPI_MODE_SPI;
 453                 gen_fifo_cmd |= *(u8 *)priv->tx_buf;
 454                 bytecount++;
 455                 priv->len--;
 456                 priv->tx_buf = (u8 *)priv->tx_buf + 1;
 457
 458                 debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
 459
 460                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 461         }
 462 }
 463
 464 static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
 465                                 u32 *gen_fifo_cmd)
 466 {
 467         u32 expval = 8;
 468         u32 len;
 469
 470         while (1) {
 471                 if (priv->len > 255) {
 472                         if (priv->len & (1 << expval)) {
 473                                 *gen_fifo_cmd &= ~GQSPI_GFIFO_IMD_MASK;
 474                                 *gen_fifo_cmd |= GQSPI_GFIFO_EXP_MASK;
 475                                 *gen_fifo_cmd |= expval;
 476                                 priv->len -= (1 << expval);
 477                                 return expval;
 478                         }
 479                         expval++;
 480                 } else {
 481                         *gen_fifo_cmd &= ~(GQSPI_GFIFO_IMD_MASK |
 482                                           GQSPI_GFIFO_EXP_MASK);
 483                         *gen_fifo_cmd |= (u8)priv->len;
 484                         len = (u8)priv->len;
 485                         priv->len  = 0;
 486                         return len;
 487                 }
 488         }
 489 }
 490
 491 static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
 492 {
 493         u32 gen_fifo_cmd;
 494         u32 len;
 495         int ret = 0;
 496
 497         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 498         gen_fifo_cmd |= GQSPI_GFIFO_TX |
 499                         GQSPI_GFIFO_DATA_XFR_MASK;
 500
 501         gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
 502
 503         while (priv->len) {
 504                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 505                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 506
 507                 debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
 508
 509                 if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
 510                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 511                                                        1 << len);
 512                 else
 513                         ret = zynqmp_qspi_fill_tx_fifo(priv,
 514                                                        len);
 515
 516                 if (ret)
 517                         return ret;
 518         }
 519         return ret;
 520 }
 521
 522 static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
 523                                  u32 gen_fifo_cmd, u32 *buf)
 524 {
 525         u32 addr;
 526         u32 size, len;
 527         u32 actuallen = priv->len;
 528         int ret = 0;
 529         struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
 530
 531         writel((unsigned long)buf, &dma_regs->dmadst);
 532         writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
 533         writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
 534         addr = (unsigned long)buf;
 535         size = roundup(priv->len, ARCH_DMA_MINALIGN);
 536         flush_dcache_range(addr, addr + size);
 537
 538         while (priv->len) {
 539                 len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
 540                 if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
 541                     (len % ARCH_DMA_MINALIGN)) {
 542                         gen_fifo_cmd &= ~GENMASK(7, 0);
 543                         gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
 544                 }
 545                 zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
 546
 547                 debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
 548         }
 549
 550         ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE,
 551                                 1, GQSPI_TIMEOUT, 1);
 552         if (ret) {
 553                 printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
 554                 return -ETIMEDOUT;
 555         }
 556
 557         writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
 558
 559         debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
 560               (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
 561               actuallen);
 562
 563         if (buf != priv->rx_buf)
 564                 memcpy(priv->rx_buf, buf, actuallen);
 565
 566         return 0;
 567 }
 568
 569 static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
 570 {
 571         u32 gen_fifo_cmd;
 572         u32 *buf;
 573         u32 actuallen = priv->len;
 574
 575         gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
 576         gen_fifo_cmd |= GQSPI_GFIFO_RX |
 577                         GQSPI_GFIFO_DATA_XFR_MASK;
 578
 579         gen_fifo_cmd |= GQSPI_SPI_MODE_SPI;
 580
 581         /*
 582          * Check if receive buffer is aligned to 4 byte and length
 583          * is multiples of four byte as we are using dma to receive.
 584          */
 585         if (!((unsigned long)priv->rx_buf & (GQSPI_DMA_ALIGN - 1)) &&
 586             !(actuallen % GQSPI_DMA_ALIGN)) {
 587                 buf = (u32 *)priv->rx_buf;
 588                 return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 589         }
 590
 591         ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
 592                                                   GQSPI_DMA_ALIGN));
 593         buf = (u32 *)tmp;
 594         return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
 595 }
 596
 597 static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
 598 {
 599         int ret = 0;
 600
 601         if (priv->is_inst) {
 602                 if (priv->tx_buf)
 603                         zynqmp_qspi_genfifo_cmd(priv);
 604                 else
 605                         return -EINVAL;
 606         } else {
 607                 if (priv->tx_buf)
 608                         ret = zynqmp_qspi_genfifo_fill_tx(priv);
 609                 else if (priv->rx_buf)
 610                         ret = zynqmp_qspi_genfifo_fill_rx(priv);
 611                 else
 612                         return -EINVAL;
 613         }
 614         return ret;
 615 }
 616
 617 static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
 618 {
 619         static unsigned int cs_change = 1;
 620         int status = 0;
 621
 622         debug("%s\n", __func__);
 623
 624         while (1) {
 625                 /* Select the chip if required */
 626                 if (cs_change)
 627                         zynqmp_qspi_chipselect(priv, 1);
 628
 629                 cs_change = priv->cs_change;
 630
 631                 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
 632                         status = -EINVAL;
 633                         break;
 634                 }
 635
 636                 /* Request the transfer */
 637                 if (priv->len) {
 638                         status = zynqmp_qspi_start_transfer(priv);
 639                         priv->is_inst = 0;
 640                         if (status < 0)
 641                                 break;
 642                 }
 643
 644                 if (cs_change)
 645                         /* Deselect the chip */
 646                         zynqmp_qspi_chipselect(priv, 0);
 647                 break;
 648         }
 649
 650         return status;
 651 }
 652
 653 static int zynqmp_qspi_claim_bus(struct udevice *dev)
 654 {
 655         struct udevice *bus = dev->parent;
 656         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 657         struct zynqmp_qspi_regs *regs = priv->regs;
 658
 659         writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 660
 661         return 0;
 662 }
 663
 664 static int zynqmp_qspi_release_bus(struct udevice *dev)
 665 {
 666         struct udevice *bus = dev->parent;
 667         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 668         struct zynqmp_qspi_regs *regs = priv->regs;
 669
 670         writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
 671
 672         return 0;
 673 }
 674
 675 int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
 676                      void *din, unsigned long flags)
 677 {
 678         struct udevice *bus = dev->parent;
 679         struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
 680
 681         debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
 682               (unsigned long)priv, bitlen, (unsigned long)dout);
 683         debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
 684
 685         priv->tx_buf = dout;
 686         priv->rx_buf = din;
 687         priv->len = bitlen / 8;
 688
 689         /*
 690          * Assume that the beginning of a transfer with bits to
 691          * transmit must contain a device command.
 692          */
 693         if (dout && flags & SPI_XFER_BEGIN)
 694                 priv->is_inst = 1;
 695         else
 696                 priv->is_inst = 0;
 697
 698         if (flags & SPI_XFER_END)
 699                 priv->cs_change = 1;
 700         else
 701                 priv->cs_change = 0;
 702
 703         zynqmp_qspi_transfer(priv);
 704
 705         return 0;
 706 }
 707
 708 static const struct dm_spi_ops zynqmp_qspi_ops = {
 709         .claim_bus      = zynqmp_qspi_claim_bus,
 710         .release_bus    = zynqmp_qspi_release_bus,
 711         .xfer           = zynqmp_qspi_xfer,
 712         .set_speed      = zynqmp_qspi_set_speed,
 713         .set_mode       = zynqmp_qspi_set_mode,
 714 };
 715
 716 static const struct udevice_id zynqmp_qspi_ids[] = {
 717         { .compatible = "xlnx,zynqmp-qspi-1.0" },
 718         { .compatible = "xlnx,versal-qspi-1.0" },
 719         { }
 720 };
 721
 722 U_BOOT_DRIVER(zynqmp_qspi) = {
 723         .name   = "zynqmp_qspi",
 724         .id     = UCLASS_SPI,
 725         .of_match = zynqmp_qspi_ids,
 726         .ops    = &zynqmp_qspi_ops,
 727         .ofdata_to_platdata = zynqmp_qspi_ofdata_to_platdata,
 728         .platdata_auto_alloc_size = sizeof(struct zynqmp_qspi_platdata),
 729         .priv_auto_alloc_size = sizeof(struct zynqmp_qspi_priv),
 730         .probe  = zynqmp_qspi_probe,
 731 };