drivers/spi/ti_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI QSPI driver
   4  *
   5  * Copyright (C) 2013, Texas Instruments, Incorporated
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/omap.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14 #include <spi-mem.h>
  15 #include <dm.h>
  16 #include <asm/gpio.h>
  17 #include <asm/omap_gpio.h>
  18 #include <asm/omap_common.h>
  19 #include <asm/ti-common/ti-edma3.h>
  20 #include <linux/err.h>
  21 #include <linux/kernel.h>
  22 #include <regmap.h>
  23 #include <syscon.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* ti qpsi register bit masks */
  28 #define QSPI_TIMEOUT                    2000000
  29 #define QSPI_FCLK                       192000000
  30 #define QSPI_DRA7XX_FCLK                76800000
  31 #define QSPI_WLEN_MAX_BITS              128
  32 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  33 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  34 /* clock control */
  35 #define QSPI_CLK_EN                     BIT(31)
  36 #define QSPI_CLK_DIV_MAX                0xffff
  37 /* command */
  38 #define QSPI_EN_CS(n)                   (n << 28)
  39 #define QSPI_WLEN(n)                    ((n-1) << 19)
  40 #define QSPI_3_PIN                      BIT(18)
  41 #define QSPI_RD_SNGL                    BIT(16)
  42 #define QSPI_WR_SNGL                    (2 << 16)
  43 #define QSPI_INVAL                      (4 << 16)
  44 #define QSPI_RD_QUAD                    (7 << 16)
  45 /* device control */
  46 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  47 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  48 #define QSPI_CKPOL(n)                   (1 << (n*8))
  49 /* status */
  50 #define QSPI_WC                         BIT(1)
  51 #define QSPI_BUSY                       BIT(0)
  52 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  53 #define QSPI_XFER_DONE                  QSPI_WC
  54 #define MM_SWITCH                       0x01
  55 #define MEM_CS(cs)                      ((cs + 1) << 8)
  56 #define MEM_CS_UNSELECT                 0xfffff8ff
  57
  58 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  59 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  60 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  61 #define QSPI_SETUP0_ADDR_SHIFT          (8)
  62 #define QSPI_SETUP0_DBITS_SHIFT         (10)
  63
  64 #define TI_QSPI_SETUP_REG(priv, cs)     (&(priv)->base->setup0 + (cs))
  65
  66 /* ti qspi register set */
  67 struct ti_qspi_regs {
  68         u32 pid;
  69         u32 pad0[3];
  70         u32 sysconfig;
  71         u32 pad1[3];
  72         u32 int_stat_raw;
  73         u32 int_stat_en;
  74         u32 int_en_set;
  75         u32 int_en_ctlr;
  76         u32 intc_eoi;
  77         u32 pad2[3];
  78         u32 clk_ctrl;
  79         u32 dc;
  80         u32 cmd;
  81         u32 status;
  82         u32 data;
  83         u32 setup0;
  84         u32 setup1;
  85         u32 setup2;
  86         u32 setup3;
  87         u32 memswitch;
  88         u32 data1;
  89         u32 data2;
  90         u32 data3;
  91 };
  92
  93 /* ti qspi priv */
  94 struct ti_qspi_priv {
  95         void *memory_map;
  96         size_t mmap_size;
  97         uint max_hz;
  98         u32 num_cs;
  99         struct ti_qspi_regs *base;
 100         void *ctrl_mod_mmap;
 101         ulong fclk;
 102         unsigned int mode;
 103         u32 cmd;
 104         u32 dc;
 105 };
 106
 107 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
 108 {
 109         struct ti_qspi_priv *priv = dev_get_priv(bus);
 110         uint clk_div;
 111
 112         if (!hz)
 113                 clk_div = 0;
 114         else
 115                 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 116
 117         /* truncate clk_div value to QSPI_CLK_DIV_MAX */
 118         if (clk_div > QSPI_CLK_DIV_MAX)
 119                 clk_div = QSPI_CLK_DIV_MAX;
 120
 121         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 122
 123         /* disable SCLK */
 124         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 125                &priv->base->clk_ctrl);
 126         /* enable SCLK and program the clk divider */
 127         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 128
 129         return 0;
 130 }
 131
 132 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 133 {
 134         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 135         /* dummy readl to ensure bus sync */
 136         readl(&priv->base->cmd);
 137 }
 138
 139 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 140 {
 141         u32 val;
 142
 143         val = readl(ctrl_mod_mmap);
 144         if (enable)
 145                 val |= MEM_CS(cs);
 146         else
 147                 val &= MEM_CS_UNSELECT;
 148         writel(val, ctrl_mod_mmap);
 149 }
 150
 151 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 152                         const void *dout, void *din, unsigned long flags)
 153 {
 154         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 155         struct ti_qspi_priv *priv;
 156         struct udevice *bus;
 157         uint words = bitlen >> 3; /* fixed 8-bit word length */
 158         const uchar *txp = dout;
 159         uchar *rxp = din;
 160         uint status;
 161         int timeout;
 162         unsigned int cs = slave->cs;
 163
 164         bus = dev->parent;
 165         priv = dev_get_priv(bus);
 166
 167         if (cs > priv->num_cs) {
 168                 debug("invalid qspi chip select\n");
 169                 return -EINVAL;
 170         }
 171
 172         if (bitlen == 0)
 173                 return -1;
 174
 175         if (bitlen % 8) {
 176                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 177                 return -1;
 178         }
 179
 180         /* Setup command reg */
 181         priv->cmd = 0;
 182         priv->cmd |= QSPI_WLEN(8);
 183         priv->cmd |= QSPI_EN_CS(cs);
 184         if (priv->mode & SPI_3WIRE)
 185                 priv->cmd |= QSPI_3_PIN;
 186         priv->cmd |= 0xfff;
 187
 188         while (words) {
 189                 u8 xfer_len = 0;
 190
 191                 if (txp) {
 192                         u32 cmd = priv->cmd;
 193
 194                         if (words >= QSPI_WLEN_MAX_BYTES) {
 195                                 u32 *txbuf = (u32 *)txp;
 196                                 u32 data;
 197
 198                                 data = cpu_to_be32(*txbuf++);
 199                                 writel(data, &priv->base->data3);
 200                                 data = cpu_to_be32(*txbuf++);
 201                                 writel(data, &priv->base->data2);
 202                                 data = cpu_to_be32(*txbuf++);
 203                                 writel(data, &priv->base->data1);
 204                                 data = cpu_to_be32(*txbuf++);
 205                                 writel(data, &priv->base->data);
 206                                 cmd &= ~QSPI_WLEN_MASK;
 207                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 208                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 209                         } else {
 210                                 writeb(*txp, &priv->base->data);
 211                                 xfer_len = 1;
 212                         }
 213                         debug("tx cmd %08x dc %08x\n",
 214                               cmd | QSPI_WR_SNGL, priv->dc);
 215                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 216                         status = readl(&priv->base->status);
 217                         timeout = QSPI_TIMEOUT;
 218                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 219                                 if (--timeout < 0) {
 220                                         printf("spi_xfer: TX timeout!\n");
 221                                         return -1;
 222                                 }
 223                                 status = readl(&priv->base->status);
 224                         }
 225                         txp += xfer_len;
 226                         debug("tx done, status %08x\n", status);
 227                 }
 228                 if (rxp) {
 229                         debug("rx cmd %08x dc %08x\n",
 230                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 231                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 232                         status = readl(&priv->base->status);
 233                         timeout = QSPI_TIMEOUT;
 234                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 235                                 if (--timeout < 0) {
 236                                         printf("spi_xfer: RX timeout!\n");
 237                                         return -1;
 238                                 }
 239                                 status = readl(&priv->base->status);
 240                         }
 241                         *rxp++ = readl(&priv->base->data);
 242                         xfer_len = 1;
 243                         debug("rx done, status %08x, read %02x\n",
 244                               status, *(rxp-1));
 245                 }
 246                 words -= xfer_len;
 247         }
 248
 249         /* Terminate frame */
 250         if (flags & SPI_XFER_END)
 251                 ti_qspi_cs_deactivate(priv);
 252
 253         return 0;
 254 }
 255
 256 /* TODO: control from sf layer to here through dm-spi */
 257 static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
 258 {
 259 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 260         unsigned int                    addr = (unsigned int) (data);
 261         unsigned int                    edma_slot_num = 1;
 262
 263         /* Invalidate the area, so no writeback into the RAM races with DMA */
 264         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 265
 266         /* enable edma3 clocks */
 267         enable_edma3_clocks();
 268
 269         /* Call edma3 api to do actual DMA transfer     */
 270         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 271
 272         /* disable edma3 clocks */
 273         disable_edma3_clocks();
 274 #else
 275         memcpy_fromio(data, offset, len);
 276 #endif
 277
 278         *((unsigned int *)offset) += len;
 279 }
 280
 281 static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
 282                                     u8 opcode, u8 data_nbits, u8 addr_width,
 283                                     u8 dummy_bytes)
 284 {
 285         u32 memval = opcode;
 286
 287         switch (data_nbits) {
 288         case 4:
 289                 memval |= QSPI_SETUP0_READ_QUAD;
 290                 break;
 291         case 2:
 292                 memval |= QSPI_SETUP0_READ_DUAL;
 293                 break;
 294         default:
 295                 memval |= QSPI_SETUP0_READ_NORMAL;
 296                 break;
 297         }
 298
 299         memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
 300                    dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
 301
 302         writel(memval, TI_QSPI_SETUP_REG(priv, cs));
 303 }
 304
 305 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 306 {
 307         struct ti_qspi_priv *priv = dev_get_priv(bus);
 308
 309         priv->dc = 0;
 310         if (mode & SPI_CPHA)
 311                 priv->dc |= QSPI_CKPHA(0);
 312         if (mode & SPI_CPOL)
 313                 priv->dc |= QSPI_CKPOL(0);
 314         if (mode & SPI_CS_HIGH)
 315                 priv->dc |= QSPI_CSPOL(0);
 316
 317         return 0;
 318 }
 319
 320 static int ti_qspi_exec_mem_op(struct spi_slave *slave,
 321                                const struct spi_mem_op *op)
 322 {
 323         struct dm_spi_slave_platdata *slave_plat;
 324         struct ti_qspi_priv *priv;
 325         struct udevice *bus;
 326         u32 from = 0;
 327         int ret = 0;
 328
 329         bus = slave->dev->parent;
 330         priv = dev_get_priv(bus);
 331         slave_plat = dev_get_parent_platdata(slave->dev);
 332
 333         /* Only optimize read path. */
 334         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 335             !op->addr.nbytes || op->addr.nbytes > 4)
 336                 return -ENOTSUPP;
 337
 338         /* Address exceeds MMIO window size, fall back to regular mode. */
 339         from = op->addr.val;
 340         if (from + op->data.nbytes > priv->mmap_size)
 341                 return -ENOTSUPP;
 342
 343         ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
 344                                 op->data.buswidth, op->addr.nbytes,
 345                                 op->dummy.nbytes);
 346
 347         ti_qspi_copy_mmap((void *)op->data.buf.in,
 348                           (void *)priv->memory_map + from, op->data.nbytes);
 349
 350         return ret;
 351 }
 352
 353 static int ti_qspi_claim_bus(struct udevice *dev)
 354 {
 355         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 356         struct ti_qspi_priv *priv;
 357         struct udevice *bus;
 358
 359         bus = dev->parent;
 360         priv = dev_get_priv(bus);
 361
 362         if (slave_plat->cs > priv->num_cs) {
 363                 debug("invalid qspi chip select\n");
 364                 return -EINVAL;
 365         }
 366
 367         writel(MM_SWITCH, &priv->base->memswitch);
 368         if (priv->ctrl_mod_mmap)
 369                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 370                                        slave_plat->cs, true);
 371
 372         writel(priv->dc, &priv->base->dc);
 373         writel(0, &priv->base->cmd);
 374         writel(0, &priv->base->data);
 375
 376         priv->dc <<= slave_plat->cs * 8;
 377         writel(priv->dc, &priv->base->dc);
 378
 379         return 0;
 380 }
 381
 382 static int ti_qspi_release_bus(struct udevice *dev)
 383 {
 384         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 385         struct ti_qspi_priv *priv;
 386         struct udevice *bus;
 387
 388         bus = dev->parent;
 389         priv = dev_get_priv(bus);
 390
 391         writel(~MM_SWITCH, &priv->base->memswitch);
 392         if (priv->ctrl_mod_mmap)
 393                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 394                                        slave_plat->cs, false);
 395
 396         writel(0, &priv->base->dc);
 397         writel(0, &priv->base->cmd);
 398         writel(0, &priv->base->data);
 399         writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
 400
 401         return 0;
 402 }
 403
 404 static int ti_qspi_probe(struct udevice *bus)
 405 {
 406         struct ti_qspi_priv *priv = dev_get_priv(bus);
 407
 408         priv->fclk = dev_get_driver_data(bus);
 409
 410         return 0;
 411 }
 412
 413 static void *map_syscon_chipselects(struct udevice *bus)
 414 {
 415 #if CONFIG_IS_ENABLED(SYSCON)
 416         struct udevice *syscon;
 417         struct regmap *regmap;
 418         const fdt32_t *cell;
 419         int len, err;
 420
 421         err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
 422                                            "syscon-chipselects", &syscon);
 423         if (err) {
 424                 debug("%s: unable to find syscon device (%d)\n", __func__,
 425                       err);
 426                 return NULL;
 427         }
 428
 429         regmap = syscon_get_regmap(syscon);
 430         if (IS_ERR(regmap)) {
 431                 debug("%s: unable to find regmap (%ld)\n", __func__,
 432                       PTR_ERR(regmap));
 433                 return NULL;
 434         }
 435
 436         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
 437                            "syscon-chipselects", &len);
 438         if (len < 2*sizeof(fdt32_t)) {
 439                 debug("%s: offset not available\n", __func__);
 440                 return NULL;
 441         }
 442
 443         return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
 444 #else
 445         fdt_addr_t addr;
 446         addr = devfdt_get_addr_index(bus, 2);
 447         return (addr == FDT_ADDR_T_NONE) ? NULL :
 448                 map_physmem(addr, 0, MAP_NOCACHE);
 449 #endif
 450 }
 451
 452 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 453 {
 454         struct ti_qspi_priv *priv = dev_get_priv(bus);
 455         const void *blob = gd->fdt_blob;
 456         int node = dev_of_offset(bus);
 457         fdt_addr_t mmap_addr;
 458         fdt_addr_t mmap_size;
 459
 460         priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 461         priv->base = map_physmem(devfdt_get_addr(bus),
 462                                  sizeof(struct ti_qspi_regs), MAP_NOCACHE);
 463         mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
 464         priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
 465         priv->mmap_size = mmap_size;
 466
 467         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 468         if (priv->max_hz < 0) {
 469                 debug("Error: Max frequency missing\n");
 470                 return -ENODEV;
 471         }
 472         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 473
 474         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 475               (int)priv->base, priv->max_hz);
 476
 477         return 0;
 478 }
 479
 480 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 481         .exec_op = ti_qspi_exec_mem_op,
 482 };
 483
 484 static const struct dm_spi_ops ti_qspi_ops = {
 485         .claim_bus      = ti_qspi_claim_bus,
 486         .release_bus    = ti_qspi_release_bus,
 487         .xfer           = ti_qspi_xfer,
 488         .set_speed      = ti_qspi_set_speed,
 489         .set_mode       = ti_qspi_set_mode,
 490         .mem_ops        = &ti_qspi_mem_ops,
 491 };
 492
 493 static const struct udevice_id ti_qspi_ids[] = {
 494         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 495         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 496         { }
 497 };
 498
 499 U_BOOT_DRIVER(ti_qspi) = {
 500         .name   = "ti_qspi",
 501         .id     = UCLASS_SPI,
 502         .of_match = ti_qspi_ids,
 503         .ops    = &ti_qspi_ops,
 504         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 505         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 506         .probe  = ti_qspi_probe,
 507 };