1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2010-2013 NVIDIA Corporation
4 * With help from the mpc8xxx SPI driver
5 * With more help from omap3_spi SPI driver
15 #include <asm/arch/clock.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch-tegra/clk_rst.h>
20 #include "tegra_spi.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 #define SPI_CMD_GO BIT(30)
25 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
26 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
27 #define SPI_CMD_CK_SDA BIT(21)
28 #define SPI_CMD_ACTIVE_SDA_SHIFT 18
29 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
30 #define SPI_CMD_CS_POL BIT(16)
31 #define SPI_CMD_TXEN BIT(15)
32 #define SPI_CMD_RXEN BIT(14)
33 #define SPI_CMD_CS_VAL BIT(13)
34 #define SPI_CMD_CS_SOFT BIT(12)
35 #define SPI_CMD_CS_DELAY BIT(9)
36 #define SPI_CMD_CS3_EN BIT(8)
37 #define SPI_CMD_CS2_EN BIT(7)
38 #define SPI_CMD_CS1_EN BIT(6)
39 #define SPI_CMD_CS0_EN BIT(5)
40 #define SPI_CMD_BIT_LENGTH BIT(4)
41 #define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
43 #define SPI_STAT_BSY BIT(31)
44 #define SPI_STAT_RDY BIT(30)
45 #define SPI_STAT_RXF_FLUSH BIT(29)
46 #define SPI_STAT_TXF_FLUSH BIT(28)
47 #define SPI_STAT_RXF_UNR BIT(27)
48 #define SPI_STAT_TXF_OVF BIT(26)
49 #define SPI_STAT_RXF_EMPTY BIT(25)
50 #define SPI_STAT_RXF_FULL BIT(24)
51 #define SPI_STAT_TXF_EMPTY BIT(23)
52 #define SPI_STAT_TXF_FULL BIT(22)
53 #define SPI_STAT_SEL_TXRX_N BIT(16)
54 #define SPI_STAT_CUR_BLKCNT BIT(15)
56 #define SPI_TIMEOUT 1000
57 #define TEGRA_SPI_MAX_FREQ 52000000
60 u32 command; /* SPI_COMMAND_0 register */
61 u32 status; /* SPI_STATUS_0 register */
62 u32 rx_cmp; /* SPI_RX_CMP_0 register */
63 u32 dma_ctl; /* SPI_DMA_CTL_0 register */
64 u32 tx_fifo; /* SPI_TX_FIFO_0 register */
65 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
66 u32 rx_fifo; /* SPI_RX_FIFO_0 register */
69 struct tegra20_sflash_priv {
70 struct spi_regs *regs;
75 int last_transaction_us;
78 int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
79 struct spi_cs_info *info)
81 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
88 static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
90 struct tegra_spi_platdata *plat = bus->platdata;
91 const void *blob = gd->fdt_blob;
92 int node = dev_of_offset(bus);
94 plat->base = devfdt_get_addr(bus);
95 plat->periph_id = clock_decode_periph_id(bus);
97 if (plat->periph_id == PERIPH_ID_NONE) {
98 debug("%s: could not decode periph id %d\n", __func__,
100 return -FDT_ERR_NOTFOUND;
103 /* Use 500KHz as a suitable default */
104 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
106 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
107 "spi-deactivate-delay", 0);
108 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
109 __func__, plat->base, plat->periph_id, plat->frequency,
110 plat->deactivate_delay_us);
115 static int tegra20_sflash_probe(struct udevice *bus)
117 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
118 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
120 priv->regs = (struct spi_regs *)plat->base;
122 priv->last_transaction_us = timer_get_us();
123 priv->freq = plat->frequency;
124 priv->periph_id = plat->periph_id;
126 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
127 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
133 static int tegra20_sflash_claim_bus(struct udevice *dev)
135 struct udevice *bus = dev->parent;
136 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
137 struct spi_regs *regs = priv->regs;
140 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
141 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
144 /* Clear stale status here */
145 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
146 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
147 writel(reg, ®s->status);
148 debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
151 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
153 reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
155 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
156 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
157 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
158 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
161 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
164 pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
165 pinmux_tristate_disable(PMUX_PINGRP_LSPI);
166 pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
171 static void spi_cs_activate(struct udevice *dev)
173 struct udevice *bus = dev->parent;
174 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
175 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
177 /* If it's too soon to do another transaction, wait */
178 if (pdata->deactivate_delay_us &&
179 priv->last_transaction_us) {
180 ulong delay_us; /* The delay completed so far */
181 delay_us = timer_get_us() - priv->last_transaction_us;
182 if (delay_us < pdata->deactivate_delay_us)
183 udelay(pdata->deactivate_delay_us - delay_us);
186 /* CS is negated on Tegra, so drive a 1 to get a 0 */
187 setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
190 static void spi_cs_deactivate(struct udevice *dev)
192 struct udevice *bus = dev->parent;
193 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
194 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
196 /* CS is negated on Tegra, so drive a 0 to get a 1 */
197 clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
199 /* Remember time of this transaction so we can honour the bus delay */
200 if (pdata->deactivate_delay_us)
201 priv->last_transaction_us = timer_get_us();
204 static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
205 const void *data_out, void *data_in,
208 struct udevice *bus = dev->parent;
209 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
210 struct spi_regs *regs = priv->regs;
211 u32 reg, tmpdout, tmpdin = 0;
212 const u8 *dout = data_out;
217 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
218 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
221 num_bytes = bitlen / 8;
225 reg = readl(®s->status);
226 writel(reg, ®s->status); /* Clear all SPI events via R/W */
227 debug("spi_xfer entry: STATUS = %08x\n", reg);
229 reg = readl(®s->command);
230 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
231 writel(reg, ®s->command);
232 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
234 if (flags & SPI_XFER_BEGIN)
235 spi_cs_activate(dev);
237 /* handle data in 32-bit chunks */
238 while (num_bytes > 0) {
244 bytes = (num_bytes > 4) ? 4 : num_bytes;
247 for (i = 0; i < bytes; ++i)
248 tmpdout = (tmpdout << 8) | dout[i];
255 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK,
257 writel(tmpdout, ®s->tx_fifo);
258 setbits_le32(®s->command, SPI_CMD_GO);
261 * Wait for SPI transmit FIFO to empty, or to time out.
262 * The RX FIFO status will be read and cleared last
264 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
267 status = readl(®s->status);
269 /* We can exit when we've had both RX and TX activity */
270 if (is_read && (status & SPI_STAT_TXF_EMPTY))
273 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
277 else if (!(status & SPI_STAT_RXF_EMPTY)) {
278 tmpdin = readl(®s->rx_fifo);
281 /* swap bytes read in */
283 for (i = bytes - 1; i >= 0; --i) {
284 din[i] = tmpdin & 0xff;
292 if (tm >= SPI_TIMEOUT)
295 /* clear ACK RDY, etc. bits */
296 writel(readl(®s->status), ®s->status);
299 if (flags & SPI_XFER_END)
300 spi_cs_deactivate(dev);
302 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
303 tmpdin, readl(®s->status));
306 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
313 static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
315 struct tegra_spi_platdata *plat = bus->platdata;
316 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
318 if (speed > plat->frequency)
319 speed = plat->frequency;
321 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
326 static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
328 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
331 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
336 static const struct dm_spi_ops tegra20_sflash_ops = {
337 .claim_bus = tegra20_sflash_claim_bus,
338 .xfer = tegra20_sflash_xfer,
339 .set_speed = tegra20_sflash_set_speed,
340 .set_mode = tegra20_sflash_set_mode,
341 .cs_info = tegra20_sflash_cs_info,
344 static const struct udevice_id tegra20_sflash_ids[] = {
345 { .compatible = "nvidia,tegra20-sflash" },
349 U_BOOT_DRIVER(tegra20_sflash) = {
350 .name = "tegra20_sflash",
352 .of_match = tegra20_sflash_ids,
353 .ops = &tegra20_sflash_ops,
354 .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
355 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
356 .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
357 .probe = tegra20_sflash_probe,