drivers/spi/stm32_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016
   4  *
   5  * Michael Kurz, <michi.kurz@gmail.com>
   6  *
   7  * STM32 QSPI driver
   8  */
   9
  10 #include <common.h>
  11 #include <clk.h>
  12 #include <log.h>
  13 #include <reset.h>
  14 #include <spi-mem.h>
  15 #include <dm/device_compat.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/ioport.h>
  18 #include <linux/sizes.h>
  19
  20 struct stm32_qspi_regs {
  21         u32 cr;         /* 0x00 */
  22         u32 dcr;        /* 0x04 */
  23         u32 sr;         /* 0x08 */
  24         u32 fcr;        /* 0x0C */
  25         u32 dlr;        /* 0x10 */
  26         u32 ccr;        /* 0x14 */
  27         u32 ar;         /* 0x18 */
  28         u32 abr;        /* 0x1C */
  29         u32 dr;         /* 0x20 */
  30         u32 psmkr;      /* 0x24 */
  31         u32 psmar;      /* 0x28 */
  32         u32 pir;        /* 0x2C */
  33         u32 lptr;       /* 0x30 */
  34 };
  35
  36 /*
  37  * QUADSPI control register
  38  */
  39 #define STM32_QSPI_CR_EN                BIT(0)
  40 #define STM32_QSPI_CR_ABORT             BIT(1)
  41 #define STM32_QSPI_CR_DMAEN             BIT(2)
  42 #define STM32_QSPI_CR_TCEN              BIT(3)
  43 #define STM32_QSPI_CR_SSHIFT            BIT(4)
  44 #define STM32_QSPI_CR_DFM               BIT(6)
  45 #define STM32_QSPI_CR_FSEL              BIT(7)
  46 #define STM32_QSPI_CR_FTHRES_SHIFT      8
  47 #define STM32_QSPI_CR_TEIE              BIT(16)
  48 #define STM32_QSPI_CR_TCIE              BIT(17)
  49 #define STM32_QSPI_CR_FTIE              BIT(18)
  50 #define STM32_QSPI_CR_SMIE              BIT(19)
  51 #define STM32_QSPI_CR_TOIE              BIT(20)
  52 #define STM32_QSPI_CR_APMS              BIT(22)
  53 #define STM32_QSPI_CR_PMM               BIT(23)
  54 #define STM32_QSPI_CR_PRESCALER_MASK    GENMASK(7, 0)
  55 #define STM32_QSPI_CR_PRESCALER_SHIFT   24
  56
  57 /*
  58  * QUADSPI device configuration register
  59  */
  60 #define STM32_QSPI_DCR_CKMODE           BIT(0)
  61 #define STM32_QSPI_DCR_CSHT_MASK        GENMASK(2, 0)
  62 #define STM32_QSPI_DCR_CSHT_SHIFT       8
  63 #define STM32_QSPI_DCR_FSIZE_MASK       GENMASK(4, 0)
  64 #define STM32_QSPI_DCR_FSIZE_SHIFT      16
  65
  66 /*
  67  * QUADSPI status register
  68  */
  69 #define STM32_QSPI_SR_TEF               BIT(0)
  70 #define STM32_QSPI_SR_TCF               BIT(1)
  71 #define STM32_QSPI_SR_FTF               BIT(2)
  72 #define STM32_QSPI_SR_SMF               BIT(3)
  73 #define STM32_QSPI_SR_TOF               BIT(4)
  74 #define STM32_QSPI_SR_BUSY              BIT(5)
  75
  76 /*
  77  * QUADSPI flag clear register
  78  */
  79 #define STM32_QSPI_FCR_CTEF             BIT(0)
  80 #define STM32_QSPI_FCR_CTCF             BIT(1)
  81 #define STM32_QSPI_FCR_CSMF             BIT(3)
  82 #define STM32_QSPI_FCR_CTOF             BIT(4)
  83
  84 /*
  85  * QUADSPI communication configuration register
  86  */
  87 #define STM32_QSPI_CCR_DDRM             BIT(31)
  88 #define STM32_QSPI_CCR_DHHC             BIT(30)
  89 #define STM32_QSPI_CCR_SIOO             BIT(28)
  90 #define STM32_QSPI_CCR_FMODE_SHIFT      26
  91 #define STM32_QSPI_CCR_DMODE_SHIFT      24
  92 #define STM32_QSPI_CCR_DCYC_SHIFT       18
  93 #define STM32_QSPI_CCR_ABSIZE_SHIFT     16
  94 #define STM32_QSPI_CCR_ABMODE_SHIFT     14
  95 #define STM32_QSPI_CCR_ADSIZE_SHIFT     12
  96 #define STM32_QSPI_CCR_ADMODE_SHIFT     10
  97 #define STM32_QSPI_CCR_IMODE_SHIFT      8
  98
  99 #define STM32_QSPI_CCR_IND_WRITE        0
 100 #define STM32_QSPI_CCR_IND_READ         1
 101 #define STM32_QSPI_CCR_MEM_MAP          3
 102
 103 #define STM32_QSPI_MAX_MMAP_SZ          SZ_256M
 104 #define STM32_QSPI_MAX_CHIP             2
 105
 106 #define STM32_QSPI_FIFO_TIMEOUT_US      30000
 107 #define STM32_QSPI_CMD_TIMEOUT_US       1000000
 108 #define STM32_BUSY_TIMEOUT_US           100000
 109 #define STM32_ABT_TIMEOUT_US            100000
 110
 111 struct stm32_qspi_flash {
 112         u32 cr;
 113         u32 dcr;
 114         bool initialized;
 115 };
 116
 117 struct stm32_qspi_priv {
 118         struct stm32_qspi_regs *regs;
 119         struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
 120         void __iomem *mm_base;
 121         resource_size_t mm_size;
 122         ulong clock_rate;
 123         int cs_used;
 124 };
 125
 126 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
 127 {
 128         u32 sr;
 129         int ret;
 130
 131         ret = readl_poll_timeout(&priv->regs->sr, sr,
 132                                  !(sr & STM32_QSPI_SR_BUSY),
 133                                  STM32_BUSY_TIMEOUT_US);
 134         if (ret)
 135                 pr_err("busy timeout (stat:%#x)\n", sr);
 136
 137         return ret;
 138 }
 139
 140 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
 141                                 const struct spi_mem_op *op)
 142 {
 143         u32 sr;
 144         int ret;
 145
 146         if (!op->data.nbytes)
 147                 return _stm32_qspi_wait_for_not_busy(priv);
 148
 149         ret = readl_poll_timeout(&priv->regs->sr, sr,
 150                                  sr & STM32_QSPI_SR_TCF,
 151                                  STM32_QSPI_CMD_TIMEOUT_US);
 152         if (ret) {
 153                 pr_err("cmd timeout (stat:%#x)\n", sr);
 154         } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
 155                 pr_err("transfer error (stat:%#x)\n", sr);
 156                 ret = -EIO;
 157         }
 158
 159         /* clear flags */
 160         writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
 161
 162         return ret;
 163 }
 164
 165 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 166 {
 167         *val = readb(addr);
 168 }
 169
 170 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 171 {
 172         writeb(*val, addr);
 173 }
 174
 175 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
 176                             const struct spi_mem_op *op)
 177 {
 178         void (*fifo)(u8 *val, void __iomem *addr);
 179         u32 len = op->data.nbytes, sr;
 180         u8 *buf;
 181         int ret;
 182
 183         if (op->data.dir == SPI_MEM_DATA_IN) {
 184                 fifo = _stm32_qspi_read_fifo;
 185                 buf = op->data.buf.in;
 186
 187         } else {
 188                 fifo = _stm32_qspi_write_fifo;
 189                 buf = (u8 *)op->data.buf.out;
 190         }
 191
 192         while (len--) {
 193                 ret = readl_poll_timeout(&priv->regs->sr, sr,
 194                                          sr & STM32_QSPI_SR_FTF,
 195                                          STM32_QSPI_FIFO_TIMEOUT_US);
 196                 if (ret) {
 197                         pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
 198                         return ret;
 199                 }
 200
 201                 fifo(buf++, &priv->regs->dr);
 202         }
 203
 204         return 0;
 205 }
 206
 207 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
 208                          const struct spi_mem_op *op)
 209 {
 210         memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
 211                       op->data.nbytes);
 212
 213         return 0;
 214 }
 215
 216 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
 217                           const struct spi_mem_op *op,
 218                           u8 mode)
 219 {
 220         if (!op->data.nbytes)
 221                 return 0;
 222
 223         if (mode == STM32_QSPI_CCR_MEM_MAP)
 224                 return stm32_qspi_mm(priv, op);
 225
 226         return _stm32_qspi_poll(priv, op);
 227 }
 228
 229 static int _stm32_qspi_get_mode(u8 buswidth)
 230 {
 231         if (buswidth == 4)
 232                 return 3;
 233
 234         return buswidth;
 235 }
 236
 237 static int stm32_qspi_exec_op(struct spi_slave *slave,
 238                               const struct spi_mem_op *op)
 239 {
 240         struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
 241         u32 cr, ccr, addr_max;
 242         u8 mode = STM32_QSPI_CCR_IND_WRITE;
 243         int timeout, ret;
 244
 245         debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
 246               __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 247               op->dummy.buswidth, op->data.buswidth,
 248               op->addr.val, op->data.nbytes);
 249
 250         ret = _stm32_qspi_wait_for_not_busy(priv);
 251         if (ret)
 252                 return ret;
 253
 254         addr_max = op->addr.val + op->data.nbytes + 1;
 255
 256         if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
 257                 if (addr_max < priv->mm_size && op->addr.buswidth)
 258                         mode = STM32_QSPI_CCR_MEM_MAP;
 259                 else
 260                         mode = STM32_QSPI_CCR_IND_READ;
 261         }
 262
 263         if (op->data.nbytes)
 264                 writel(op->data.nbytes - 1, &priv->regs->dlr);
 265
 266         ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
 267         ccr |= op->cmd.opcode;
 268         ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
 269                 << STM32_QSPI_CCR_IMODE_SHIFT);
 270
 271         if (op->addr.nbytes) {
 272                 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
 273                 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
 274                         << STM32_QSPI_CCR_ADMODE_SHIFT);
 275         }
 276
 277         if (op->dummy.buswidth && op->dummy.nbytes)
 278                 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
 279                         << STM32_QSPI_CCR_DCYC_SHIFT);
 280
 281         if (op->data.nbytes)
 282                 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
 283                         << STM32_QSPI_CCR_DMODE_SHIFT);
 284
 285         writel(ccr, &priv->regs->ccr);
 286
 287         if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
 288                 writel(op->addr.val, &priv->regs->ar);
 289
 290         ret = _stm32_qspi_tx(priv, op, mode);
 291         /*
 292          * Abort in:
 293          * -error case
 294          * -read memory map: prefetching must be stopped if we read the last
 295          *  byte of device (device size - fifo size). like device size is not
 296          *  knows, the prefetching is always stop.
 297          */
 298         if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
 299                 goto abort;
 300
 301         /* Wait end of tx in indirect mode */
 302         ret = _stm32_qspi_wait_cmd(priv, op);
 303         if (ret)
 304                 goto abort;
 305
 306         return 0;
 307
 308 abort:
 309         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
 310
 311         /* Wait clear of abort bit by hw */
 312         timeout = readl_poll_timeout(&priv->regs->cr, cr,
 313                                      !(cr & STM32_QSPI_CR_ABORT),
 314                                      STM32_ABT_TIMEOUT_US);
 315
 316         writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
 317
 318         if (ret || timeout)
 319                 pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
 320
 321         return ret;
 322 }
 323
 324 static int stm32_qspi_probe(struct udevice *bus)
 325 {
 326         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 327         struct resource res;
 328         struct clk clk;
 329         struct reset_ctl reset_ctl;
 330         int ret;
 331
 332         ret = dev_read_resource_byname(bus, "qspi", &res);
 333         if (ret) {
 334                 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
 335                 return ret;
 336         }
 337
 338         priv->regs = (struct stm32_qspi_regs *)res.start;
 339
 340         ret = dev_read_resource_byname(bus, "qspi_mm", &res);
 341         if (ret) {
 342                 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
 343                 return ret;
 344         }
 345
 346         priv->mm_base = (void __iomem *)res.start;
 347
 348         priv->mm_size = resource_size(&res);
 349         if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
 350                 return -EINVAL;
 351
 352         debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
 353               __func__, priv->regs, priv->mm_base, priv->mm_size);
 354
 355         ret = clk_get_by_index(bus, 0, &clk);
 356         if (ret < 0)
 357                 return ret;
 358
 359         ret = clk_enable(&clk);
 360         if (ret) {
 361                 dev_err(bus, "failed to enable clock\n");
 362                 return ret;
 363         }
 364
 365         priv->clock_rate = clk_get_rate(&clk);
 366         if (!priv->clock_rate) {
 367                 clk_disable(&clk);
 368                 return -EINVAL;
 369         }
 370
 371         ret = reset_get_by_index(bus, 0, &reset_ctl);
 372         if (ret) {
 373                 if (ret != -ENOENT) {
 374                         dev_err(bus, "failed to get reset\n");
 375                         clk_disable(&clk);
 376                         return ret;
 377                 }
 378         } else {
 379                 /* Reset QSPI controller */
 380                 reset_assert(&reset_ctl);
 381                 udelay(2);
 382                 reset_deassert(&reset_ctl);
 383         }
 384
 385         priv->cs_used = -1;
 386
 387         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 388
 389         /* Set dcr fsize to max address */
 390         setbits_le32(&priv->regs->dcr,
 391                      STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
 392
 393         return 0;
 394 }
 395
 396 static int stm32_qspi_claim_bus(struct udevice *dev)
 397 {
 398         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 399         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 400         int slave_cs = slave_plat->cs;
 401
 402         if (slave_cs >= STM32_QSPI_MAX_CHIP)
 403                 return -ENODEV;
 404
 405         if (priv->cs_used != slave_cs) {
 406                 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
 407
 408                 priv->cs_used = slave_cs;
 409
 410                 if (flash->initialized) {
 411                         /* Set the configuration: speed + cs */
 412                         writel(flash->cr, &priv->regs->cr);
 413                         writel(flash->dcr, &priv->regs->dcr);
 414                 } else {
 415                         /* Set chip select */
 416                         clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
 417                                         priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
 418
 419                         /* Save the configuration: speed + cs */
 420                         flash->cr = readl(&priv->regs->cr);
 421                         flash->dcr = readl(&priv->regs->dcr);
 422
 423                         flash->initialized = true;
 424                 }
 425         }
 426
 427         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 428
 429         return 0;
 430 }
 431
 432 static int stm32_qspi_release_bus(struct udevice *dev)
 433 {
 434         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 435
 436         clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 437
 438         return 0;
 439 }
 440
 441 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 442 {
 443         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 444         u32 qspi_clk = priv->clock_rate;
 445         u32 prescaler = 255;
 446         u32 csht;
 447         int ret;
 448
 449         if (speed > 0) {
 450                 prescaler = 0;
 451                 if (qspi_clk) {
 452                         prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
 453                         if (prescaler > 255)
 454                                 prescaler = 255;
 455                 }
 456         }
 457
 458         csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
 459         csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 460
 461         ret = _stm32_qspi_wait_for_not_busy(priv);
 462         if (ret)
 463                 return ret;
 464
 465         clrsetbits_le32(&priv->regs->cr,
 466                         STM32_QSPI_CR_PRESCALER_MASK <<
 467                         STM32_QSPI_CR_PRESCALER_SHIFT,
 468                         prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 469
 470         clrsetbits_le32(&priv->regs->dcr,
 471                         STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
 472                         csht << STM32_QSPI_DCR_CSHT_SHIFT);
 473
 474         debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
 475               (qspi_clk / (prescaler + 1)));
 476
 477         return 0;
 478 }
 479
 480 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
 481 {
 482         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 483         int ret;
 484
 485         ret = _stm32_qspi_wait_for_not_busy(priv);
 486         if (ret)
 487                 return ret;
 488
 489         if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
 490                 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 491         else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
 492                 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 493         else
 494                 return -ENODEV;
 495
 496         if (mode & SPI_CS_HIGH)
 497                 return -ENODEV;
 498
 499         debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
 500
 501         if (mode & SPI_RX_QUAD)
 502                 debug("quad, tx: ");
 503         else if (mode & SPI_RX_DUAL)
 504                 debug("dual, tx: ");
 505         else
 506                 debug("single, tx: ");
 507
 508         if (mode & SPI_TX_QUAD)
 509                 debug("quad\n");
 510         else if (mode & SPI_TX_DUAL)
 511                 debug("dual\n");
 512         else
 513                 debug("single\n");
 514
 515         return 0;
 516 }
 517
 518 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
 519         .exec_op = stm32_qspi_exec_op,
 520 };
 521
 522 static const struct dm_spi_ops stm32_qspi_ops = {
 523         .claim_bus      = stm32_qspi_claim_bus,
 524         .release_bus    = stm32_qspi_release_bus,
 525         .set_speed      = stm32_qspi_set_speed,
 526         .set_mode       = stm32_qspi_set_mode,
 527         .mem_ops        = &stm32_qspi_mem_ops,
 528 };
 529
 530 static const struct udevice_id stm32_qspi_ids[] = {
 531         { .compatible = "st,stm32f469-qspi" },
 532         { }
 533 };
 534
 535 U_BOOT_DRIVER(stm32_qspi) = {
 536         .name = "stm32_qspi",
 537         .id = UCLASS_SPI,
 538         .of_match = stm32_qspi_ids,
 539         .ops = &stm32_qspi_ops,
 540         .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
 541         .probe = stm32_qspi_probe,
 542 };