drivers/spi/stm32_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016
   4  *
   5  * Michael Kurz, <michi.kurz@gmail.com>
   6  *
   7  * STM32 QSPI driver
   8  */
   9
  10 #include <common.h>
  11 #include <clk.h>
  12 #include <log.h>
  13 #include <reset.h>
  14 #include <spi-mem.h>
  15 #include <dm/device_compat.h>
  16 #include <linux/delay.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/ioport.h>
  19 #include <linux/sizes.h>
  20
  21 struct stm32_qspi_regs {
  22         u32 cr;         /* 0x00 */
  23         u32 dcr;        /* 0x04 */
  24         u32 sr;         /* 0x08 */
  25         u32 fcr;        /* 0x0C */
  26         u32 dlr;        /* 0x10 */
  27         u32 ccr;        /* 0x14 */
  28         u32 ar;         /* 0x18 */
  29         u32 abr;        /* 0x1C */
  30         u32 dr;         /* 0x20 */
  31         u32 psmkr;      /* 0x24 */
  32         u32 psmar;      /* 0x28 */
  33         u32 pir;        /* 0x2C */
  34         u32 lptr;       /* 0x30 */
  35 };
  36
  37 /*
  38  * QUADSPI control register
  39  */
  40 #define STM32_QSPI_CR_EN                BIT(0)
  41 #define STM32_QSPI_CR_ABORT             BIT(1)
  42 #define STM32_QSPI_CR_DMAEN             BIT(2)
  43 #define STM32_QSPI_CR_TCEN              BIT(3)
  44 #define STM32_QSPI_CR_SSHIFT            BIT(4)
  45 #define STM32_QSPI_CR_DFM               BIT(6)
  46 #define STM32_QSPI_CR_FSEL              BIT(7)
  47 #define STM32_QSPI_CR_FTHRES_SHIFT      8
  48 #define STM32_QSPI_CR_TEIE              BIT(16)
  49 #define STM32_QSPI_CR_TCIE              BIT(17)
  50 #define STM32_QSPI_CR_FTIE              BIT(18)
  51 #define STM32_QSPI_CR_SMIE              BIT(19)
  52 #define STM32_QSPI_CR_TOIE              BIT(20)
  53 #define STM32_QSPI_CR_APMS              BIT(22)
  54 #define STM32_QSPI_CR_PMM               BIT(23)
  55 #define STM32_QSPI_CR_PRESCALER_MASK    GENMASK(7, 0)
  56 #define STM32_QSPI_CR_PRESCALER_SHIFT   24
  57
  58 /*
  59  * QUADSPI device configuration register
  60  */
  61 #define STM32_QSPI_DCR_CKMODE           BIT(0)
  62 #define STM32_QSPI_DCR_CSHT_MASK        GENMASK(2, 0)
  63 #define STM32_QSPI_DCR_CSHT_SHIFT       8
  64 #define STM32_QSPI_DCR_FSIZE_MASK       GENMASK(4, 0)
  65 #define STM32_QSPI_DCR_FSIZE_SHIFT      16
  66
  67 /*
  68  * QUADSPI status register
  69  */
  70 #define STM32_QSPI_SR_TEF               BIT(0)
  71 #define STM32_QSPI_SR_TCF               BIT(1)
  72 #define STM32_QSPI_SR_FTF               BIT(2)
  73 #define STM32_QSPI_SR_SMF               BIT(3)
  74 #define STM32_QSPI_SR_TOF               BIT(4)
  75 #define STM32_QSPI_SR_BUSY              BIT(5)
  76
  77 /*
  78  * QUADSPI flag clear register
  79  */
  80 #define STM32_QSPI_FCR_CTEF             BIT(0)
  81 #define STM32_QSPI_FCR_CTCF             BIT(1)
  82 #define STM32_QSPI_FCR_CSMF             BIT(3)
  83 #define STM32_QSPI_FCR_CTOF             BIT(4)
  84
  85 /*
  86  * QUADSPI communication configuration register
  87  */
  88 #define STM32_QSPI_CCR_DDRM             BIT(31)
  89 #define STM32_QSPI_CCR_DHHC             BIT(30)
  90 #define STM32_QSPI_CCR_SIOO             BIT(28)
  91 #define STM32_QSPI_CCR_FMODE_SHIFT      26
  92 #define STM32_QSPI_CCR_DMODE_SHIFT      24
  93 #define STM32_QSPI_CCR_DCYC_SHIFT       18
  94 #define STM32_QSPI_CCR_ABSIZE_SHIFT     16
  95 #define STM32_QSPI_CCR_ABMODE_SHIFT     14
  96 #define STM32_QSPI_CCR_ADSIZE_SHIFT     12
  97 #define STM32_QSPI_CCR_ADMODE_SHIFT     10
  98 #define STM32_QSPI_CCR_IMODE_SHIFT      8
  99
 100 #define STM32_QSPI_CCR_IND_WRITE        0
 101 #define STM32_QSPI_CCR_IND_READ         1
 102 #define STM32_QSPI_CCR_MEM_MAP          3
 103
 104 #define STM32_QSPI_MAX_MMAP_SZ          SZ_256M
 105 #define STM32_QSPI_MAX_CHIP             2
 106
 107 #define STM32_QSPI_FIFO_TIMEOUT_US      30000
 108 #define STM32_QSPI_CMD_TIMEOUT_US       1000000
 109 #define STM32_BUSY_TIMEOUT_US           100000
 110 #define STM32_ABT_TIMEOUT_US            100000
 111
 112 struct stm32_qspi_flash {
 113         u32 cr;
 114         u32 dcr;
 115         bool initialized;
 116 };
 117
 118 struct stm32_qspi_priv {
 119         struct stm32_qspi_regs *regs;
 120         struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP];
 121         void __iomem *mm_base;
 122         resource_size_t mm_size;
 123         ulong clock_rate;
 124         int cs_used;
 125 };
 126
 127 static int _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
 128 {
 129         u32 sr;
 130         int ret;
 131
 132         ret = readl_poll_timeout(&priv->regs->sr, sr,
 133                                  !(sr & STM32_QSPI_SR_BUSY),
 134                                  STM32_BUSY_TIMEOUT_US);
 135         if (ret)
 136                 pr_err("busy timeout (stat:%#x)\n", sr);
 137
 138         return ret;
 139 }
 140
 141 static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
 142                                 const struct spi_mem_op *op)
 143 {
 144         u32 sr;
 145         int ret;
 146
 147         if (!op->data.nbytes)
 148                 return _stm32_qspi_wait_for_not_busy(priv);
 149
 150         ret = readl_poll_timeout(&priv->regs->sr, sr,
 151                                  sr & STM32_QSPI_SR_TCF,
 152                                  STM32_QSPI_CMD_TIMEOUT_US);
 153         if (ret) {
 154                 pr_err("cmd timeout (stat:%#x)\n", sr);
 155         } else if (readl(&priv->regs->sr) & STM32_QSPI_SR_TEF) {
 156                 pr_err("transfer error (stat:%#x)\n", sr);
 157                 ret = -EIO;
 158         }
 159
 160         /* clear flags */
 161         writel(STM32_QSPI_FCR_CTCF | STM32_QSPI_FCR_CTEF, &priv->regs->fcr);
 162
 163         return ret;
 164 }
 165
 166 static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
 167 {
 168         *val = readb(addr);
 169 }
 170
 171 static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
 172 {
 173         writeb(*val, addr);
 174 }
 175
 176 static int _stm32_qspi_poll(struct stm32_qspi_priv *priv,
 177                             const struct spi_mem_op *op)
 178 {
 179         void (*fifo)(u8 *val, void __iomem *addr);
 180         u32 len = op->data.nbytes, sr;
 181         u8 *buf;
 182         int ret;
 183
 184         if (op->data.dir == SPI_MEM_DATA_IN) {
 185                 fifo = _stm32_qspi_read_fifo;
 186                 buf = op->data.buf.in;
 187
 188         } else {
 189                 fifo = _stm32_qspi_write_fifo;
 190                 buf = (u8 *)op->data.buf.out;
 191         }
 192
 193         while (len--) {
 194                 ret = readl_poll_timeout(&priv->regs->sr, sr,
 195                                          sr & STM32_QSPI_SR_FTF,
 196                                          STM32_QSPI_FIFO_TIMEOUT_US);
 197                 if (ret) {
 198                         pr_err("fifo timeout (len:%d stat:%#x)\n", len, sr);
 199                         return ret;
 200                 }
 201
 202                 fifo(buf++, &priv->regs->dr);
 203         }
 204
 205         return 0;
 206 }
 207
 208 static int stm32_qspi_mm(struct stm32_qspi_priv *priv,
 209                          const struct spi_mem_op *op)
 210 {
 211         memcpy_fromio(op->data.buf.in, priv->mm_base + op->addr.val,
 212                       op->data.nbytes);
 213
 214         return 0;
 215 }
 216
 217 static int _stm32_qspi_tx(struct stm32_qspi_priv *priv,
 218                           const struct spi_mem_op *op,
 219                           u8 mode)
 220 {
 221         if (!op->data.nbytes)
 222                 return 0;
 223
 224         if (mode == STM32_QSPI_CCR_MEM_MAP)
 225                 return stm32_qspi_mm(priv, op);
 226
 227         return _stm32_qspi_poll(priv, op);
 228 }
 229
 230 static int _stm32_qspi_get_mode(u8 buswidth)
 231 {
 232         if (buswidth == 4)
 233                 return 3;
 234
 235         return buswidth;
 236 }
 237
 238 static int stm32_qspi_exec_op(struct spi_slave *slave,
 239                               const struct spi_mem_op *op)
 240 {
 241         struct stm32_qspi_priv *priv = dev_get_priv(slave->dev->parent);
 242         u32 cr, ccr, addr_max;
 243         u8 mode = STM32_QSPI_CCR_IND_WRITE;
 244         int timeout, ret;
 245
 246         debug("%s: cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
 247               __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
 248               op->dummy.buswidth, op->data.buswidth,
 249               op->addr.val, op->data.nbytes);
 250
 251         ret = _stm32_qspi_wait_for_not_busy(priv);
 252         if (ret)
 253                 return ret;
 254
 255         addr_max = op->addr.val + op->data.nbytes + 1;
 256
 257         if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes) {
 258                 if (addr_max < priv->mm_size && op->addr.buswidth)
 259                         mode = STM32_QSPI_CCR_MEM_MAP;
 260                 else
 261                         mode = STM32_QSPI_CCR_IND_READ;
 262         }
 263
 264         if (op->data.nbytes)
 265                 writel(op->data.nbytes - 1, &priv->regs->dlr);
 266
 267         ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
 268         ccr |= op->cmd.opcode;
 269         ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
 270                 << STM32_QSPI_CCR_IMODE_SHIFT);
 271
 272         if (op->addr.nbytes) {
 273                 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
 274                 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
 275                         << STM32_QSPI_CCR_ADMODE_SHIFT);
 276         }
 277
 278         if (op->dummy.buswidth && op->dummy.nbytes)
 279                 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
 280                         << STM32_QSPI_CCR_DCYC_SHIFT);
 281
 282         if (op->data.nbytes)
 283                 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
 284                         << STM32_QSPI_CCR_DMODE_SHIFT);
 285
 286         writel(ccr, &priv->regs->ccr);
 287
 288         if (op->addr.nbytes && mode != STM32_QSPI_CCR_MEM_MAP)
 289                 writel(op->addr.val, &priv->regs->ar);
 290
 291         ret = _stm32_qspi_tx(priv, op, mode);
 292         /*
 293          * Abort in:
 294          * -error case
 295          * -read memory map: prefetching must be stopped if we read the last
 296          *  byte of device (device size - fifo size). like device size is not
 297          *  knows, the prefetching is always stop.
 298          */
 299         if (ret || mode == STM32_QSPI_CCR_MEM_MAP)
 300                 goto abort;
 301
 302         /* Wait end of tx in indirect mode */
 303         ret = _stm32_qspi_wait_cmd(priv, op);
 304         if (ret)
 305                 goto abort;
 306
 307         return 0;
 308
 309 abort:
 310         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
 311
 312         /* Wait clear of abort bit by hw */
 313         timeout = readl_poll_timeout(&priv->regs->cr, cr,
 314                                      !(cr & STM32_QSPI_CR_ABORT),
 315                                      STM32_ABT_TIMEOUT_US);
 316
 317         writel(STM32_QSPI_FCR_CTCF, &priv->regs->fcr);
 318
 319         if (ret || timeout)
 320                 pr_err("%s ret:%d abort timeout:%d\n", __func__, ret, timeout);
 321
 322         return ret;
 323 }
 324
 325 static int stm32_qspi_probe(struct udevice *bus)
 326 {
 327         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 328         struct resource res;
 329         struct clk clk;
 330         struct reset_ctl reset_ctl;
 331         int ret;
 332
 333         ret = dev_read_resource_byname(bus, "qspi", &res);
 334         if (ret) {
 335                 dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret);
 336                 return ret;
 337         }
 338
 339         priv->regs = (struct stm32_qspi_regs *)res.start;
 340
 341         ret = dev_read_resource_byname(bus, "qspi_mm", &res);
 342         if (ret) {
 343                 dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret);
 344                 return ret;
 345         }
 346
 347         priv->mm_base = (void __iomem *)res.start;
 348
 349         priv->mm_size = resource_size(&res);
 350         if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ)
 351                 return -EINVAL;
 352
 353         debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n",
 354               __func__, priv->regs, priv->mm_base, priv->mm_size);
 355
 356         ret = clk_get_by_index(bus, 0, &clk);
 357         if (ret < 0)
 358                 return ret;
 359
 360         ret = clk_enable(&clk);
 361         if (ret) {
 362                 dev_err(bus, "failed to enable clock\n");
 363                 return ret;
 364         }
 365
 366         priv->clock_rate = clk_get_rate(&clk);
 367         if (!priv->clock_rate) {
 368                 clk_disable(&clk);
 369                 return -EINVAL;
 370         }
 371
 372         ret = reset_get_by_index(bus, 0, &reset_ctl);
 373         if (ret) {
 374                 if (ret != -ENOENT) {
 375                         dev_err(bus, "failed to get reset\n");
 376                         clk_disable(&clk);
 377                         return ret;
 378                 }
 379         } else {
 380                 /* Reset QSPI controller */
 381                 reset_assert(&reset_ctl);
 382                 udelay(2);
 383                 reset_deassert(&reset_ctl);
 384         }
 385
 386         priv->cs_used = -1;
 387
 388         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 389
 390         /* Set dcr fsize to max address */
 391         setbits_le32(&priv->regs->dcr,
 392                      STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT);
 393
 394         return 0;
 395 }
 396
 397 static int stm32_qspi_claim_bus(struct udevice *dev)
 398 {
 399         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 400         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 401         int slave_cs = slave_plat->cs;
 402
 403         if (slave_cs >= STM32_QSPI_MAX_CHIP)
 404                 return -ENODEV;
 405
 406         if (priv->cs_used != slave_cs) {
 407                 struct stm32_qspi_flash *flash = &priv->flash[slave_cs];
 408
 409                 priv->cs_used = slave_cs;
 410
 411                 if (flash->initialized) {
 412                         /* Set the configuration: speed + cs */
 413                         writel(flash->cr, &priv->regs->cr);
 414                         writel(flash->dcr, &priv->regs->dcr);
 415                 } else {
 416                         /* Set chip select */
 417                         clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
 418                                         priv->cs_used ? STM32_QSPI_CR_FSEL : 0);
 419
 420                         /* Save the configuration: speed + cs */
 421                         flash->cr = readl(&priv->regs->cr);
 422                         flash->dcr = readl(&priv->regs->dcr);
 423
 424                         flash->initialized = true;
 425                 }
 426         }
 427
 428         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 429
 430         return 0;
 431 }
 432
 433 static int stm32_qspi_release_bus(struct udevice *dev)
 434 {
 435         struct stm32_qspi_priv *priv = dev_get_priv(dev->parent);
 436
 437         clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 438
 439         return 0;
 440 }
 441
 442 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 443 {
 444         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 445         u32 qspi_clk = priv->clock_rate;
 446         u32 prescaler = 255;
 447         u32 csht;
 448         int ret;
 449
 450         if (speed > 0) {
 451                 prescaler = 0;
 452                 if (qspi_clk) {
 453                         prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
 454                         if (prescaler > 255)
 455                                 prescaler = 255;
 456                 }
 457         }
 458
 459         csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
 460         csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 461
 462         ret = _stm32_qspi_wait_for_not_busy(priv);
 463         if (ret)
 464                 return ret;
 465
 466         clrsetbits_le32(&priv->regs->cr,
 467                         STM32_QSPI_CR_PRESCALER_MASK <<
 468                         STM32_QSPI_CR_PRESCALER_SHIFT,
 469                         prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 470
 471         clrsetbits_le32(&priv->regs->dcr,
 472                         STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
 473                         csht << STM32_QSPI_DCR_CSHT_SHIFT);
 474
 475         debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
 476               (qspi_clk / (prescaler + 1)));
 477
 478         return 0;
 479 }
 480
 481 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
 482 {
 483         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 484         int ret;
 485
 486         ret = _stm32_qspi_wait_for_not_busy(priv);
 487         if (ret)
 488                 return ret;
 489
 490         if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
 491                 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 492         else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
 493                 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 494         else
 495                 return -ENODEV;
 496
 497         if (mode & SPI_CS_HIGH)
 498                 return -ENODEV;
 499
 500         debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
 501
 502         if (mode & SPI_RX_QUAD)
 503                 debug("quad, tx: ");
 504         else if (mode & SPI_RX_DUAL)
 505                 debug("dual, tx: ");
 506         else
 507                 debug("single, tx: ");
 508
 509         if (mode & SPI_TX_QUAD)
 510                 debug("quad\n");
 511         else if (mode & SPI_TX_DUAL)
 512                 debug("dual\n");
 513         else
 514                 debug("single\n");
 515
 516         return 0;
 517 }
 518
 519 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
 520         .exec_op = stm32_qspi_exec_op,
 521 };
 522
 523 static const struct dm_spi_ops stm32_qspi_ops = {
 524         .claim_bus      = stm32_qspi_claim_bus,
 525         .release_bus    = stm32_qspi_release_bus,
 526         .set_speed      = stm32_qspi_set_speed,
 527         .set_mode       = stm32_qspi_set_mode,
 528         .mem_ops        = &stm32_qspi_mem_ops,
 529 };
 530
 531 static const struct udevice_id stm32_qspi_ids[] = {
 532         { .compatible = "st,stm32f469-qspi" },
 533         { }
 534 };
 535
 536 U_BOOT_DRIVER(stm32_qspi) = {
 537         .name = "stm32_qspi",
 538         .id = UCLASS_SPI,
 539         .of_match = stm32_qspi_ids,
 540         .ops = &stm32_qspi_ops,
 541         .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
 542         .probe = stm32_qspi_probe,
 543 };